diff options
| author | Cedric Neveux <cedric.neveux@nxp.com> | 2020-08-04 16:22:21 +0200 |
|---|---|---|
| committer | Jérôme Forissier <jerome@forissier.org> | 2021-09-22 13:45:33 +0200 |
| commit | 046801b63e2e6500e43704c2c74922f86ab8176d (patch) | |
| tree | 30d05a37b3b6a6a370e40c3d3ec403a5640f1c25 | |
| parent | ae368944a4ee52694a5839a35479230a0a35c5f7 (diff) | |
drivers: caam: fix hal control split key detection
Fix the CAAM Version ID MS register address (CAAM Control + JR Offset).
Change HAL caam_hal_ctrl_splitkey() to read the parameters register LS
bit 14 (SPLIT_KEY) that indicates the support for the split key.
Fixes: 81ab436 ("drivers: caam: implement NXP CAAM Driver - HMAC")
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Acked-by: Jerome Forissier <jerome@forissier.org>
Acked-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
| -rw-r--r-- | core/drivers/crypto/caam/hal/common/hal_ctrl.c | 4 | ||||
| -rw-r--r-- | core/drivers/crypto/caam/hal/common/registers/version_regs.h | 20 |
2 files changed, 17 insertions, 7 deletions
diff --git a/core/drivers/crypto/caam/hal/common/hal_ctrl.c b/core/drivers/crypto/caam/hal/common/hal_ctrl.c index 859f5f6a..53a37600 100644 --- a/core/drivers/crypto/caam/hal/common/hal_ctrl.c +++ b/core/drivers/crypto/caam/hal/common/hal_ctrl.c @@ -73,9 +73,9 @@ uint8_t caam_hal_ctrl_hash_limit(vaddr_t baseaddr) bool caam_hal_ctrl_splitkey_support(vaddr_t baseaddr) { - uint32_t val = io_caam_read32(baseaddr + CAAMVID_MS); + uint32_t val = io_caam_read32(baseaddr + CTPR_LS); - return GET_CAAMVID_MS_MAJ_REV(val) >= 3; + return GET_CTPR_LS_SPLIT_KEY(val); } uint8_t caam_hal_ctrl_pknum(vaddr_t baseaddr) diff --git a/core/drivers/crypto/caam/hal/common/registers/version_regs.h b/core/drivers/crypto/caam/hal/common/registers/version_regs.h index 50cecdcd..96911173 100644 --- a/core/drivers/crypto/caam/hal/common/registers/version_regs.h +++ b/core/drivers/crypto/caam/hal/common/registers/version_regs.h @@ -9,16 +9,26 @@ #include <util.h> -/* CAAM Version ID */ -#define CAAMVID_MS 0x0BF8 -#define BM_CAAMVID_MS_MAJ_REV SHIFT_U32(0xFF, 8) -#define GET_CAAMVID_MS_MAJ_REV(val) (((val) & BM_CAAMVID_MS_MAJ_REV) >> 8) - /* Compile Time Parameters */ #define CTPR_MS 0x0FA8 #define BM_CTPR_MS_RNG_I SHIFT_U32(0x7, 8) #define GET_CTPR_MS_RNG_I(val) (((val) & BM_CTPR_MS_RNG_I) >> 8) +#define CTPR_LS 0x0FAC +#define BM_CTPR_LS_SPLIT_KEY BIT(14) +#define GET_CTPR_LS_SPLIT_KEY(val) (((val) & BM_CTPR_LS_SPLIT_KEY) >> 14) + +/* Secure Memory Version ID */ +#define SMVID_MS 0x0FD8 +#define BM_SMVID_MS_MAX_NPAG SHIFT_U32(0x3FF, 16) +#define GET_SMVID_MS_MAX_NPAG(val) (((val) & BM_SMVID_MS_MAX_NPAG) >> 16) +#define BM_SMVID_MS_NPRT SHIFT_U32(0xF, 12) +#define GET_SMVID_MS_NPRT(val) (((val) & BM_SMVID_MS_NPRT) >> 12) + +#define SMVID_LS 0x0FDC +#define BM_SMVID_LS_PSIZ SHIFT_U32(0x7, 16) +#define GET_SMVID_LS_PSIZ(val) (((val) & BM_SMVID_LS_PSIZ) >> 16) + /* CHA Cluster Block Version ID */ #define CCBVID 0x0FE4 #define BM_CCBVID_CAAM_ERA SHIFT_U32(0xFF, 24) |