diff options
| author | Loic Poulain <loic.poulain@linaro.org> | 2021-01-26 17:40:25 +0100 |
|---|---|---|
| committer | Loic Poulain <loic.poulain@linaro.org> | 2021-01-28 09:26:57 +0100 |
| commit | e3df5765e104e660a4a5e978a9a5db0265095566 (patch) | |
| tree | a9df6d4871d6e63046f24d7736e41d81ebf4ced4 | |
| parent | 5851c939a42688a7207088270134e297f5d9c743 (diff) | |
mhi: pci_generic: Add quectel EM1XXGR-L support
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
| -rw-r--r-- | drivers/bus/mhi/pci_generic.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 444693e3fd72..28cf934cbe6d 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -182,9 +182,45 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { .dma_data_width = 32 }; +static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { + /* MBIM only device */ + MHI_CHANNEL_CONFIG_UL(12, "MBIM", 8, 0), + MHI_CHANNEL_CONFIG_DL(13, "MBIM", 8, 0), + MHI_CHANNEL_CONFIG_UL(32, "DUN", 8, 0), + MHI_CHANNEL_CONFIG_DL(33, "DUN", 8, 0), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 1), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 2), +}; + +static struct mhi_event_config mhi_quectel_em1xx_events[] = { + MHI_EVENT_CONFIG_CTRL(0), + MHI_EVENT_CONFIG_HW_DATA(1, 100), + MHI_EVENT_CONFIG_HW_DATA(2, 101) +}; + +static struct mhi_controller_config modem_quectel_em1xx_config = { + .max_channels = 128, + .timeout_ms = 8000, + .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels), + .ch_cfg = mhi_quectel_em1xx_channels, + .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events), + .event_cfg = mhi_quectel_em1xx_events, +}; + +static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { + .name = "quectel-em1xx", + .config = &modem_quectel_em1xx_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32 +}; + static const struct pci_device_id mhi_pci_id_table[] = { { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, + { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL */ + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, + { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL */ + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { } }; MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); |