debian: Bump to 20.1.1-1+linaro1mesa-20.1.1-1+linaro1

Add patches to fix issues on a3xx.

Signed-off-by: Aníbal Limón <anibal.limon@linaro.org>

4 files changed, 197 insertions, 0 deletions

diff --git a/debian/changelog b/debian/changelog
index 0461da4735f..9c48d067192 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+mesa (20.1.1-1+linaro1) unstable; urgency=medium
+
+  * Add patch to fix freedreno a3xx issue.
+
+ -- Anibal Limon <anibal.limon@linaro.org>  Tue, 23 Jun 2020 11:01:29 -0500
+
 mesa (20.1.1-1) unstable; urgency=medium
 
   * New upstream release.
diff --git a/debian/patches/0001-freedreno_resource.c-fd_layout_resource_for_modifier.patch b/debian/patches/0001-freedreno_resource.c-fd_layout_resource_for_modifier.patch
new file mode 100644
index 00000000000..21ab478b399
--- /dev/null
+++ b/debian/patches/0001-freedreno_resource.c-fd_layout_resource_for_modifier.patch
@@ -0,0 +1,64 @@
+From db453f3f35578dd3ca6628b012650fc51ad1c6fb Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?An=C3=ADbal=20Lim=C3=B3n?= <anibal.limon@linaro.org>
+Date: Tue, 23 Jun 2020 10:58:18 -0500
+Subject: [PATCH 1/2] freedreno_resource.c: fd_layout_resource_for_modifier
+ return 0 for invalid
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+See,
+
+https://gitlab.freedesktop.org/mesa/mesa/-/issues/3154
+
+Fixes issues in a3xx,
+
+...
+linaro@linaro-alip:~$ DISPLAY=:0 glxinfo
+name of display: :0
+
+^C
+linaro@linaro-alip:~$ DISPLAY=:0 glxgears
+Running synchronized to the vertical refresh.  The framerate should be
+approximately the same as the monitor refresh rate.
+X Error of failed request:  BadAlloc (insufficient resources for operation)
+  Major opcode of failed request:  149 ()
+  Minor opcode of failed request:  7
+  Serial number of failed request:  44
+  Current serial number in output stream:  45
+linaro@linaro-alip:~$ DISPLAY=:0 glmark2
+=======================================================
+    glmark2 2014.03+git20150611.fa71af2d
+=======================================================
+    OpenGL Information
+    GL_VENDOR:     freedreno
+    GL_RENDERER:   FD307
+    GL_VERSION:    3.1 Mesa 20.1.1
+=======================================================
+X Error of failed request:  BadAlloc (insufficient resources for operation)
+  Major opcode of failed request:  149 ()
+  Minor opcode of failed request:  7
+  Serial number of failed request:  48
+  Current serial number in output stream:  49
+...
+
+Signed-off-by: Aníbal Limón <anibal.limon@linaro.org>
+---
+ src/gallium/drivers/freedreno/freedreno_resource.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/src/gallium/drivers/freedreno/freedreno_resource.c b/src/gallium/drivers/freedreno/freedreno_resource.c
+index 519cfbc1a5b..ad5011c97b5 100644
+--- a/src/gallium/drivers/freedreno/freedreno_resource.c
++++ b/src/gallium/drivers/freedreno/freedreno_resource.c
+@@ -1244,6 +1244,7 @@ fd_layout_resource_for_modifier(struct fd_resource *rsc, uint64_t modifier)
+ {
+ 	switch (modifier) {
+ 	case DRM_FORMAT_MOD_LINEAR:
++	case DRM_FORMAT_MOD_INVALID:
+ 		return 0;
+ 	default:
+ 		return -1;
+-- 
+2.27.0
+
diff --git a/debian/patches/0002-freedreno-ir3-Fix-register-allocation-assertion-fail.patch b/debian/patches/0002-freedreno-ir3-Fix-register-allocation-assertion-fail.patch
new file mode 100644
index 00000000000..8baabbcd88c
--- /dev/null
+++ b/debian/patches/0002-freedreno-ir3-Fix-register-allocation-assertion-fail.patch
@@ -0,0 +1,125 @@
+From 075d684629c6fcaeab23d837f4ce179d5ca71f4c Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric@anholt.net>
+Date: Tue, 21 Apr 2020 13:26:14 -0700
+Subject: [PATCH] freedreno/ir3: Fix register allocation assertion failures.
+
+We were failing to tell the allocator about the restriction that scalar
+texture instructions (allocated as scalar regs) couldn't be allocated such
+that the start of the full unwritemasked vector started before r0.  There
+was a patch in select_reg_callback on a6xx that tried to work around that,
+but you could still end up backed into a corner you shouldn't be because
+we didn't tell the RA what it needed.
+
+Fixes compiler assertion failures on a300-a400's blit_z shader, used for
+Z32F gmem blits.
+
+Looks like as a result we get tighter register allocation but more nops:
+
+instructions in affected programs: 757945 -> 760356 (0.32%)
+nops in affected programs: 317983 -> 320468 (0.78%)
+non-nops in affected programs: 27525 -> 27451 (-0.27%)
+mov in affected programs: 3098 -> 3023 (-2.42%)
+dwords in affected programs: 109664 -> 110656 (0.90%)
+last-baryf in affected programs: 112701 -> 112847 (0.13%)
+full in affected programs: 4326 -> 4011 (-7.28%)
+sstall in affected programs: 120550 -> 120836 (0.24%)
+(ss) in affected programs: 13939 -> 13918 (-0.15%)
+(sy) in affected programs: 3006 -> 2786 (-7.32%)
+
+Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
+(cherry picked from commit b420d04e1f744d15622f89180d1e3e511d92a8ba)
+Signed-off-by: Rob Clark <robdclark@chromium.org>
+---
+ src/freedreno/ir3/ir3_ra.c | 41 ++++++++++++++++++++++++++------------
+ src/freedreno/ir3/ir3_ra.h |  2 ++
+ 2 files changed, 30 insertions(+), 13 deletions(-)
+
+diff --git a/src/freedreno/ir3/ir3_ra.c b/src/freedreno/ir3/ir3_ra.c
+index 927f91e98ec..231bfc6ffc1 100644
+--- a/src/freedreno/ir3/ir3_ra.c
++++ b/src/freedreno/ir3/ir3_ra.c
+@@ -497,19 +497,6 @@ ra_select_reg_merged(unsigned int n, BITSET_WORD *regs, void *data)
+ 				return reg;
+ 			}
+ 		}
+-	} else if (is_tex_or_prefetch(instr)) {
+-		/* we could have a tex fetch w/ wrmask .z, for example.. these
+-		 * cannot land in r0.x since that would underflow when we
+-		 * subtract the offset.  Ie. if we pick r0.z, and subtract
+-		 * the offset, the register encoded for dst will be r0.x
+-		 */
+-		unsigned n = ffs(instr->regs[0]->wrmask);
+-		debug_assert(n > 0);
+-		unsigned offset = n - 1;
+-		if (!half)
+-			offset *= 2;
+-		base += offset;
+-		max_target -= offset;
+ 	}
+ 
+ 	int r = pick_in_range(regs, base + start, base + max_target);
+@@ -571,6 +558,12 @@ ra_init(struct ir3_ra_ctx *ctx)
+ 	}
+ 	ctx->alloc_count += ctx->class_alloc_count[total_class_count];
+ 
++	/* Add vreg names for r0.xyz */
++	ctx->r0_xyz_nodes = ctx->alloc_count;
++	ctx->alloc_count += 3;
++	ctx->hr0_xyz_nodes = ctx->alloc_count;
++	ctx->alloc_count += 3;
++
+ 	ctx->g = ra_alloc_interference_graph(ctx->set->regs, ctx->alloc_count);
+ 	ralloc_steal(ctx->g, ctx->instrd);
+ 	ctx->def = rzalloc_array(ctx->g, unsigned, ctx->alloc_count);
+@@ -710,6 +703,20 @@ ra_block_compute_live_ranges(struct ir3_ra_ctx *ctx, struct ir3_block *block)
+ 
+ 			if ((instr->opc == OPC_META_INPUT) && first_non_input)
+ 				use(name, first_non_input);
++
++			/* Texture instructions with writemasks can be treated as smaller
++			 * vectors (or just scalars!) to allocate knowing that the
++			 * masked-out regs won't be written, but we need to make sure that
++			 * the start of the vector doesn't come before the first register
++			 * or we'll wrap.
++			 */
++			if (is_tex_or_prefetch(instr)) {
++				int writemask_skipped_regs = ffs(instr->regs[0]->wrmask) - 1;
++				int r0_xyz = (instr->regs[0]->flags & IR3_REG_HALF) ?
++					ctx->hr0_xyz_nodes : ctx->r0_xyz_nodes;
++				for (int i = 0; i < writemask_skipped_regs; i++)
++					ra_add_node_interference(ctx->g, name, r0_xyz + i);
++			}
+ 		}
+ 
+ 		foreach_use (name, ctx, instr) {
+@@ -1005,6 +1012,14 @@ ra_add_interference(struct ir3_ra_ctx *ctx)
+ 		arr->end_ip = 0;
+ 	}
+ 
++
++	/* set up the r0.xyz precolor regs. */
++	for (int i = 0; i < 3; i++) {
++		ra_set_node_reg(ctx->g, ctx->r0_xyz_nodes + i, i);
++		ra_set_node_reg(ctx->g, ctx->hr0_xyz_nodes + i,
++				ctx->set->first_half_reg + i);
++	}
++
+ 	/* compute live ranges (use/def) on a block level, also updating
+ 	 * block's def/use bitmasks (used below to calculate per-block
+ 	 * livein/liveout):
+diff --git a/src/freedreno/ir3/ir3_ra.h b/src/freedreno/ir3/ir3_ra.h
+index 45df2397ddc..35fb618c49a 100644
+--- a/src/freedreno/ir3/ir3_ra.h
++++ b/src/freedreno/ir3/ir3_ra.h
+@@ -144,6 +144,8 @@ struct ir3_ra_ctx {
+ 	bool scalar_pass;
+ 
+ 	unsigned alloc_count;
++	unsigned r0_xyz_nodes; /* ra node numbers for r0.[xyz] precolors */
++	unsigned hr0_xyz_nodes; /* ra node numbers for hr0.[xyz] precolors pre-a6xx */
+ 	/* one per class, plus one slot for arrays: */
+ 	unsigned class_alloc_count[total_class_count + 1];
+ 	unsigned class_base[total_class_count + 1];
+-- 
+2.27.0
+
diff --git a/debian/patches/series b/debian/patches/series
index f9efbaeee85..393b2649225 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -3,3 +3,5 @@ fix-python-shebang.diff
 path_max.diff
 fix-ppc64el.patch
 src_glx_dri_common.h.diff
+0001-freedreno_resource.c-fd_layout_resource_for_modifier.patch
+0002-freedreno-ir3-Fix-register-allocation-assertion-fail.patch