diff options
24 files changed, 521 insertions, 68 deletions
diff --git a/dev/gcdb/display/include/display_resource.h b/dev/gcdb/display/include/display_resource.h index 62504270..6fc177a4 100755 --- a/dev/gcdb/display/include/display_resource.h +++ b/dev/gcdb/display/include/display_resource.h @@ -55,11 +55,11 @@ #define SIM_DSI_ID "dsi:0:" #define SIM_VIDEO_PANEL_NODE "qcom,mdss_dsi_sim_video" -#define SIM_DUALDSI_VIDEO_PANEL_NODE "qcom,mdss_dsi_sim_video_0" -#define SIM_DUALDSI_VIDEO_SLAVE_PANEL_NODE "qcom,mdss_dsi_sim_video_1" +#define SIM_DUALDSI_VIDEO_PANEL_NODE "qcom,mdss_dsi_dual_sim_video" +#define SIM_DUALDSI_VIDEO_SLAVE_PANEL_NODE "qcom,mdss_dsi_dual_sim_video" #define SIM_CMD_PANEL_NODE "qcom,mdss_dsi_sim_cmd" -#define SIM_DUALDSI_CMD_PANEL_NODE "qcom,mdss_dsi_sim_cmd_0" -#define SIM_DUALDSI_CMD_SLAVE_PANEL_NODE "qcom,mdss_dsi_sim_cmd_1" +#define SIM_DUALDSI_CMD_PANEL_NODE "qcom,mdss_dsi_dual_sim_cmd" +#define SIM_DUALDSI_CMD_SLAVE_PANEL_NODE "qcom,mdss_dsi_dual_sim_cmd" /*---------------------------------------------------------------------------*/ /* Structure definition */ diff --git a/dev/gcdb/display/include/panel_nt35597_wqxga_dualdsi_video.h b/dev/gcdb/display/include/panel_nt35597_wqxga_dualdsi_video.h index 9714b26c..88d21259 100644 --- a/dev/gcdb/display/include/panel_nt35597_wqxga_dualdsi_video.h +++ b/dev/gcdb/display/include/panel_nt35597_wqxga_dualdsi_video.h @@ -38,9 +38,9 @@ /* Panel configuration */ /*---------------------------------------------------------------------------*/ static struct panel_config nt35597_wqxga_dualdsi_video_panel_data = { - "qcom,mdss_dsi_nt35597_wqxga_video_0", "dsi:0:", "qcom,mdss-dsi-panel", + "qcom,mdss_dsi_nt35597_wqxga_video", "dsi:0:", "qcom,mdss-dsi-panel", 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 1, 0, 0, 0, 0, 0, 25, 1, 0, - "qcom,mdss_dsi_nt35597_wqxga_video_1" + "qcom,mdss_dsi_nt35597_wqxga_video" }; /*---------------------------------------------------------------------------*/ diff --git a/include/platform.h b/include/platform.h index 3cb7f2fb..0c590564 100644 --- a/include/platform.h +++ b/include/platform.h @@ -65,6 +65,7 @@ void clock_config_cdc(uint32_t interface); int platform_is_msm8939(); int platform_is_msm8909(); int platform_is_msm8992(); +int platform_is_msm8956(); int boot_device_mask(int); uint32_t platform_detect_panel(); uint32_t platform_get_max_periph(); diff --git a/platform/mdm9640/include/platform/iomap.h b/platform/mdm9640/include/platform/iomap.h index 1f5d9aad..5803acda 100644 --- a/platform/mdm9640/include/platform/iomap.h +++ b/platform/mdm9640/include/platform/iomap.h @@ -29,6 +29,10 @@ #ifndef _PLATFORM_MDM9640_IOMAP_H_ #define _PLATFORM_MDM9640_IOMAP_H_ +#include <stdint.h> + +uint32_t platform_boot_config(); + /* NAND */ #define MSM_NAND_BASE 0x079B0000 /* NAND BAM */ @@ -182,7 +186,9 @@ /* Boot config */ #define SEC_CTRL_CORE_BASE 0x00058000 #define BOOT_CONFIG_OFFSET 0x0000602C -#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET) +#define BOOT_CONFIG_REG_V1 (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET) +#define BOOT_CONFIG_REG_V2 0x000A602C +#define BOOT_CONFIG_REG platform_boot_config() /* QPIC DISPLAY */ #define QPIC_BASE 0x7980000 diff --git a/platform/mdm9640/platform.c b/platform/mdm9640/platform.c index c549287b..7cbf165e 100644 --- a/platform/mdm9640/platform.c +++ b/platform/mdm9640/platform.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are @@ -154,3 +154,15 @@ addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr) /* Fixed 1-1 mapping */ return phys_addr; } + +uint32_t platform_boot_config() +{ + uint32_t boot_config; + + if (board_soc_version() >= 0x20000) + boot_config = BOOT_CONFIG_REG_V2; + else + boot_config = BOOT_CONFIG_REG_V1; + + return boot_config; +} diff --git a/platform/msm8952/include/platform/iomap.h b/platform/msm8952/include/platform/iomap.h index 69925229..8ea20f4c 100644 --- a/platform/msm8952/include/platform/iomap.h +++ b/platform/msm8952/include/platform/iomap.h @@ -98,6 +98,7 @@ #define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x45000) #define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x45004) #define GPLL4_MODE (CLK_CTL_BASE + 0x24000) +#define GPLL4_STATUS (CLK_CTL_BASE + 0x24024) /* SDCC */ #define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x10A000) diff --git a/platform/msm8952/msm8952-clock.c b/platform/msm8952/msm8952-clock.c index b2f467ae..fd1d6f75 100644 --- a/platform/msm8952/msm8952-clock.c +++ b/platform/msm8952/msm8952-clock.c @@ -298,7 +298,7 @@ static struct vote_clk gcc_blsp1_ahb_clk = { /* USB Clocks */ static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = { - F(80000000, gpll0, 10, 0, 0), + F(100000000, gpll0, 10, 0, 0), F(133330000, gpll0, 6, 0, 0), F_END }; @@ -528,7 +528,15 @@ static struct clk_lookup msm_clocks_8952[] = CLK_LOOKUP("ce1_src_clk", ce1_clk_src.c), }; +void msm8956_clock_override() +{ + gpll4_clk_src.status_reg = (void *)GPLL4_STATUS; + gpll4_clk_src.status_mask = BIT(17); +} + void platform_clock_init(void) { + if (platform_is_msm8956()) + msm8956_clock_override(); clk_init(msm_clocks_8952, ARRAY_SIZE(msm_clocks_8952)); } diff --git a/platform/msm8952/platform.c b/platform/msm8952/platform.c index 996d6034..0f1439ab 100644 --- a/platform/msm8952/platform.c +++ b/platform/msm8952/platform.c @@ -172,3 +172,23 @@ uint32_t platform_get_max_periph() { return 256; } + +int platform_is_msm8956() +{ + uint32_t platform = board_platform_id(); + uint32_t ret = 0; + + switch(platform) + { + case MSM8956: + case APQ8056: + case APQ8076: + case MSM8976: + ret = 1; + break; + default: + ret = 0; + }; + + return ret; +} diff --git a/platform/msm8994/platform.c b/platform/msm8994/platform.c index 12b10395..82e33b9c 100644 --- a/platform/msm8994/platform.c +++ b/platform/msm8994/platform.c @@ -42,7 +42,7 @@ #define HLOS_MEMORY_START 0x0 #define HLOS_MEMORY_SIZE 0x63 -/* LK memory - cacheable, write through */ +/* LK memory - cacheable, write back */ #define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \ MMU_MEMORY_AP_READ_WRITE) @@ -54,6 +54,11 @@ #define COMMON_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN) +/* Scratch memory - cacheable, write back */ +#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \ + MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN) + + static mmu_section_t mmu_section_table[] = { /* Physical addr, Virtual addr, Size (in MB), Flags */ { MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY}, @@ -61,7 +66,7 @@ static mmu_section_t mmu_section_table[] = { { SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1, COMMON_MEMORY}, { MSM_SHARED_BASE, MSM_SHARED_BASE, 2, COMMON_MEMORY}, { HLOS_MEMORY_START, HLOS_MEMORY_START, HLOS_MEMORY_SIZE, COMMON_MEMORY}, - { SCRATCH_ADDR, SCRATCH_ADDR, (SCRATCH_SIZE / MB), COMMON_MEMORY}, + { SCRATCH_ADDR, SCRATCH_ADDR, (SCRATCH_SIZE / MB), SCRATCH_MEMORY}, }; void platform_early_init(void) diff --git a/platform/msm8996/acpuclock.c b/platform/msm8996/acpuclock.c index 63dd958f..9b1a23bb 100644 --- a/platform/msm8996/acpuclock.c +++ b/platform/msm8996/acpuclock.c @@ -495,18 +495,18 @@ void mmss_bus_clock_disable(void) clk_disable(clk_get("mmss_mmagic_axi_clk")); } -void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t flags) +void mmss_dsi_clock_enable(uint32_t cfg_rcgr, uint32_t flags) { int ret; if (flags & MMSS_DSI_CLKS_FLAG_DSI0) { /* Enable DSI0 branch clocks */ - writel(0x100, DSI_BYTE0_CFG_RCGR); + writel(cfg_rcgr, DSI_BYTE0_CFG_RCGR); writel(0x1, DSI_BYTE0_CMD_RCGR); writel(0x1, DSI_BYTE0_CBCR); - writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR); + writel(cfg_rcgr, DSI_PIXEL0_CFG_RCGR); writel(0x1, DSI_PIXEL0_CMD_RCGR); writel(0x1, DSI_PIXEL0_CBCR); @@ -520,11 +520,11 @@ void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t flags) if (flags & MMSS_DSI_CLKS_FLAG_DSI1) { /* Enable DSI1 branch clocks */ - writel(0x100, DSI_BYTE1_CFG_RCGR); + writel(cfg_rcgr, DSI_BYTE1_CFG_RCGR); writel(0x1, DSI_BYTE1_CMD_RCGR); writel(0x1, DSI_BYTE1_CBCR); - writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR); + writel(cfg_rcgr, DSI_PIXEL1_CFG_RCGR); writel(0x1, DSI_PIXEL1_CMD_RCGR); writel(0x1, DSI_PIXEL1_CBCR); diff --git a/platform/msm8996/include/platform/clock.h b/platform/msm8996/include/platform/clock.h index f740bd0e..4ad790f0 100644 --- a/platform/msm8996/include/platform/clock.h +++ b/platform/msm8996/include/platform/clock.h @@ -82,6 +82,7 @@ #define DSI_PIXEL0_D REG_MM(0x2010) #define DSI0_PHY_PLL_OUT BIT(8) +#define DSI1_PHY_PLL_OUT BIT(9) #define PIXEL_SRC_DIV_1_5 BIT(1) #define DSI_BYTE1_CMD_RCGR REG_MM(0x2140) @@ -112,7 +113,7 @@ void clock_ce_disable(uint8_t instance); void clock_usb30_init(void); void clock_reset_usb_phy(); -void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi); +void mmss_dsi_clock_enable(uint32_t cfg_rcgr, uint32_t dual_dsi); void mmss_dsi_clock_disable(uint32_t dual_dsi); void mmss_bus_clock_enable(void); void mmss_bus_clock_disable(void); diff --git a/platform/msm_shared/include/clock_pll.h b/platform/msm_shared/include/clock_pll.h index 22efac32..b263a1cf 100644 --- a/platform/msm_shared/include/clock_pll.h +++ b/platform/msm_shared/include/clock_pll.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012, The Linux Foundation. All rights reserved. + * Copyright (c) 2012,2015, The Linux Foundation. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -57,8 +57,8 @@ struct pll_vote_clk { void *const en_reg; const uint32_t en_mask; - void *const status_reg; - const uint32_t status_mask; + void *status_reg; + uint32_t status_mask; struct clk *parent; struct clk c; diff --git a/platform/msm_shared/include/qpic_nand.h b/platform/msm_shared/include/qpic_nand.h index 14282ece..211f8941 100644 --- a/platform/msm_shared/include/qpic_nand.h +++ b/platform/msm_shared/include/qpic_nand.h @@ -122,6 +122,8 @@ #define NAND_ERASED_CW_DETECT_STATUS_CODEWORD_ALL_ERASED 6 #define NAND_ERASED_CW_DETECT_STATUS_CODEWORD_ERASED 4 +#define NAND_ERASED_CW (BIT(NAND_ERASED_CW_DETECT_STATUS_CODEWORD_ERASED) | \ + BIT(NAND_ERASED_CW_DETECT_STATUS_CODEWORD_ALL_ERASED)) #define NAND_ERASED_CW_DETECT_CFG_RESET_CTRL 1 #define NAND_ERASED_CW_DETECT_CFG_ACTIVATE_CTRL 0 #define NAND_ERASED_CW_DETECT_ERASED_CW_ECC_MASK (1 << 1) diff --git a/platform/msm_shared/include/regulator.h b/platform/msm_shared/include/regulator.h index 92d322e5..9f02e7ef 100644 --- a/platform/msm_shared/include/regulator.h +++ b/platform/msm_shared/include/regulator.h @@ -65,6 +65,7 @@ #define LNBB_CLK_ID 0x8 #define RPM_CLK_BUFFER_PIN_CONTROL_ENABLE_NONE 0x0 +#define REG_LDO1 BIT(0) #define REG_LDO2 BIT(1) #define REG_LDO6 BIT(5) #define REG_LDO12 BIT(11) diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c index ae1cba00..4caa5c8d 100644 --- a/platform/msm_shared/qpic_nand.c +++ b/platform/msm_shared/qpic_nand.c @@ -48,6 +48,8 @@ static uint32_t cfg1; static uint32_t cfg0_raw; static uint32_t cfg1_raw; static uint32_t ecc_bch_cfg; +static uint32_t ecc_cfg_raw; +static uint32_t ecc_parity_bytes; struct cmd_element ce_array[100] __attribute__ ((aligned(16))); struct cmd_element ce_read_array[20] __attribute__ ((aligned(16))); @@ -55,6 +57,8 @@ struct cmd_element ce_read_array[20] __attribute__ ((aligned(16))); #define QPIC_BAM_DATA_FIFO_SIZE 64 #define QPIC_BAM_CMD_FIFO_SIZE 64 +#define THRESHOLD_BIT_FLIPS 4 + static struct bam_desc cmd_desc_fifo[QPIC_BAM_CMD_FIFO_SIZE] __attribute__ ((aligned(BAM_DESC_SIZE))); static struct bam_desc data_desc_fifo[QPIC_BAM_DATA_FIFO_SIZE] __attribute__ ((aligned(BAM_DESC_SIZE))); @@ -516,6 +520,7 @@ qpic_nand_onfi_save_params(struct onfi_param_page *param_page, struct flash_info static void qpic_nand_save_config(struct flash_info *flash) { + uint32_t spare_bytes = 0; /* Save Configurations */ flash->cws_per_page = flash->page_size >> NAND_CW_DIV_RIGHT_SHIFT; @@ -564,6 +569,10 @@ qpic_nand_save_config(struct flash_info *flash) */ flash->bad_blk_loc = flash->page_size - flash->cw_size * (flash->cws_per_page - 1) + 1; + /* Calculate the parity and spare bytes */ + ecc_parity_bytes = (flash->ecc_width & NAND_WITH_8_BIT_ECC) ? (flash->widebus ? 14 : 13) : (flash->widebus ? 8 : 7) ; + spare_bytes = flash->cw_size - (USER_DATA_BYTES_PER_CW + ecc_parity_bytes); + cfg0 |= ((flash->cws_per_page - 1) << NAND_DEV0_CFG0_CW_PER_PAGE_SHIFT) /* 4/8 cw/pg for 2/4k */ |(DATA_BYTES_IN_IMG_PER_CW << NAND_DEV0_CFG0_UD_SIZE_BYTES_SHIFT) /* 516 user data bytes */ |(5 << NAND_DEV0_CFG0_ADDR_CYCLE_SHIFT) /* 5 address cycles */ @@ -576,16 +585,16 @@ qpic_nand_save_config(struct flash_info *flash) |(2 << NAND_DEV0_CFG1_WR_RD_BSY_GAP_SHIFT) /* 8 cycle tWB/tRB */ |(flash->widebus << NAND_DEV0_CFG1_WIDE_BUS_SHIFT); /* preserve wide flash flag */ - cfg0_raw = ((flash->cws_per_page- 1) << NAND_DEV0_CFG0_CW_PER_PAGE_SHIFT) + cfg0_raw = ((flash->cws_per_page - 1) << NAND_DEV0_CFG0_CW_PER_PAGE_SHIFT) |(5 << NAND_DEV0_CFG0_ADDR_CYCLE_SHIFT) - |(516 << NAND_DEV0_CFG0_UD_SIZE_BYTES_SHIFT) //figure out the size of cw - | (1 << NAND_DEV0_CFG0_DIS_STS_AFTER_WR_SHIFT); + |(512 << NAND_DEV0_CFG0_UD_SIZE_BYTES_SHIFT) + | (spare_bytes << NAND_DEV0_CFG0_SPARE_SZ_BYTES_SHIFT); - cfg1_raw = (7 << NAND_DEV0_CFG1_RECOVERY_CYCLES_SHIFT) - | (0 << NAND_DEV0_CFG1_CS_ACTIVE_BSY_SHIFT) - | (17 << NAND_DEV0_CFG1_BAD_BLK_BYTE_NUM_SHIFT) + cfg1_raw = (2 << NAND_DEV0_CFG1_WR_RD_BSY_GAP_SHIFT) | (1 << NAND_DEV0_CFG1_BAD_BLK_IN_SPARE_SHIFT) - | (2 << NAND_DEV0_CFG1_WR_RD_BSY_GAP_SHIFT) + | (21 << NAND_DEV0_CFG1_BAD_BLK_BYTE_NUM_SHIFT) + | (0 << NAND_DEV0_CFG1_CS_ACTIVE_BSY_SHIFT) + | (7 << NAND_DEV0_CFG1_RECOVERY_CYCLES_SHIFT) | (flash->widebus << NAND_DEV0_CFG1_WIDE_BUS_SHIFT) |1 ; /* to disable reed solomon ecc..this feild is now read only. */ @@ -593,6 +602,18 @@ qpic_nand_save_config(struct flash_info *flash) | (0 << NAND_DEV0_ECC_SW_RESET_SHIFT) /* Put ECC core in op mode */ | (DATA_BYTES_IN_IMG_PER_CW << NAND_DEV0_ECC_NUM_DATA_BYTES) | (1 << NAND_DEV0_ECC_FORCE_CLK_OPEN_SHIFT); /* Enable all clocks */ + + ecc_cfg_raw = (1 << NAND_DEV0_ECC_FORCE_CLK_OPEN_SHIFT) + | (DATA_BYTES_IN_IMG_PER_CW << NAND_DEV0_ECC_NUM_DATA_BYTES) + | (ecc_parity_bytes << NAND_DEV0_ECC_PARITY_SZ_BYTES_SHIFT) + | (0 << NAND_DEV0_ECC_SW_RESET_SHIFT) + | (1 << NAND_DEV0_ECC_DISABLE_SHIFT); + +#if DEBUG_QPIC_NAND + dprintf(INFO, "CFG0: 0x%08x CFG1: 0x%08x\n", cfg0, cfg1); + dprintf(INFO, "CFG0_RAW: 0x%08x CFG1_RAW: 0x%08x\n", cfg0_raw, cfg1_raw); + dprintf(INFO, "ECC_BCH_CFG: 0x%08x ECC_CFG_RAW: 0x%08x\n", ecc_bch_cfg, ecc_cfg_raw); +#endif } /* Onfi probe should issue the following commands to the flash device: @@ -1381,14 +1402,209 @@ flash_set_ptable(struct ptable *new_ptable) flash_ptable = new_ptable; } +static int find_num_zeros_per_cw(uint8_t *ecc_buf, uint32_t ecc_bytes) +{ + uint8_t val; + uint32_t i; + int num_zeros = 0; + + for (i = 0; i < ecc_bytes; i++) + { + val = ecc_buf[i]; + while (val) + { + if ((val & 1) == 0) + num_zeros++; + if (num_zeros > THRESHOLD_BIT_FLIPS) + goto out; + val >>= 1; + } + } + +out: + return num_zeros; +} + +static int qpic_nand_read_erased_page(uint32_t page) +{ + struct cfg_params params; + uint32_t ecc; + uint32_t flash_sts[QPIC_NAND_MAX_CWS_IN_PAGE]; + uint32_t buffer_sts[QPIC_NAND_MAX_CWS_IN_PAGE]; + uint32_t addr_loc_0; + uint32_t total_ecc_bytes = 0; + struct cmd_element *cmd_list_ptr = ce_array; + struct cmd_element *cmd_list_ptr_start = ce_array; + uint32_t num_cmd_desc = 0; + uint32_t num_data_desc = 0; + uint32_t i; + int nand_ret = NANDC_RESULT_SUCCESS; + uint8_t flags = 0; + uint32_t *cmd_list_temp = NULL; + uint8_t *ecc_buf = NULL; + uint8_t *ecc_temp = NULL; + int num_zeros = 0; +#if DEBUG_QPIC_NAND + uint32_t *buffer_temp = NULL; +#endif + + total_ecc_bytes = (ecc_parity_bytes * flash.cws_per_page); + ecc_buf = memalign(16, total_ecc_bytes); + ASSERT(ecc_buf); + + memset(ecc_buf, 0, total_ecc_bytes); + + ecc_temp = ecc_buf; +#if DEBUG_QPIC_NAND + buffer_temp = (uint32_t*)ecc_buf; +#endif + params.addr0 = page << 16; + params.addr1 = (page >> 16) & 0xff; + params.cfg0 = cfg0_raw; + params.cfg1 = cfg1_raw; + params.cmd = NAND_CMD_PAGE_READ; + params.exec = 1; + ecc = ecc_cfg_raw; + + /* Read all the Data bytes in the first 3 CWs. */ + addr_loc_0 = NAND_RD_LOC_OFFSET(517); + addr_loc_0 |= NAND_RD_LOC_SIZE(ecc_parity_bytes); + addr_loc_0 |= NAND_RD_LOC_LAST_BIT(1); + + /* Queue up the command and data descriptors for all the codewords in a page + * and do a single bam transfer at the end.*/ + for (i = 0; i < flash.cws_per_page; i++) + { + num_cmd_desc = 0; + num_data_desc = 0; + flags = 0; + + if (i == 0) + { + /* Set the lock flag for the first CW */ + flags = BAM_DESC_LOCK_FLAG; + + cmd_list_ptr = qpic_nand_add_addr_n_cfg_ce(¶ms, cmd_list_ptr); + + bam_add_cmd_element(cmd_list_ptr, NAND_DEV0_ECC_CFG,(uint32_t)ecc, CE_WRITE_TYPE); + cmd_list_ptr++; + + bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_CMD, (uint32_t)params.cmd, CE_WRITE_TYPE); + cmd_list_ptr++; + + /* Write addr loc 0. */ + bam_add_cmd_element(cmd_list_ptr, + NAND_READ_LOCATION_n(0), + (uint32_t)addr_loc_0, + CE_WRITE_TYPE); + + cmd_list_ptr++; + } + else + cmd_list_ptr_start = cmd_list_ptr; + + if (i == flash.cws_per_page - 1) + flags = BAM_DESC_INT_FLAG; + + /* Add Data desc */ + bam_add_one_desc(&bam, + DATA_PRODUCER_PIPE_INDEX, + (unsigned char *)PA((addr_t)ecc_temp), + ecc_parity_bytes, + flags); + num_data_desc++; + bam_sys_gen_event(&bam, DATA_PRODUCER_PIPE_INDEX, num_data_desc); + + bam_add_cmd_element(cmd_list_ptr, + NAND_EXEC_CMD, + (uint32_t)params.exec, + CE_WRITE_TYPE); + cmd_list_ptr++; + + /* Enqueue the desc for the above commands */ + bam_add_one_desc(&bam, + CMD_PIPE_INDEX, + (unsigned char*)cmd_list_ptr_start, + PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_ptr_start), + BAM_DESC_NWD_FLAG | BAM_DESC_CMD_FLAG | flags); + num_cmd_desc++; + + bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_STATUS, (uint32_t)PA((addr_t)&(flash_sts[i])), CE_READ_TYPE); + + cmd_list_temp = (uint32_t *)cmd_list_ptr; + + cmd_list_ptr++; + + bam_add_cmd_element(cmd_list_ptr, NAND_BUFFER_STATUS, (uint32_t)PA((addr_t)&(buffer_sts[i])), CE_READ_TYPE); + cmd_list_ptr++; + + if (i == flash.cws_per_page - 1) + { + /* Unlock flag for the last CW */ + flags = BAM_DESC_CMD_FLAG | BAM_DESC_UNLOCK_FLAG; + } + else + flags = BAM_DESC_CMD_FLAG; + + /* Enqueue the desc for the above command */ + bam_add_one_desc(&bam, + CMD_PIPE_INDEX, + (unsigned char*)PA((addr_t)cmd_list_temp), + PA((uint32_t)cmd_list_ptr - (uint32_t)cmd_list_temp), + flags); + num_cmd_desc++; + + ecc_temp += ecc_parity_bytes; + + /* Notify BAM HW about the newly added descriptors */ + bam_sys_gen_event(&bam, CMD_PIPE_INDEX, num_cmd_desc); + } + + qpic_nand_wait_for_data(DATA_PRODUCER_PIPE_INDEX); + + /* Find number of bit flips in the ecc & if there are more than "threshold" bit flips then + * the page is bad otherwise the page is erased page + */ + ecc_temp = ecc_buf; + + for (i = 0; i < flash.cws_per_page; i++) + { + num_zeros = find_num_zeros_per_cw(ecc_temp, ecc_parity_bytes); + + if (num_zeros > THRESHOLD_BIT_FLIPS) + { + nand_ret = NANDC_RESULT_BAD_PAGE; + goto qpic_nand_read_page_error; + } + + ecc_temp += ecc_parity_bytes; + } + +qpic_nand_read_page_error: + +#if DEBUG_QPIC_NAND + for(i = 0; i < 24; i += 8) + { + printf("ECC: %08x %08x %08x %08x %08x %08x %08x %08x\n", + buffer_temp[i], buffer_temp[i+1], buffer_temp[i+2], buffer_temp[i+3], + buffer_temp[i+4], buffer_temp[i+5], buffer_temp[i+6], buffer_temp[i+7]); + } + printf("ECC: %08x %08x\n", buffer_temp[24], buffer_temp[25]); +#endif + + free(ecc_buf); + return nand_ret; +} + /* Note: No support for raw reads. */ static int qpic_nand_read_page(uint32_t page, unsigned char* buffer, unsigned char* spareaddr) { struct cfg_params params; uint32_t ecc; - uint32_t flash_sts[QPIC_NAND_MAX_CWS_IN_PAGE]; - uint32_t buffer_sts[QPIC_NAND_MAX_CWS_IN_PAGE]; + uint32_t flash_sts[QPIC_NAND_MAX_CWS_IN_PAGE] = {0}; + uint32_t buffer_sts[QPIC_NAND_MAX_CWS_IN_PAGE] = {0}; + uint32_t erased_cw_sts[QPIC_NAND_MAX_CWS_IN_PAGE] = {0}; uint32_t addr_loc_0; uint32_t addr_loc_1; struct cmd_element *cmd_list_ptr = ce_array; @@ -1400,6 +1616,9 @@ qpic_nand_read_page(uint32_t page, unsigned char* buffer, unsigned char* sparead int nand_ret = NANDC_RESULT_SUCCESS; uint8_t flags = 0; uint32_t *cmd_list_temp = NULL; +#if DEBUG_QPIC_NAND + uint8_t *buffer_temp = buffer; +#endif /* UD bytes in last CW is 512 - cws_per_page *4. * Since each of the CW read earlier reads 4 spare bytes. @@ -1411,7 +1630,7 @@ qpic_nand_read_page(uint32_t page, unsigned char* buffer, unsigned char* sparead params.addr1 = (page >> 16) & 0xff; params.cfg0 = cfg0; params.cfg1 = cfg1; - params.cmd = NAND_CMD_PAGE_READ_ALL; + params.cmd = NAND_CMD_PAGE_READ_ECC; params.exec = 1; ecc = ecc_bch_cfg; @@ -1522,6 +1741,10 @@ qpic_nand_read_page(uint32_t page, unsigned char* buffer, unsigned char* sparead bam_add_cmd_element(cmd_list_ptr, NAND_BUFFER_STATUS, (uint32_t)PA((addr_t)&(buffer_sts[i])), CE_READ_TYPE); cmd_list_ptr++; + /* Read erased CW status */ + bam_add_cmd_element(cmd_list_ptr, NAND_ERASED_CW_DETECT_STATUS, (uint32_t)PA((addr_t)&erased_cw_sts[i]), CE_READ_TYPE); + cmd_list_ptr++; + if (i == flash.cws_per_page - 1) { flags = BAM_DESC_CMD_FLAG | BAM_DESC_UNLOCK_FLAG; @@ -1545,19 +1768,57 @@ qpic_nand_read_page(uint32_t page, unsigned char* buffer, unsigned char* sparead qpic_nand_wait_for_data(DATA_PRODUCER_PIPE_INDEX); - /* Check status */ + /* Check flash read status & errors */ for (i = 0; i < flash.cws_per_page ; i ++) { - flash_sts[i] = qpic_nand_check_status(flash_sts[i]); - if (flash_sts[i]) +#if DEBUG_QPIC_NAND + dprintf(INFO, "FLASH STATUS: 0x%08x, BUFFER STATUS: 0x%08x, ERASED CW STATUS: 0x%08x\n", + flash_sts[i], buffer_sts[i], erased_cw_sts[i]); +#endif + + /* If MPU or flash op erros are set, look for erased cw status. + * If erased CW status is not set then look for bit flips to confirm + * if the page is and erased page or a bad page + */ + if (flash_sts[i] & (NAND_FLASH_OP_ERR | NAND_FLASH_MPU_ERR)) { - nand_ret = NANDC_RESULT_BAD_PAGE; - dprintf(CRITICAL, "NAND page read failed. page: %x status %x\n", page, flash_sts[i]); - goto qpic_nand_read_page_error; + if ((erased_cw_sts[i] & NAND_ERASED_CW) != NAND_ERASED_CW) + { +#if DEBUG_QPIC_NAND + dprintf(CRITICAL, "Page: 0x%08x, addr0: 0x%08x, addr1: 0x%08x\n", page, params.addr0, params.addr1); +#endif + /* + * Depending on the process technology used there could be bit flips on + * pages on the NAND card + * When any page is erased the controller fills the page with all 1's. + * When we try to read from an erased page and there are bit flips the + * controller would not detect the page as erased page instead throws + * an uncorrectable ecc error. + * The NAND data sheet for that card would specify the number of bit flips + * expected per code word. If the number of bit flips is less than expected + * bit flips then we should ignore the uncorrectable ECC error and consider + * the page as an erased page. + */ +#if DEBUG_QPIC_NAND + for(i = 0; i < 4096; i += 8) + { + printf("DATA: %x %x %x %x %x %x %x %x", + buffer_temp[i], buffer_temp[i+1], buffer_temp[i+2], buffer_temp[i+3], + buffer_temp[i+4], buffer_temp[i+5], buffer_temp[i+6], buffer_temp[i+7]); + i += 8; + printf("DATA: %x %x %x %x %x %x %x %x\n", + buffer_temp[i], buffer_temp[i+1], buffer_temp[i+2], buffer_temp[i+3], + buffer_temp[i+4], buffer_temp[i+5], buffer_temp[i+6], buffer_temp[i+7]); + } +#endif + nand_ret = qpic_nand_read_erased_page(page); + goto qpic_nand_read_page_error; + } } } + qpic_nand_read_page_error: -return nand_ret; + return nand_ret; } /** diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c index 88e68983..9aad8093 100644 --- a/platform/msm_shared/scm.c +++ b/platform/msm_shared/scm.c @@ -1139,6 +1139,7 @@ static uint32_t scm_call_a32(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3, register uint32_t r3 __asm__("r3") = x3; register uint32_t r4 __asm__("r4") = x4; register uint32_t r5 __asm__("r5") = x5; + register uint32_t r6 __asm__("r6") = 0; do { __asm__ volatile( @@ -1152,9 +1153,10 @@ static uint32_t scm_call_a32(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3, __asmeq("%7", "r3") __asmeq("%8", "r4") __asmeq("%9", "r5") + __asmeq("%10", "r6") "smc #0 @ switch to secure world\n" : "=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) - : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4), "r" (r5)); + : "r" (r0), "r" (r1), "r" (r2), "r" (r3), "r" (r4), "r" (r5), "r" (r6)); } while(r0 == 1); if (ret) diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h index 24a206be..ceb25e61 100644 --- a/platform/msm_shared/smem.h +++ b/platform/msm_shared/smem.h @@ -413,6 +413,7 @@ enum { APQ8076 = 277, MSM8976 = 278, APQ8052 = 289, + APQ8096 = 291, }; enum platform { diff --git a/project/msm8952.mk b/project/msm8952.mk index c0484d07..d8e3dc8e 100644 --- a/project/msm8952.mk +++ b/project/msm8952.mk @@ -56,6 +56,12 @@ ifeq ($(ENABLE_SMD_SUPPORT),1) DEFINES += SMD_SUPPORT=1 endif +ifeq ($(ENABLE_MDTP_SUPPORT),1) +DEFINES += MDTP_SUPPORT=1 +DEFINES += MDTP_EFUSE_ADDRESS=0x0C858250 # QFPROM_RAW_QC_SPARE_REG_LSB_ADDR +DEFINES += MDTP_EFUSE_START=0 +endif + #SCM call before entering DLOAD mode DEFINES += PLATFORM_USE_SCM_DLOAD=1 diff --git a/target/msm8909/target_display.c b/target/msm8909/target_display.c index 085dc006..9af712e2 100755 --- a/target/msm8909/target_display.c +++ b/target/msm8909/target_display.c @@ -62,33 +62,125 @@ static void mdss_dsi_uniphy_pll_sw_reset_8909(uint32_t pll_base) mdelay(1); } -static uint32_t dsi_pll_enable_seq_8909(uint32_t pll_base) +static void dsi_pll_toggle_lock_detect_8909(uint32_t pll_base) { - uint32_t pll_locked = 0; + writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */ + udelay(1); + writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */ + udelay(512); +} +static void dsi_pll_sw_reset_8909(uint32_t pll_base) +{ writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */ udelay(1); writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */ +} +static uint32_t dsi_pll_enable_seq_1_8909(uint32_t pll_base) +{ + uint32_t rc; + + dsi_pll_sw_reset_8909(pll_base); /* * Add hardware recommended delays between register writes for * the updates to take effect. These delays are necessary for the * PLL to successfully lock */ + writel(0x34, pll_base + 0x0070); /* CAL CFG1*/ - udelay(1); writel(0x01, pll_base + 0x0020); /* GLB CFG */ - udelay(1); writel(0x05, pll_base + 0x0020); /* GLB CFG */ - udelay(1); writel(0x0f, pll_base + 0x0020); /* GLB CFG */ - udelay(1); + udelay(500); - writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */ - udelay(1); - writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */ - udelay(512); - pll_locked = readl(pll_base + 0x00c0) & 0x01; + dsi_pll_toggle_lock_detect_8909(pll_base); + rc = readl(pll_base + 0x00c0) & 0x01; + + return rc; +} + +static uint32_t dsi_pll_enable_seq_2_8909(uint32_t pll_base) +{ + uint32_t rc; + + dsi_pll_sw_reset_8909(pll_base); + + /* + * Add hardware recommended delays between register writes for + * the updates to take effect. These delays are necessary for the + * PLL to successfully lock + */ + writel(0x14, pll_base + 0x0070); /* CAL CFG1*/ + writel(0x01, pll_base + 0x0020); /* GLB CFG */ + writel(0x05, pll_base + 0x0020); /* GLB CFG */ + udelay(3); + writel(0x0f, pll_base + 0x0020); /* GLB CFG */ + udelay(500); + + dsi_pll_toggle_lock_detect_8909(pll_base); + rc = readl(pll_base + 0x00c0) & 0x01; + + return rc; +} + +static uint32_t dsi_pll_enable_seq_3_8909(uint32_t pll_base) +{ + uint32_t rc; + + dsi_pll_sw_reset_8909(pll_base); + + /* + * Add hardware recommended delays between register writes for + * the updates to take effect. These delays are necessary for the + * PLL to successfully lock + */ + writel(0x04, pll_base + 0x0070); /* CAL CFG1*/ + writel(0x01, pll_base + 0x0020); /* GLB CFG */ + writel(0x05, pll_base + 0x0020); /* GLB CFG */ + udelay(3); + writel(0x0f, pll_base + 0x0020); /* GLB CFG */ + udelay(500); + + dsi_pll_toggle_lock_detect_8909(pll_base); + rc = readl(pll_base + 0x00c0) & 0x01; + + return rc; +} + +static uint32_t dsi_pll_enable_seq_8909(uint32_t pll_base) +{ + uint32_t pll_locked = 0; + uint32_t counter = 0; + + do { + pll_locked = dsi_pll_enable_seq_1_8909(pll_base); + + dprintf(SPEW, "TSMC pll locked status is %d\n", pll_locked); + ++counter; + } while (!pll_locked && (counter < 3)); + + if (!pll_locked) { + counter = 0; + do { + pll_locked = dsi_pll_enable_seq_2_8909(pll_base); + + dprintf(SPEW, "GF P1 pll locked status is %d\n", + pll_locked); + ++counter; + } while (!pll_locked && (counter < 3)); + } + + if (!pll_locked) { + counter = 0; + do { + pll_locked = dsi_pll_enable_seq_3_8909(pll_base); + + dprintf(SPEW, "GF P2 pll locked status is %d\n", + pll_locked); + ++counter; + } while (!pll_locked && (counter < 3)); + } return pll_locked; } diff --git a/target/msm8952/init.c b/target/msm8952/init.c index 6998aa40..70da0ad3 100644 --- a/target/msm8952/init.c +++ b/target/msm8952/init.c @@ -163,7 +163,7 @@ void *target_mmc_device() } /* Return 1 if vol_up pressed */ -static int target_volume_up() +int target_volume_up() { uint8_t status = 0; diff --git a/target/msm8952/regulator.c b/target/msm8952/regulator.c index f411b1a6..74b6fe04 100644 --- a/target/msm8952/regulator.c +++ b/target/msm8952/regulator.c @@ -31,6 +31,25 @@ #include <rpm-smd.h> #include <bits.h> #include <debug.h> +#include <platform.h> + + +static uint32_t ldo1[][11]= +{ + { + LDOA_RES_TYPE, 1, + KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE, + KEY_MICRO_VOLT, 4, 0, + KEY_CURRENT, 4, 0, + }, + + { + LDOA_RES_TYPE, 1, + KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE, + KEY_MICRO_VOLT, 4, 1200000, + KEY_CURRENT, 4, 40, + }, +}; static uint32_t ldo2[][11]= { @@ -86,8 +105,17 @@ static uint32_t ldo17[][11]= void regulator_enable(uint32_t enable) { - if (enable & REG_LDO2) - rpm_send_data(&ldo2[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE); + if(platform_is_msm8956()) + { + if (enable & REG_LDO1) + rpm_send_data(&ldo1[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE); + + } + else + { + if (enable & REG_LDO2) + rpm_send_data(&ldo2[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE); + } if (enable & REG_LDO17) rpm_send_data(&ldo17[GENERIC_ENABLE][0], 36, RPM_REQUEST_TYPE); @@ -98,8 +126,17 @@ void regulator_enable(uint32_t enable) void regulator_disable(uint32_t enable) { - if (enable & REG_LDO2) - rpm_send_data(&ldo2[GENERIC_DISABLE][0], 36, RPM_REQUEST_TYPE); + if(platform_is_msm8956()) + { + if (enable & REG_LDO1) + rpm_send_data(&ldo1[GENERIC_DISABLE][0], 36, RPM_REQUEST_TYPE); + + } + else + { + if (enable & REG_LDO2) + rpm_send_data(&ldo2[GENERIC_DISABLE][0], 36, RPM_REQUEST_TYPE); + } if (enable & REG_LDO17) rpm_send_data(&ldo17[GENERIC_DISABLE][0], 36, RPM_REQUEST_TYPE); diff --git a/target/msm8996/init.c b/target/msm8996/init.c index 6667314e..f3c13275 100644 --- a/target/msm8996/init.c +++ b/target/msm8996/init.c @@ -317,6 +317,9 @@ void target_baseband_detect(struct board_data *board) platform = board->platform; switch(platform) { + case APQ8096: + board->baseband = BASEBAND_APQ; + break; case MSM8996: if (board->platform_version == 0x10000) board->baseband = BASEBAND_APQ; diff --git a/target/msm8996/oem_panel.c b/target/msm8996/oem_panel.c index 4e864482..7cc95ea6 100644 --- a/target/msm8996/oem_panel.c +++ b/target/msm8996/oem_panel.c @@ -105,10 +105,6 @@ static bool init_panel_data(struct panel_struct *panelstruct, pan_type = PANEL_TYPE_DSI; pinfo->lcd_reg_en = 0; panelstruct->paneldata = &sharp_wqxga_dualdsi_video_panel_data; - panelstruct->paneldata->panel_node_id = - "qcom,mdss_dsi_sharp_wqxga_video_0"; - panelstruct->paneldata->slave_panel_node_id = - "qcom,mdss_dsi_sharp_wqxga_video_1"; panelstruct->paneldata->panel_operating_mode = 11; panelstruct->paneldata->panel_with_enable_gpio = 0; @@ -176,10 +172,6 @@ static bool init_panel_data(struct panel_struct *panelstruct, case JDI_QHD_DUALDSI_VIDEO_PANEL: pan_type = PANEL_TYPE_DSI; pinfo->lcd_reg_en = 1; - panelstruct->paneldata->panel_node_id = - "qcom,dsi_jdi_qhd_video_0"; - panelstruct->paneldata->slave_panel_node_id = - "qcom,dsi_jdi_qhd_video_1"; panelstruct->paneldata = &jdi_qhd_dualdsi_video_panel_data; panelstruct->panelres = &jdi_qhd_dualdsi_video_panel_res; @@ -209,10 +201,6 @@ static bool init_panel_data(struct panel_struct *panelstruct, pan_type = PANEL_TYPE_DSI; pinfo->lcd_reg_en = 1; panelstruct->paneldata = &jdi_qhd_dualdsi_cmd_panel_data; - panelstruct->paneldata->panel_node_id = - "qcom,mdss_dsi_jdi_qhd_dualmipi0_cmd"; - panelstruct->paneldata->slave_panel_node_id = - "qcom,mdss_dsi_jdi_qhd_dualmipi1_cmd"; panelstruct->panelres = &jdi_qhd_dualdsi_cmd_panel_res; panelstruct->color = &jdi_qhd_dualdsi_cmd_color; diff --git a/target/msm8996/target_display.c b/target/msm8996/target_display.c index f9f3a5ba..283720c8 100644 --- a/target/msm8996/target_display.c +++ b/target/msm8996/target_display.c @@ -275,7 +275,7 @@ int target_backlight_ctrl(struct backlight *bl, uint8_t enable) int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) { - uint32_t flags; + uint32_t flags, dsi_phy_pll_out; uint32_t ret = NO_ERROR; uint32_t board_version = board_soc_version(); @@ -311,7 +311,13 @@ int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) dprintf(CRITICAL, "PLL failed to lock!\n"); goto clks_disable; } - mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, flags); + + if (pinfo->mipi.use_dsi1_pll) + dsi_phy_pll_out = DSI1_PHY_PLL_OUT; + else + dsi_phy_pll_out = DSI0_PHY_PLL_OUT; + mmss_dsi_clock_enable(dsi_phy_pll_out, flags); + return NO_ERROR; clks_disable: |