diff options
| author | Bjorn Andersson <bjorn.andersson@linaro.org> | 2018-11-02 17:16:08 -0700 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2018-11-02 22:46:19 -0700 |
| commit | fef7954dcb50784869fcf7498744dc92da022485 (patch) | |
| tree | e8d50ac378ff8935130caf2643dbc55f7d6144e3 | |
| parent | 77677ad63e05ed4f9e4c4158361d90baaa6bcf6f (diff) | |
arm64: dts: qcom: qcs404: Add USB PHYs
Add the two HS USB PHYs and the SS USB PHY found in the QCS404 platform
and enable these in the EVB.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/qcs404-evb.dts | 29 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/qcom/qcs404.dtsi | 87 |
2 files changed, 116 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dts b/arch/arm64/boot/dts/qcom/qcs404-evb.dts index 10ad05ba5ca9..bb9dfdc700fe 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dts +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dts @@ -181,3 +181,32 @@ }; }; }; + +&usb3_phy { + status = "okay"; + + vdd-supply = <&vreg_l3_1p05>; + vdda18-supply = <&vreg_l5_1p8>; + + qcom,vdd-voltage-level = <0 1050000 1050000>; +}; + +&usb2_phy_prim { + status = "okay"; + + vdd-supply = <&vreg_l4_1p2>; + vdda18-supply = <&vreg_l5_1p8>; + vdda33-supply = <&vreg_l12_3p3>; + + qcom,vdd-voltage-level = <0 1144000 1200000>; +}; + +&usb2_phy_sec { + status = "okay"; + + vdd-supply = <&vreg_l4_1p2>; + vdda18-supply = <&vreg_l5_1p8>; + vdda33-supply = <&vreg_l12_3p3>; + + qcom,vdd-voltage-level = <0 1144000 1200000>; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 8ea0f35a357c..7604c0733f5c 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -174,6 +174,93 @@ reg = <0x60000 0x6000>; }; + usb3_phy: phy@78000 { + compatible = "qcom,usb-ssphy"; + reg = <0x78000 0x400>; + + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref_clk", "cfg_ahb_clk", "pipe_clk"; + + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb2_phy_prim: phy@7a000 { + compatible = "qcom,usb-snps-hsphy"; + reg = <0x7a000 0x200>; + reg-names = "phy_csr"; + + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref_clk", "phy_csr_clk", "sleep_clk"; + + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy_reset", "phy_por_reset"; + + #phy-cells = <0>; + + qcom,snps-hs-phy-init-seq = + <0xc0 0x01 0>, + <0xe8 0x0d 0>, + <0x74 0x12 0>, + <0x98 0x63 0>, + <0x9c 0x03 0>, + <0xa0 0x1d 0>, + <0xa4 0x03 0>, + <0x8c 0x23 0>, + <0x78 0x08 0>, + <0x7c 0xdc 0>, + <0x90 0xe0 20>, + <0x74 0x10 0>, + <0x90 0x60 0>, + <0xffffffff 0xffffffff 0>; + + status = "disabled"; + }; + + usb2_phy_sec: phy@7c000 { + compatible = "qcom,usb-snps-hsphy"; + reg = <0x7c000 0x200>; + reg-names = "phy_csr"; + + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref_clk", "phy_csr_clk", "sleep_clk"; + + resets = <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy_reset", "phy_por_reset"; + + #phy-cells = <0>; + + qcom,snps-hs-phy-init-seq = + <0xc0 0x01 0>, + <0xe8 0x0d 0>, + <0x74 0x12 0>, + <0x98 0x63 0>, + <0x9c 0x03 0>, + <0xa0 0x1d 0>, + <0xa4 0x03 0>, + <0x8c 0x23 0>, + <0x78 0x08 0>, + <0x7c 0xdc 0>, + <0x90 0xe0 20>, + <0x74 0x10 0>, + <0x90 0x60 0>, + <0xffffffff 0xffffffff 0>; + + status = "disabled"; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; |