From 150a2e78e99625859a6722a08260b2f2b1791f7f Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 2 Nov 2018 17:09:21 -0700 Subject: arm64: dts: qcom: qcs404: Add rpmcc node Add the rpm clock controller node, to provide the low-noise baseband clock for the USB PHYs. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 9b5c16562bbe..f11ffd6801d5 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -3,6 +3,7 @@ #include #include +#include / { interrupt-parent = <&intc>; @@ -224,6 +225,11 @@ rpm_requests: glink-channel { compatible = "qcom,rpm-qcs404"; qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-qcs404"; + #clock-cells = <1>; + }; }; }; -- cgit v1.2.3 From 7aa0445da832bc4a5d70b4751666cc967280b2ba Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 2 Nov 2018 17:38:51 -0700 Subject: arm64: dts: qcom: qcs404: Mark gcc as reset-controller The global clock controller is reset-controller for e.g. the USB PHYs, add #reset-cells in order to allow it to be referenced as such. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index f11ffd6801d5..7c0e9b7d9c03 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -284,6 +284,7 @@ compatible = "qcom,gcc-qcs404"; reg = <0x01800000 0x80000>; #clock-cells = <1>; + #reset-cells = <1>; assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; -- cgit v1.2.3 From 843ce57d613b1a3742ec0a1e44868dda640b1226 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 2 Nov 2018 17:16:08 -0700 Subject: arm64: dts: qcom: qcs404: Add USB devices and PHYs QCS404 sports HS and SS USB controllers based on dwc3 block with two HS PHYs and one SS PHY. Add nodes for these devices and enable them for EVB board. Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 93 ++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/qcs404.dtsi | 100 +++++++++++++++++++++++++++++++ 2 files changed, 193 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index a39924efebe4..2f9d9706a6a4 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -3,6 +3,8 @@ #include "qcs404.dtsi" #include "pms405.dtsi" +#include +#include / { aliases { @@ -19,6 +21,25 @@ regulator-always-on; regulator-boot-on; }; + + usb3_vbus_reg: regulator-usb3-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pms405_gpios 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_vbus_boost_pin>; + enable-active-high; + }; + + usb3_con: usb3-connector { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 116 GPIO_ACTIVE_HIGH>; + vbus-gpio = <&pms405_gpios 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_id_pin>, <&usb3_vbus_pin>; + }; }; &remoteproc_adsp { @@ -185,4 +206,76 @@ bias-pull-down; }; }; + + usb3_id_pin: usb3-id-pin { + pinmux { + pins = "gpio116"; + function = "gpio"; + }; + + pinconf { + pins = "gpio116"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; +}; + +&pms405_gpios { + usb3_vbus_boost_pin: usb3-vbus-boost-pin { + pinconf { + pins = "gpio3"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + power-source = <1>; + }; + }; + + usb3_vbus_pin: usb3-vbus-pin { + pinconf { + pins = "gpio12"; + function = PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-down; + power-source = <1>; + }; + }; +}; + +&usb2 { + status = "okay"; +}; + +&usb2_phy_prim { + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + qcom,vdd-voltage-level = <0 1144000 1200000>; + status = "okay"; +}; + +&usb2_phy_sec { + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + qcom,vdd-voltage-level = <0 1144000 1200000>; + status = "okay"; +}; + +&usb3 { + extcon = <&usb3_con>; + status = "okay"; + + dwc3@7580000 { + extcon = <&usb3_con>; + }; +}; + +&usb3_phy { + vdd-supply = <&vreg_l3_1p05>; + vdda1p8-supply = <&vreg_l5_1p8>; + vbus-supply = <&usb3_vbus_reg>; + qcom,vdd-voltage-level = <0 1050000 1050000>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 7c0e9b7d9c03..dadfe42c3fec 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -266,6 +266,106 @@ clock-names = "core"; }; + usb3_phy: phy@78000 { + compatible = "qcom,usb-ssphy"; + reg = <0x78000 0x400>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "ref", "phy", "pipe"; + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "com", "phy"; + status = "disabled"; + }; + + usb2_phy_prim: phy@7a000 { + compatible = "qcom,qcs404-usb-hsphy"; + reg = <0x7a000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "phy", "sleep"; + resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, + <&gcc GCC_USB2A_PHY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + + usb2_phy_sec: phy@7c000 { + compatible = "qcom,qcs404-usb-hsphy"; + reg = <0x7c000 0x200>; + #phy-cells = <0>; + clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB2A_PHY_SLEEP_CLK>; + clock-names = "ref", "phy", "sleep"; + resets = <&gcc GCC_QUSB2_PHY_BCR>, + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; + reset-names = "phy", "por"; + status = "disabled"; + }; + + usb3: usb@7678800 { + compatible = "qcom,dwc3"; + reg = <0x07678800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + status = "disabled"; + + dwc3@7580000 { + compatible = "snps,dwc3"; + reg = <0x07580000 0xcd00>; + interrupts = ; + phys = <&usb2_phy_sec>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + dr_mode = "otg"; + }; + }; + + usb2: usb@79b8800 { + compatible = "qcom,dwc3"; + reg = <0x079b8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, + <&gcc GCC_PCNOC_USB2_CLK>, + <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>; + clock-names = "core", "iface", "sleep", "mock_utmi"; + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB_HS_SYSTEM_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + status = "disabled"; + + dwc3@78c0000 { + compatible = "snps,dwc3"; + reg = <0x078c0000 0xcc00>; + interrupts = ; + phys = <&usb2_phy_prim>; + phy-names = "usb2-phy"; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + dr_mode = "peripheral"; + }; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x01000000 0x200000>, -- cgit v1.2.3 From cd793f5ab9030b812b8cac13823803d354205aa6 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Thu, 13 Dec 2018 14:36:30 +0100 Subject: dt-bindings: mailbox: qcom: Add clock-name optional property When the APCS clock is registered (platform dependent), it retrieves its parent names from hardcoded values in the driver. The following commit allows the DT node to provide such clock names to the platform data based clock driver therefore avoiding having to explicitly embed those names in the clock driver source code. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- .../bindings/mailbox/qcom,apcs-kpss-global.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt index 1232fc9fc709..f2524396a9a7 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt @@ -23,6 +23,10 @@ platforms. Value type: Definition: phandle to the input PLL, which feeds the APCS mux/divider + Usage: required if #clock-names property is present + Value type: + Definition: phandles to the two parent clocks of the clock driver. + - #mbox-cells: Usage: required Value type: @@ -33,6 +37,12 @@ platforms. Value type: Definition: as described in clock.txt, must be 0 +- clock-names: + Usage: required if the platform data based clock driver needs to + retrieve the parent clock names from device tree. + This will requires two mandatory clocks to be defined. + Value type: + Definition: must be "aux" and "pll" = EXAMPLE The following example describes the APCS HMSS found in MSM8996 and part of the @@ -65,3 +75,14 @@ Below is another example of the APCS binding on MSM8916 platforms: clocks = <&a53pll>; #clock-cells = <0>; }; + +Below is another example of the APCS binding on QCS404 platforms: + + apcs_glb: mailbox@b011000 { + compatible = "qcom,qcs404-apcs-apps-global", "syscon"; + reg = <0x0b011000 0x1000>; + #mbox-cells = <1>; + clocks = <&gcc GCC_GPLL0_AO_OUT_MAIN>, <&apcs_hfpll>; + clock-names = "aux", "pll"; + #clock-cells = <0>; + }; -- cgit v1.2.3 From 10a46c9c551a29a7fea234abeb68884776b24b5b Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Thu, 13 Dec 2018 12:51:44 +0100 Subject: arm64: dts: qcom: qcs404: Add OPP table Add a CPU OPP table to qcs404 Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index dadfe42c3fec..42eaea4bb2df 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -63,6 +63,21 @@ }; }; + cpu_opp_table: cpu_opp_table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + }; + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-qcs404", "qcom,scm"; -- cgit v1.2.3 From 64de0810b3582990c9c55550a54ed2313c105ce4 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Thu, 13 Dec 2018 12:55:56 +0100 Subject: arm64: dts: qcom: qcs404: Add HFPLL node The high frequency pll functionality is required to enable CPU frequency scaling operation. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 42eaea4bb2df..923c3f41e40e 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -482,6 +482,15 @@ #mbox-cells = <1>; }; + apcs_hfpll: clock-controller@0b016000 { + compatible = "qcom,hfpll"; + reg = <0x0b016000 0x30>; + #clock-cells = <0>; + clock-output-names = "apcs_hfpll"; + clocks = <&xo_board>; + clock-names = "xo"; + }; + timer@b120000 { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 482dfaf8e191b4a8d23a8bf2b33ad0968b31ac30 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Fri, 14 Dec 2018 12:52:31 +0100 Subject: arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider Specify the clocks that feed the APCS mux/divider instead of using default hardcoded values in the source code. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 923c3f41e40e..5b9bbb0d0112 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -480,6 +480,9 @@ compatible = "qcom,qcs404-apcs-apps-global", "syscon"; reg = <0x0b011000 0x1000>; #mbox-cells = <1>; + clocks = <&gcc GCC_GPLL0_AO_OUT_MAIN>, <&apcs_hfpll>; + clock-names = "aux", "pll"; + #clock-cells = <0>; }; apcs_hfpll: clock-controller@0b016000 { -- cgit v1.2.3 From cf3fdbe9e93cb16e5dbd3b0465067850b36f1312 Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Wed, 19 Dec 2018 14:03:44 +0100 Subject: arm64: dts: qcom: qcs404: Add cpufreq support Support CPU frequency scaling on qcs404. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 5b9bbb0d0112..749fb27ca283 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -31,6 +31,8 @@ reg = <0x100>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; }; CPU1: cpu@101 { @@ -39,6 +41,8 @@ reg = <0x101>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; }; CPU2: cpu@102 { @@ -47,6 +51,8 @@ reg = <0x102>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; }; CPU3: cpu@103 { @@ -55,6 +61,8 @@ reg = <0x103>; enable-method = "psci"; next-level-cache = <&L2_0>; + clocks = <&apcs_glb>; + operating-points-v2 = <&cpu_opp_table>; }; L2_0: l2-cache { -- cgit v1.2.3 From 8cf22ee0132403b0bd01812da242ff1c6824aea4 Mon Sep 17 00:00:00 2001 From: Thierry Escande Date: Thu, 20 Dec 2018 14:20:42 +0100 Subject: arm64: dts: qcom: qcs404: Add fastrpc nodes This patch adds the adsp and cdsp fastrpc nodes nested under their respective glink nodes. Signed-off-by: Thierry Escande --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 65 ++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 749fb27ca283..5ee4bb5c8365 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -132,6 +132,34 @@ mboxes = <&apcs_glb 8>; label = "adsp"; + + #address-cells = <1>; + #size-cells = <0>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,msm_fastrpc_compute_cb_1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + }; + + qcom,msm_fastrpc_compute_cb_2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + }; + + qcom,msm_fastrpc_compute_cb_3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + shared-cb = <5>; + }; + }; }; }; @@ -163,6 +191,43 @@ mboxes = <&apcs_glb 12>; label = "cdsp"; + + #address-cells = <1>; + #size-cells = <0>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,msm_fastrpc_compute_cb_1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + }; + + qcom,msm_fastrpc_compute_cb_2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + }; + + qcom,msm_fastrpc_compute_cb_3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + }; + + qcom,msm_fastrpc_compute_cb_4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + }; + + qcom,msm_fastrpc_compute_cb_5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + }; + }; }; }; -- cgit v1.2.3 From 3079599785508d10758e35b9212d99f2ada123cb Mon Sep 17 00:00:00 2001 From: Jorge Ramirez-Ortiz Date: Thu, 3 Jan 2019 21:23:06 +0100 Subject: arm64: dts: qcom: qcs404: sdcc1: enable HS400 The controller can support EXT_CSD_CARD_TYPE_HS400_1_8V cards. Signed-off-by: Jorge Ramirez-Ortiz --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index 2f9d9706a6a4..f8fdc87ebd3a 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -148,6 +148,7 @@ status = "ok"; mmc-ddr-1_8v; + mmc-hs400-1_8v; bus-width = <8>; non-removable; -- cgit v1.2.3 From cd91eee446d79869eaa6d41a6e77752c82f10560 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 2 Nov 2018 17:16:08 -0700 Subject: arm64: dts: qcom: qcs404: Add USB devices and PHYs Add the two HS USB PHYs and the SS USB PHY found in the QCS404 platform and enable these in the EVB. QCS404 sports HS and SS USB controllers based on dwc3 block. Add these node and dummy phy for now which would be replaced by phy drivers Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 31 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/qcs404.dtsi | 26 ++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index f8fdc87ebd3a..f13c42d15ac2 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -280,3 +280,34 @@ qcom,vdd-voltage-level = <0 1050000 1050000>; status = "okay"; }; + +&usb2 { + status = "okay"; +}; + +&usb2_phy_prim { + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + qcom,vdd-voltage-level = <0 1144000 1200000>; + status = "okay"; +}; + +&usb2_phy_sec { + vdd-supply = <&vreg_l4_1p2>; + vdda1p8-supply = <&vreg_l5_1p8>; + vdda3p3-supply = <&vreg_l12_3p3>; + qcom,vdd-voltage-level = <0 1144000 1200000>; + status = "okay"; +}; + +&usb3 { + status = "disabled"; +}; + +&usb3_phy { + vdd-supply = <&vreg_l3_1p05>; + vdda1p8-supply = <&vreg_l5_1p8>; + qcom,vdd-voltage-level = <0 1050000 1050000>; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 5ee4bb5c8365..7255a29853fb 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -379,6 +379,19 @@ resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, <&gcc GCC_USB2A_PHY_BCR>; reset-names = "phy", "por"; + qcom,init-seq = <0xc0 0x01 0>, + <0xe8 0x0d 0>, + <0x74 0x12 0>, + <0x98 0x63 0>, + <0x9c 0x03 0>, + <0xa0 0x1d 0>, + <0xa4 0x03 0>, + <0x8c 0x23 0>, + <0x78 0x08 0>, + <0x7c 0xdc 0>, + <0x90 0xe0 20>, + <0x74 0x10 0>, + <0x90 0x60 0>; status = "disabled"; }; @@ -393,6 +406,19 @@ resets = <&gcc GCC_QUSB2_PHY_BCR>, <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; reset-names = "phy", "por"; + qcom,init-seq = <0xc0 0x01 0>, + <0xe8 0x0d 0>, + <0x74 0x12 0>, + <0x98 0x63 0>, + <0x9c 0x03 0>, + <0xa0 0x1d 0>, + <0xa4 0x03 0>, + <0x8c 0x23 0>, + <0x78 0x08 0>, + <0x7c 0xdc 0>, + <0x90 0xe0 20>, + <0x74 0x10 0>, + <0x90 0x60 0>; status = "disabled"; }; -- cgit v1.2.3