From bf83a0ab6b904abc121260503d000e5fb535b11f Mon Sep 17 00:00:00 2001 From: Tanmay Shah Date: Mon, 17 Aug 2020 15:53:00 -0700 Subject: arm64: dts: qcom: sc7180: Add Display Port dt node Add DP device node on sc7180. Changes in v2: - Add assigned-clocks and assigned-clock-parents - Remove cell-index and pixel_rcg - Change compatible to qcom,sc7180-dp Changes in v3: - Update commit text - Make DP child node of MDSS - Remove data-lanes property from SOC dts - Disable DP node in SOC dts - Assign DP to Port2 in MDP node - Add MDSS AHB clock in DP device node Changes in v4: - Remove redundant reg-names property - Use IRQ flag instead had hard coded value. - Add link clock source in assigned-clocks list. Changes in v5: - Add OPP table and power-domains for DisplayPort Changes in v6: - Remove redundant IRQ flag Signed-off-by: Tanmay Shah Co-developed-by: Kuogee Hsieh Signed-off-by: Kuogee Hsieh --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 76 +++++++++++++++++++++++++++++++++++- 1 file changed, 74 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 1ea3344ab62c..d3b65b72513d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3041,6 +3041,13 @@ remote-endpoint = <&dsi0_in>; }; }; + + port@2 { + reg = <2>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; + }; + }; }; mdp_opp_table: mdp-opp-table { @@ -3157,6 +3164,71 @@ status = "disabled"; }; + + msm_dp: displayport-controller@ae90000 { + status = "disabled"; + compatible = "qcom,sc7180-dp"; + + reg = <0 0x0ae90000 0 0x1400>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", "core_aux", "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + #clock-cells = <1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&msm_dp 0>, <&msm_dp 1>; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SC7180_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint { }; + }; + }; + + dp_opp_table: dp-opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; }; dispcc: clock-controller@af00000 { @@ -3166,8 +3238,8 @@ <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&dsi_phy 0>, <&dsi_phy 1>, - <0>, - <0>; + <&msm_dp 0>, + <&msm_dp 1>; clock-names = "bi_tcxo", "gcc_disp_gpll0_clk_src", "dsi0_phy_pll_out_byteclk", -- cgit v1.2.3 From 42f89f96cbd93131a3bc84c261990eb2893047d5 Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Wed, 12 Aug 2020 16:46:53 -0400 Subject: usb: typec: add gpio aux switch driver Signed-off-by: Jonathan Marek --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 76 +-------------------------- drivers/usb/typec/mux/Kconfig | 7 +++ drivers/usb/typec/mux/Makefile | 1 + drivers/usb/typec/mux/gpio_aux_switch.c | 91 +++++++++++++++++++++++++++++++++ 4 files changed, 101 insertions(+), 74 deletions(-) create mode 100644 drivers/usb/typec/mux/gpio_aux_switch.c diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index d3b65b72513d..1ea3344ab62c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3041,13 +3041,6 @@ remote-endpoint = <&dsi0_in>; }; }; - - port@2 { - reg = <2>; - dpu_intf0_out: endpoint { - remote-endpoint = <&dp_in>; - }; - }; }; mdp_opp_table: mdp-opp-table { @@ -3164,71 +3157,6 @@ status = "disabled"; }; - - msm_dp: displayport-controller@ae90000 { - status = "disabled"; - compatible = "qcom,sc7180-dp"; - - reg = <0 0x0ae90000 0 0x1400>; - - interrupt-parent = <&mdss>; - interrupts = <12>; - - clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, - <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, - <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; - clock-names = "core_iface", "core_aux", "ctrl_link", - "ctrl_link_iface", "stream_pixel"; - #clock-cells = <1>; - assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, - <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; - assigned-clock-parents = <&msm_dp 0>, <&msm_dp 1>; - - operating-points-v2 = <&dp_opp_table>; - power-domains = <&rpmhpd SC7180_CX>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; - dp_in: endpoint { - remote-endpoint = <&dpu_intf0_out>; - }; - }; - - port@1 { - reg = <1>; - dp_out: endpoint { }; - }; - }; - - dp_opp_table: dp-opp-table { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-270000000 { - opp-hz = /bits/ 64 <270000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-540000000 { - opp-hz = /bits/ 64 <540000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-810000000 { - opp-hz = /bits/ 64 <810000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - }; }; dispcc: clock-controller@af00000 { @@ -3238,8 +3166,8 @@ <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&dsi_phy 0>, <&dsi_phy 1>, - <&msm_dp 0>, - <&msm_dp 1>; + <0>, + <0>; clock-names = "bi_tcxo", "gcc_disp_gpll0_clk_src", "dsi0_phy_pll_out_byteclk", diff --git a/drivers/usb/typec/mux/Kconfig b/drivers/usb/typec/mux/Kconfig index edead555835e..087981d59f9f 100644 --- a/drivers/usb/typec/mux/Kconfig +++ b/drivers/usb/typec/mux/Kconfig @@ -19,4 +19,11 @@ config TYPEC_MUX_INTEL_PMC control the USB role switch and also the multiplexer/demultiplexer switches used with USB Type-C Alternate Modes. +config TYPEC_MUX_GPIO + tristate "GPIO DP aux switch" + depends on I2C + help + Driver for GPIO-controlled DP aux switch, to flip DP aux lanes + when orientation changes. + endmenu diff --git a/drivers/usb/typec/mux/Makefile b/drivers/usb/typec/mux/Makefile index 280a6f553115..4aeebe4df61f 100644 --- a/drivers/usb/typec/mux/Makefile +++ b/drivers/usb/typec/mux/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_TYPEC_MUX_PI3USB30532) += pi3usb30532.o obj-$(CONFIG_TYPEC_MUX_INTEL_PMC) += intel_pmc_mux.o +obj-$(CONFIG_TYPEC_MUX_GPIO) += gpio_aux_switch.o diff --git a/drivers/usb/typec/mux/gpio_aux_switch.c b/drivers/usb/typec/mux/gpio_aux_switch.c new file mode 100644 index 000000000000..6236b2a0b702 --- /dev/null +++ b/drivers/usb/typec/mux/gpio_aux_switch.c @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for GPIO controlled aux switch + * + * Copyright (C) 2020 The Linux Foundation + */ + +#include +#include +#include +#include +#include +#include + +struct gpio_aux_switch { + struct typec_mux *typec_mux; + struct gpio_desc *gpio_en, *gpio_cc; +}; + +static int gpio_typec_mux_set(struct typec_mux *mux, struct typec_mux_state *state) +{ + struct gpio_aux_switch *gas = typec_mux_get_drvdata(mux); + bool enable = false, reverse = false; + + if (!state->alt) + return 0; + + if (typec_altmode_get_orientation(state->alt) == TYPEC_ORIENTATION_REVERSE) + reverse = true; + + if (state->alt->svid == USB_TYPEC_DP_SID && state->alt->active) + enable = true; + + gpiod_set_value(gas->gpio_en, !enable); + gpiod_set_value(gas->gpio_cc, reverse); + + return 0; +} + +static int gpio_aux_switch_probe(struct platform_device *pdev) +{ + struct typec_mux_desc mux_desc = { }; + struct device *dev = &pdev->dev; + struct gpio_aux_switch *gas; + + gas = devm_kzalloc(dev, sizeof(*gas), GFP_KERNEL); + if (!gas) + return -ENOMEM; + + gas->gpio_en = devm_gpiod_get(dev, "enable", GPIOD_OUT_HIGH); + gas->gpio_cc = devm_gpiod_get(dev, "cc", GPIOD_OUT_LOW); + + mux_desc.fwnode = dev->fwnode; + mux_desc.drvdata = gas; + mux_desc.set = gpio_typec_mux_set; + gas->typec_mux = typec_mux_register(dev, &mux_desc); + if (IS_ERR(gas->typec_mux)) + return PTR_ERR(gas->typec_mux); + + platform_set_drvdata(pdev, gas); + + return 0; +} + +static int gpio_aux_switch_remove(struct platform_device *pdev) +{ + struct gpio_aux_switch *gas = platform_get_drvdata(pdev); + + typec_mux_unregister(gas->typec_mux); + + return 0; +} + +static const struct of_device_id gpio_aux_switch_dt_match[] = { + { .compatible = "gpio-aux-switch" }, + { } +}; + +static struct platform_driver gpio_aux_switch_driver = { + .driver = { + .name = "gpio-aux-switch", + .of_match_table = gpio_aux_switch_dt_match, + }, + .probe = gpio_aux_switch_probe, + .remove = gpio_aux_switch_remove, +}; + +module_platform_driver(gpio_aux_switch_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("GPIO AUX Switch driver"); -- cgit v1.2.3 From 1e4918f3c0da4c1afe20918720fae7ae9c74ae8a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Dec 2020 01:52:12 +0300 Subject: phy: qualcomm: phy-qcom-qmp: add support for combo USB3+DP phy on SDM845 Define configuration to be used by combo USB3 + DisplayPort phy on SDM845 SoC family. It closely follows sc7180, however like the main USB3 phy it uses the qmp_v3_usb3phy_cfg config. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 9cdebe7f26cb..00e1fcb1c512 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -2878,6 +2878,11 @@ static const struct qmp_phy_combo_cfg sc7180_usb3dpphy_cfg = { .dp_cfg = &sc7180_dpphy_cfg, }; +static const struct qmp_phy_combo_cfg sdm845_usb3dpphy_cfg = { + .usb_cfg = &qmp_v3_usb3phy_cfg, + .dp_cfg = &sc7180_dpphy_cfg, +}; + static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { .type = PHY_TYPE_USB3, .nlanes = 1, @@ -4556,6 +4561,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { }, { .compatible = "qcom,sdm845-qmp-usb3-uni-phy", .data = &qmp_v3_usb3_uniphy_cfg, + }, { + .compatible = "qcom,sdm845-qmp-usb3-dp-phy", + /* It's a combo phy */ }, { .compatible = "qcom,sdm845-qmp-ufs-phy", .data = &sdm845_ufsphy_cfg, @@ -4611,6 +4619,10 @@ static const struct of_device_id qcom_qmp_combo_phy_of_match_table[] = { .compatible = "qcom,sc7180-qmp-usb3-dp-phy", .data = &sc7180_usb3dpphy_cfg, }, + { + .compatible = "qcom,sdm845-qmp-usb3-dp-phy", + .data = &sdm845_usb3dpphy_cfg, + }, { } }; -- cgit v1.2.3 From 3577e4327400cf1c44cb1604143055dfe5548a2f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Dec 2020 01:54:43 +0300 Subject: arm64: qcom: sdm845: switch usb_1 phy to use combo usb+dp phy Change sdm845's usb_1_qmpphy to use combo usb+dp phy bindings, rather than just usb phy. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 454f794af547..9d7b6064ccb8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3668,10 +3668,10 @@ }; usb_1_qmpphy: phy@88e9000 { - compatible = "qcom,sdm845-qmp-usb3-phy"; + compatible = "qcom,sdm845-qmp-usb3-dp-phy"; reg = <0 0x088e9000 0 0x18c>, - <0 0x088e8000 0 0x10>; - reg-names = "reg-base", "dp_com"; + <0 0x088e8000 0 0x38>, + <0 0x088ea000 0 0x40>; status = "disabled"; #clock-cells = <1>; #address-cells = <2>; @@ -3684,11 +3684,11 @@ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; clock-names = "aux", "cfg_ahb", "ref", "com_aux"; - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; reset-names = "phy", "common"; - usb_1_ssphy: lanes@88e9200 { + usb_1_ssphy: usb3-phy@88e9200 { reg = <0 0x088e9200 0 0x128>, <0 0x088e9400 0 0x200>, <0 0x088e9c00 0 0x218>, @@ -3700,6 +3700,16 @@ clock-names = "pipe0"; clock-output-names = "usb3_phy_pipe_clk_src"; }; + + dp_phy: dp-phy@88ea200 { + reg = <0 0x088ea200 0 0x200>, + <0 0x088ea400 0 0x200>, + <0 0x088eaa00 0 0x200>, + <0 0x088ea600 0 0x200>, + <0 0x088ea800 0 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + }; }; usb_2_qmpphy: phy@88eb000 { @@ -4369,8 +4379,8 @@ <&dsi0_phy 1>, <&dsi1_phy 0>, <&dsi1_phy 1>, - <0>, - <0>; + <&dp_phy 0>, + <&dp_phy 1>; clock-names = "bi_tcxo", "gcc_disp_gpll0_clk_src", "gcc_disp_gpll0_div_clk_src", -- cgit v1.2.3 From de733d439dfb523755b661672f189cd5e84d337a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Dec 2020 03:05:10 +0300 Subject: arm64: dts: qcom: sdm845: add displayport node Add displayport controller device node, describing DisplayPort hardware block on SDM845. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 78 +++++++++++++++++++++++++++++++++++- 1 file changed, 76 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 9d7b6064ccb8..43d5970b3dc5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4065,13 +4065,20 @@ port@0 { reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; + dpu_intf0_out: endpoint { + remote-endpoint = <&dp_in>; }; }; port@1 { reg = <1>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@2 { + reg = <2>; dpu_intf2_out: endpoint { remote-endpoint = <&dsi1_in>; }; @@ -4103,6 +4110,73 @@ }; }; + msm_dp: displayport-controller@ae90000 { + status = "disabled"; + compatible = "qcom,sc7180-dp"; + + reg = <0 0x0ae90000 0 0x1400>; + + interrupt-parent = <&mdss>; + interrupts = <12>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; + clock-names = "core_iface", "core_aux", "ctrl_link", + "ctrl_link_iface", "stream_pixel"; + #clock-cells = <1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>; + phys = <&dp_phy>; + phy-names = "dp"; + + operating-points-v2 = <&dp_opp_table>; + power-domains = <&rpmhpd SDM845_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + dp_in: endpoint { + remote-endpoint = <&dpu_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_out: endpoint { }; + }; + }; + + dp_opp_table: dp-opp-table { + compatible = "operating-points-v2"; + + opp-162000000 { + opp-hz = /bits/ 64 <162000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + dsi0: dsi@ae94000 { compatible = "qcom,mdss-dsi-ctrl"; reg = <0 0x0ae94000 0 0x400>; -- cgit v1.2.3 From 5bf326c2b35aa0cd75208531a14ae6a17e532deb Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Dec 2020 03:05:54 +0300 Subject: WIP: arm64: dts: qcom: sdm845-db845c: enable DisplayPort support Enable DisplayPort device on DragonBoard 845c (RB3) board. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index c4ac6f5dc008..ef7e3f524fdf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -489,6 +489,13 @@ status = "okay"; }; +&msm_dp { + status = "okay"; + data-lanes = <0 1>; + vdda-1p2-supply = <&vreg_l26a_1p2>; + vdda-0p9-supply = <&vreg_l1a_0p875>; +}; + &mss_pil { status = "okay"; firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn"; -- cgit v1.2.3