From 9defba345b6af7704bb2725e2b1418ba4ce844ed Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 16 Nov 2021 14:58:19 +0300 Subject: arm64: dts: qcom: sm8450-qrd: tighten voltage regulators Tighten voltage regulators constraints according to the attached WLAN needs. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index f7592946c783..b3d1197a0336 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -70,13 +70,13 @@ vreg_s11b_0p95: smps11 { regulator-name = "vreg_s11b_0p95"; - regulator-min-microvolt = <848000>; + regulator-min-microvolt = <966000>; regulator-max-microvolt = <1104000>; }; vreg_s12b_1p25: smps12 { regulator-name = "vreg_s12b_1p25"; - regulator-min-microvolt = <1224000>; + regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1400000>; }; @@ -154,7 +154,7 @@ vreg_s1c_1p86: smps1 { regulator-name = "vreg_s1c_1p86"; - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <1900000>; regulator-max-microvolt = <2024000>; }; @@ -307,8 +307,8 @@ vreg_s2e_0p85: smps2 { regulator-name = "vreg_s2e_0p85"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1040000>; + regulator-min-microvolt = <1012000>; + regulator-max-microvolt = <1012000>; }; vreg_l1e_0p8: ldo1 { @@ -346,6 +346,12 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; }; + + vreg_l7e_2p8: ldo7 { + regulator-name = "vreg_l7e_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; }; }; -- cgit v1.2.3 From fa35be44234876f3a30f9c9464a33bf4fed9533c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Feb 2022 06:21:11 +0300 Subject: arm64: dts: qcom: sm8450-qrd: add wcn6855 dt node Add device tree node describing WiFi/BT chip power semantics. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 40 +++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index b3d1197a0336..969e16e33111 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -36,6 +36,24 @@ regulator-always-on; regulator-boot-on; }; + + wcn6856: wcn6856 { + compatible = "qcom,wcn6855"; + #power-domain-cells = <0>; + + vddaon-supply = <&vreg_s11b_0p95>; + vddcx-supply = <&vreg_s11b_0p95>; + vddmx-supply = <&vreg_s2e_0p85>; + vddrfa1-supply = <&vreg_s1c_1p86>; + vddrfa2-supply = <&vreg_s12b_1p25>; + vddio-supply = <&vreg_s10b_1p8>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_state &xo_clk_state>; + + xo-clk-gpios = <&tlmm 204 GPIO_ACTIVE_HIGH>; + wlan-en-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>; + }; }; &apps_rsc { @@ -434,6 +452,28 @@ drive-strength = <2>; bias-pull-up; }; + + xo_clk_state: xo_clk_state { + pinconf { + pins = "gpio204"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-down; + }; + }; + + wlan_en_state: wlan_en_state { + pinconf { + pins = "gpio80"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-down; + }; + }; }; &uart7 { -- cgit v1.2.3 From fd0333e4d32f5bacedbfbb2ef80e77d1dce08ed8 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Feb 2022 06:21:32 +0300 Subject: arm64: dts: qcom: sm8450-qrd: add bluetooth support Add QUP, UART and bluetooth device tree node to enable bluetooth on SM8450-QRD. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 969e16e33111..6752d89e1637 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -21,6 +21,7 @@ aliases { serial0 = &uart7; + serial1 = &uart20; }; chosen { @@ -399,6 +400,10 @@ status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &remoteproc_adsp { status = "okay"; firmware-name = "qcom/sm8450/adsp.mbn"; @@ -446,6 +451,17 @@ &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; + bt_en_state: bt-default-state { + bt-en { + pins = "gpio81"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-up; + }; + }; + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio92"; function = "gpio"; @@ -480,6 +496,18 @@ status = "okay"; }; +&uart20 { + status = "okay"; + bluetooth { + /* a little lie */ + compatible = "qcom,wcn6855-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_state>; + power-domains = <&wcn6856>; + enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + }; +}; + &ufs_mem_hc { status = "okay"; -- cgit v1.2.3 From 46b4f83ed741d57448002c982b0b045d460d6765 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Feb 2022 06:07:34 +0300 Subject: HACK: arm64: dts: qcom: sm8450-qrd: enable WiFi Add wcn-controller power domain to the pcie0 PHY node as a way to power up the WiFI part before enabling the PCIe bus. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 6752d89e1637..57fa3565a7d1 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -376,12 +376,15 @@ &pcie0 { status = "okay"; + max-link-speed = <2>; }; &pcie0_phy { status = "okay"; vdda-phy-supply = <&vreg_l5b_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; + + power-domains = <&wcn6856>; }; &gpi_dma0 { -- cgit v1.2.3 From 1a331954ee70c00be4b714eb90692cb54676a17d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 26 Feb 2022 23:30:19 +0300 Subject: dt-bindings: mfd: qcom-spmi-pmic: add pm8450 entry Add bindings for the PM8450 PMIC (qcom,pm8450). Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml index adf88245c409..256340f5ccb1 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml @@ -56,6 +56,7 @@ properties: - qcom,pm8350 - qcom,pm8350b - qcom,pm8350c + - qcom,pm8450 - qcom,pm8550 - qcom,pm8550b - qcom,pm8550ve -- cgit v1.2.3 From b12cea9bb00235a00f26453f9fee15b1c5fcd254 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Feb 2022 06:05:44 +0300 Subject: arm64: dts: qcom: sm8450-hdk: add wcn6855 dt node Add device tree node describing WiFi/BT chip power semantics. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 44 +++++++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index feef3837e4cd..340ac056e1af 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -96,6 +96,24 @@ regulator-always-on; regulator-boot-on; }; + + wcn6856: wcn6856 { + compatible = "qcom,wcn6855"; + #power-domain-cells = <0>; + + vddaon-supply = <&vreg_s11b_0p95>; + vddcx-supply = <&vreg_s11b_0p95>; + vddmx-supply = <&vreg_s2e_0p85>; + vddrfa1-supply = <&vreg_s1c_1p86>; + vddrfa2-supply = <&vreg_s12b_1p25>; + vddio-supply = <&vreg_s10b_1p8>; + + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_state &xo_clk_state>; + + xo-clk-gpios = <&tlmm 204 GPIO_ACTIVE_HIGH>; + wlan-en-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>; + }; }; &apps_rsc { @@ -215,7 +233,7 @@ vreg_s1c_1p86: smps1 { regulator-name = "vreg_s1c_1p86"; - regulator-min-microvolt = <1800000>; + regulator-min-microvolt = <1900000>; regulator-max-microvolt = <2024000>; }; @@ -368,7 +386,7 @@ vreg_s2e_0p85: smps2 { regulator-name = "vreg_s2e_0p85"; - regulator-min-microvolt = <500000>; + regulator-min-microvolt = <1012000>; regulator-max-microvolt = <1040000>; }; @@ -695,6 +713,28 @@ drive-strength = <2>; bias-pull-up; }; + + xo_clk_state: xo_clk_state { + pinconf { + pins = "gpio204"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-down; + }; + }; + + wlan_en_state: wlan_en_state { + pinconf { + pins = "gpio80"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-down; + }; + }; }; &uart7 { -- cgit v1.2.3 From 89852748c9583475dfa5e4f56c0607e1a20deac2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Feb 2022 06:06:37 +0300 Subject: arm64: dts: qcom: sm8450-hdk: add bluetooth support Add QUP, UART and bluetooth device tree node to enable bluetooth on SM8450-HDK. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 340ac056e1af..6ce012b37d73 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -22,6 +22,7 @@ aliases { serial0 = &uart7; + serial1 = &uart20; }; wcd938x: audio-codec { @@ -551,6 +552,10 @@ status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &sdhc_2 { cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; pinctrl-names = "default", "sleep"; @@ -695,6 +700,17 @@ &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; + bt_en_state: bt-default-state { + bt-en { + pins = "gpio81"; + function = "gpio"; + + drive-strength = <16>; + output-low; + bias-pull-up; + }; + }; + lt9611_irq_pin: lt9611-irq-state { pins = "gpio44"; function = "gpio"; @@ -741,6 +757,18 @@ status = "okay"; }; +&uart20 { + status = "okay"; + bluetooth { + /* a little lie */ + compatible = "qcom,wcn6855-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_state>; + power-domains = <&wcn6856>; + enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + }; +}; + &ufs_mem_hc { status = "okay"; -- cgit v1.2.3 From 08af893127550ad4d17679070a4806bfb7af7d5e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 27 Feb 2022 06:07:34 +0300 Subject: HACK: arm64: dts: qcom: sm8450-hdk: enable WiFi Add wcn-controller power domain to the pcie0 PHY node as a way to power up the WiFI part before enabling the PCIe bus. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 6ce012b37d73..a26cb68663ad 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -512,6 +512,8 @@ status = "okay"; vdda-phy-supply = <&vreg_l5b_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; + + power-domains = <&wcn6856>; }; &pcie1 { -- cgit v1.2.3 From 6e676abc6141c7ab93df492dcc534b6f033d5526 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 11 Apr 2022 15:34:17 +0300 Subject: arm64: dts: qcom: sm8450: provide additional MSI interrupts On SM8450 each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe0 host. Tested on Qualcomm RB5 platform with first group of MSI interrupts being used by the PME and attached ath11k WiFi chip using second group of MSI interrupts. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1a744a33bcf4..ae1e3302c32e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1756,8 +1756,15 @@ msi-map = <0x0 &gic_its 0x5981 0x1>, <0x100 &gic_its 0x5980 0x1>; msi-map-mask = <0xff00>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ -- cgit v1.2.3 From 3d462a39a5b89d094ee21b46e25cbc79e0c02327 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 19 Dec 2022 14:06:19 +0530 Subject: dt-bindings: PCI: qcom: Document msi-map and msi-map-mask properties The Qcom PCIe controller is capable of using either internal MSI controller or the external GIC-ITS for receiving the MSIs from endpoint devices. Currently, the binding only documents the internal MSI implementation. Let's document the GIC-ITS imeplementation by making use of msi-map and msi-map-mask properties. Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index fb32c43dd12d..65496b2367ba 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -116,18 +116,28 @@ properties: description: GPIO controlled connection to WAKE# signal maxItems: 1 + msi-map: true + + msi-map-mask: true + required: - compatible - reg - reg-names - - interrupts - - interrupt-names - - "#interrupt-cells" - interrupt-map-mask - interrupt-map - clocks - clock-names +oneOf: + - required: + - interrupts + - interrupt-names + - "#interrupt-cells" + - required: + - msi-map + - msi-map-mask + allOf: - $ref: /schemas/pci/pci-bus.yaml# - if: -- cgit v1.2.3 From 34414e05bee8b9a0ebb1d6a78648772cab70cc67 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 30 Jan 2023 10:54:36 +0100 Subject: arm64: dts: qcom: sm8450-hdk: add pmic glink node Add the pmic glink node linked with the DWC3 USB controller switched to OTG mode and tagged with usb-role-switch. Link: https://lore.kernel.org/r/20230130-topic-sm8450-upstream-pmic-glink-v1-5-0b0acfad301e@linaro.org Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 34 ++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index a26cb68663ad..a86198fa4da7 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -88,6 +88,31 @@ enable-active-high; }; + pmic-glink { + compatible = "qcom,sm8450-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + pmic_glink_dwc3_in: endpoint { + remote-endpoint = <&usb_1_dwc3_out>; + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -794,7 +819,14 @@ }; &usb_1_dwc3 { - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; + + port { + usb_1_dwc3_out: endpoint { + remote-endpoint = <&pmic_glink_dwc3_in>; + }; + }; }; &usb_1_hsphy { -- cgit v1.2.3 From 3581137c648b9cee491e3dfd990471655120ec07 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 12:15:32 +0100 Subject: arm64: dts: qcom: sm8450: correct WSA2 assigned clocks The WSA2 assigned-clocks were copied from WSA, but the WSA2 uses its own. Fixes: 14341e76dbc7 ("arm64: dts: qcom: sm8450: add Soundwire and LPASS") Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index ae1e3302c32e..5cc15629a56c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2150,8 +2150,8 @@ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&vamacro>; clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; - assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, - <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; assigned-clock-rates = <19200000>, <19200000>; #clock-cells = <0>; -- cgit v1.2.3 From 2f6a849aac597a5ed5eb933d2be2abd587d90aa7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 15:17:44 +0100 Subject: arm64: dts: qcom: sm8450-hdk: use recommended drive strength for speaker SD_N Downstream DTS (and sc8280xp-lenovo-thinkpad-x13s with the same speakers) uses 16 mA drive strength for the WSA8835 speaker SD_N reset/shutdown pin. Use the same for HDK8450, as it is seem the recommended value. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index a86198fa4da7..b39e957e53a6 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -857,7 +857,7 @@ spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio1"; function = "gpio"; - drive-strength = <4>; + drive-strength = <16>; bias-disable; output-low; }; @@ -865,7 +865,7 @@ spkr_2_sd_n_active: spkr-2-sd-n-active-state { pins = "gpio89"; function = "gpio"; - drive-strength = <4>; + drive-strength = <16>; bias-disable; output-low; }; -- cgit v1.2.3 From da3962ed3debe5b652ccb77b47674fbb56613169 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 18:32:51 +0100 Subject: arm64: dts: qcom: sm8450-hdk: use precise WCD9385 compatible The HDK8450 uses WCD9385 audio codec, so use precise compatible, even though WCD9380 and WCD9385 are both compatible. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index b39e957e53a6..d6b0974ed85b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -26,7 +26,7 @@ }; wcd938x: audio-codec { - compatible = "qcom,wcd9380-codec"; + compatible = "qcom,wcd9385-codec"; pinctrl-names = "default"; pinctrl-0 = <&wcd_default>; -- cgit v1.2.3 From 028c6e749fd890e68e710ca1d6d941dc5a77b8c5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 18:34:21 +0100 Subject: arm64: dts: qcom: sm8450-hdk: align WCD9385 reset pin with downstream config Downstream DTS uses 16 mA drive strength for the WCD9385 audio codec RESET_N reset pin. It also pulls the pin down in shutdown mode, thus it is more like a shutdown pin, not a reset. Use the same settings here for HDK8450 and keep the WCD9385 by default in powered off (so pin as low). Align the name of pin configuration node with other pins in the DTS. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index d6b0974ed85b..d86712bd96e5 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -870,9 +870,11 @@ output-low; }; - wcd_default: wcd-default-state { + wcd_default: wcd-reset-n-active-state { pins = "gpio43"; function = "gpio"; + drive-strength = <16>; bias-disable; + output-low; }; }; -- cgit v1.2.3