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2022-01-28Merge remote-tracking branch 'sm8450-dts/tracking-qcomlt-sm8450-dts' into ↵Linaro CI
integration-linux-qcomlt
2022-01-28Merge remote-tracking branch 'sm8450-drivers/tracking-qcomlt-sm8450-drivers' ↵Linaro CI
into integration-linux-qcomlt
2022-01-28Merge remote-tracking branch ↵Linaro CI
'sa8155p-adp-dts-drivers/tracking-qcomlt-sa8155p-dts-drivers' into integration-linux-qcomlt
2022-01-28Merge remote-tracking branch 'sm8350-drivers/tracking-qcomlt-sm8350-drivers' ↵Linaro CI
into integration-linux-qcomlt # Conflicts: # Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.txt
2022-01-28Merge remote-tracking branch 'sdx55-dts/tracking-qcomlt-sdx55-dts' into ↵Linaro CI
integration-linux-qcomlt
2022-01-28Merge remote-tracking branch 'sdx55-drivers/tracking-qcomlt-sdx55-drivers' ↵Linaro CI
into integration-linux-qcomlt # Conflicts: # scripts/mod/file2alias.c
2022-01-28Merge remote-tracking branch 'lt9611-fix-4k/tracking-qcomlt-lt9611-fix-4k' ↵Linaro CI
into integration-linux-qcomlt
2022-01-28Merge remote-tracking branch ↵Linaro CI
'ov8856-remove-mode/tracking-qcomlt-ov8856-remove-mode' into integration-linux-qcomlt # Conflicts: # drivers/media/i2c/ov8856.c
2022-01-28Merge remote-tracking branch 'gsi/tracking-qcomlt-gsi' into ↵Linaro CI
integration-linux-qcomlt
2022-01-28Merge remote-tracking branch 'interconnect/tracking-qcomlt-interconnect' ↵Linaro CI
into integration-linux-qcomlt # Conflicts: # arch/arm64/configs/defconfig
2022-01-28Merge remote-tracking branch 'db820c-fixes/db820c/5.7-rc1' into ↵Linaro CI
integration-linux-qcomlt # Conflicts: # drivers/clk/qcom/Kconfig # drivers/clk/qcom/Makefile # drivers/clk/qcom/clk-cpu-8996.c # drivers/soc/qcom/Kconfig # drivers/soc/qcom/kryo-l2-accessors.c
2022-01-28Merge remote-tracking branch 'cpufeq/tracking-qcomlt-cpufreq-fixes' into ↵Linaro CI
integration-linux-qcomlt
2022-01-28Merge remote-tracking branch 'sm8250-typec/tracking-qcomlt-sm8250-typec' ↵Linaro CI
into integration-linux-qcomlt # Conflicts: # arch/arm64/configs/defconfig # drivers/usb/typec/mux/Kconfig # drivers/usb/typec/mux/Makefile
2022-01-28Merge remote-tracking branch 'sm8250-gdsc/tracking-qcomlt-sm8250-gdsc' into ↵Linaro CI
integration-linux-qcomlt # Conflicts: # drivers/clk/qcom/gdsc.h
2022-01-28Merge remote-tracking branch 'sm8250/tracking-qcomlt-sm8250' into ↵Linaro CI
integration-linux-qcomlt
2022-01-28Merge remote-tracking branch 'qca6390/tracking-qcomlt-qca6390' into ↵Linaro CI
integration-linux-qcomlt # Conflicts: # drivers/net/wireless/ath/ath11k/dp_rx.c # drivers/net/wireless/ath/ath11k/wmi.c
2022-01-28Merge remote-tracking branch 'lpg/tracking-qcomlt-lpg' into ↵Linaro CI
integration-linux-qcomlt
2022-01-28Merge remote-tracking branch 'fixes-lumag/tracking-qcomlt-fixes-lumag' into ↵Linaro CI
integration-linux-qcomlt
2022-01-28Merge remote-tracking branch ↵Linaro CI
'qcs404-defconfig/tracking-qcomlt-qcs404-defconfig' into integration-linux-qcomlt
2022-01-28Merge remote-tracking branch 'sdm845-dp/tracking-qcomlt-sdm845-dp' into ↵Linaro CI
integration-linux-qcomlt # Conflicts: # arch/arm64/boot/dts/qcom/sdm845-db845c.dts # arch/arm64/boot/dts/qcom/sdm845.dtsi # drivers/phy/qualcomm/phy-qcom-qmp.c
2022-01-28Merge remote-tracking branch 'sdm845-usb/tracking-qcomlt-usb-renesas' into ↵Linaro CI
integration-linux-qcomlt # Conflicts: # drivers/usb/host/xhci-pci-renesas.c
2022-01-28Merge remote-tracking branch 'bus-scaling/icc-testing' into ↵Linaro CI
integration-linux-qcomlt
2022-01-28Merge remote-tracking branch ↵Linaro CI
'distro.config/tracking-qcomlt-config-fragments' into integration-linux-qcomlt
2022-01-28Merge remote-tracking branch ↵Linaro CI
'arm64-defconfig/tracking-qcomlt-arm64-defconfig' into integration-linux-qcomlt
2022-01-28Merge remote-tracking branch 'drm-msm/tracking-qcomlt-drm-msm' into ↵Linaro CI
integration-linux-qcomlt
2022-01-28Merge remote-tracking branch 'audio/tracking-qcomlt-audio' into ↵Linaro CI
integration-linux-qcomlt
2022-01-28Merge remote-tracking branch 'wcd9335/tracking-qcomlt-wcd9335' into ↵Linaro CI
integration-linux-qcomlt
2022-01-28arm64: dts: qcom: sm8450: Add thermal zonesVladimir Zapolskiy
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> [DB: fixed thermal zone names] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28arm64: dts: qcom: sm8450: Add thermal sensor controllersVladimir Zapolskiy
The change adds description of two thermal sensor controllers found on SM8450. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
2022-01-28HACK: arm64: dts: qcom: sm8450-qrd: enable wlan device found on PCIe0Dmitry Baryshkov
While we do not support proper power sequencing for the WiFi+BT chips, hack this by daisy chaining all required voltage regulators. This makes regulator core switch them on one by one in the correct order. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28arm64: dts: qcom: sm8450-qrd: tighten voltage regulatorsDmitry Baryshkov
Tighten voltage regulators constraints according to the attached WLAN needs. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28arm64: dts: qcom: sm8450-qrd: enable PCIe0 hostDmitry Baryshkov
Enable PCIe0 host on SM8450 QRD device. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28arm64: dts: qcom: sm8450-qrd: enable PCIe0 PHY deviceDmitry Baryshkov
Enable PCIe0 PHY on the SM8450 QRD device. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28arm64: dts: qcom: sm8450: add PCIe1 root deviceDmitry Baryshkov
Add device tree node for the second PCIe host found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28arm64: dts: qcom: sm8450: add PCIe1 PHY nodeDmitry Baryshkov
Add device tree node for the second PCIe PHY device found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28arm64: dts: qcom: sm8450: add PCIe0 RC deviceDmitry Baryshkov
Add device tree node for the first PCIe host found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2022-01-28arm64: dts: qcom: sm8450: add PCIe0 PHY nodeDmitry Baryshkov
Add device tree node for the first PCIe PHY device found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28arm64: dts: qcom: add ITS device tree nodeDmitry Baryshkov
Add device tree node corresponding to the ITS part of GICv3. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28arm64: dts: qcom: sm8450: Add usb nodesVinod Koul
SM8450 features a single USB controller which connects to both HS and SS phy. Add the USB and the phy nodes for Qualcomm SM8450 SoC. Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-28arm64: dts: qcom: sm8450: add cpufreq supportVladimir Zapolskiy
The change adds a description of a SM8450 cpufreq-epss controller and references to it from CPU nodes. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-28of: property: do not create clocks device link for clock controllersDmitry Baryshkov
Do not create device link for clock controllers. Some of the clocks provided to the device via OF can be the clocks that are just parents to the clocks provided by this clock controller. Clock subsystem already has support for handling missing clock parents correctly (clock orphans). Later when the parent clock is registered, clocks get populated properly. An example of the system where this matters is the SDM8450 MTP board (see arch/arm64/boot/dts/qcom/sdm845-mtp.dts). Here the dispcc uses clocks provided by dsi0_phy and dsi1_phy device tree nodes. However the dispcc itself provides clocks to both PHYs, to the PHY parent device, etc. With just dsi0_phy in place devlink is able to break the dependency, but with two PHYs, dispcc doesn't get probed at all, thus breaking display support. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Saravana Kannan <saravanak@google.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28Revert "of: property: fw_devlink: Add support for remote-endpoint"Dmitry Baryshkov
This reverts commit f7514a6630166a7b566dee9b1af2e87e431959be. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28drm/msm/dpu1: dpu_encoder_phys_*: proper suppor for active CTLsDmitry Baryshkov
Adapt dpu_encoder_phys_* to properly support active CTLs and their features. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28drm/msm/dpu1: use one active CTL if it is availableDmitry Baryshkov
Unlike previous generation, with newer ("active") CTLs it is possible to use just one CTL to handle both interfaces. And one has to use single CTL to support master/slave DSI config. So use one active CTL if it is available. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28drm/msm/dpu1: improve support for active CTLsDmitry Baryshkov
- Support setting master interface if several INTFs are to be handled by a single CTL - Support setting handling several MERGE_3D instances using a single CTL. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28arm64: dts: qcom: add qrb5165-rb5 DTS with dual DSI enabledDmitry Baryshkov
Add a variant of the RB5 platform's device tree having both DSI channels connected to the lt9611uxc bridge in the dual DSI mode. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28drm/bridge/lontium-lt9611uxc: add proper support for dual-DSI modeDmitry Baryshkov
Program DSI registers depending on the ports enabled in the device tree. A, B and A+B setups are supported. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28drm/msm/dsi: pll_7nm: remove unsupported dividers for DSI pixel clockDmitry Baryshkov
Remove dividers that are not recommended for DSI DPHY mode when setting up the clock tree for the DSI pixel clock. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28arm64: dts: qcom: sm8250: populate idle states informationDmitry Baryshkov
Populate CPU's idle state information basing on msm-4.19 data. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2022-01-28drm/msm/dsi: save PLL registers across first PHY resetBenjamin Li
Take advantage of previously-added support for persisting PLL registers across DSI PHY disable/enable cycles (see 328e1a6 'drm/msm/dsi: Save/Restore PLL status across PHY reset') to support persisting across the very first DSI PHY enable at boot. The bootloader may have left the PLL registers in a non-default state. For example, for dsi_pll_28nm.c on 8x16/8x39, the byte clock mux's power-on reset configuration is to bypass DIV1, but depending on bandwidth requirements[1] the bootloader may have set the DIV1 path. When the byte clock mux is registered with the generic clock framework at probe time, the framework reads & caches the value of the mux bit field (the initial clock parent). After PHY enable, when clk_set_rate is called on the byte clock, the framework assumes there is no need to reparent, and doesn't re-write the mux bit field. But PHY enable resets PLL registers, so the mux bit field actually silently reverted to the DIV1 bypass path. This causes the byte clock to be off by a factor of e.g. 2 for our tested WXGA panel. The above issue manifests as the display not working and a constant stream of FIFO/LP0 contention errors. [1] The specific requirement for triggering the DIV1 path (and thus this issue) on 28nm is a panel with pixel clock <116.7MHz (one-third the minimum VCO setting). FHD/1080p (~145MHz) is fine, WXGA/1280x800 (~75MHz) is not. Signed-off-by: Benjamin Li <benl@squareup.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-21 00:13:08 +0000