diff options
author | Linaro CI <ci_notify@linaro.org> | 2023-04-26 13:36:24 +0000 |
---|---|---|
committer | Linaro CI <ci_notify@linaro.org> | 2023-04-26 13:36:24 +0000 |
commit | d242e898339d52006af99ce00a23fb6456f0c491 (patch) | |
tree | 7dc96351ec3e2cbf1a6fb08b0606f2645af735d3 /drivers | |
parent | 0cbce2f2a7c7ca2306237779fd347652e95435c2 (diff) | |
parent | 64689cb98d9ab8602142b1b6c49c75a332d60901 (diff) |
Merge remote-tracking branch 'RB1/tracking-rb1' into integration-linux-qcomlt
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/clk/qcom/dispcc-qcm2290.c | 32 | ||||
-rw-r--r-- | drivers/clk/qcom/gcc-qcm2290.c | 62 | ||||
-rw-r--r-- | drivers/gpu/drm/bridge/lontium-lt9611uxc.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/msm/dsi/dsi.c | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/msm/dsi/dsi_cfg.c | 161 | ||||
-rw-r--r-- | drivers/gpu/drm/msm/dsi/dsi_cfg.h | 9 | ||||
-rw-r--r-- | drivers/gpu/drm/msm/dsi/dsi_host.c | 14 | ||||
-rw-r--r-- | drivers/iio/adc/qcom-spmi-adc5.c | 16 | ||||
-rw-r--r-- | drivers/interconnect/qcom/Makefile | 2 | ||||
-rw-r--r-- | drivers/interconnect/qcom/ddr-go-brr.c | 55 | ||||
-rw-r--r-- | drivers/interconnect/qcom/icc-rpm.c | 3 |
11 files changed, 195 insertions, 168 deletions
diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c index 2ebd9a02b895..4983b5418c26 100644 --- a/drivers/clk/qcom/dispcc-qcm2290.c +++ b/drivers/clk/qcom/dispcc-qcm2290.c @@ -20,13 +20,15 @@ #include "clk-regmap-divider.h" #include "common.h" #include "gdsc.h" +#include "reset.h" enum { P_BI_TCXO, + P_BI_TCXO_AO, P_DISP_CC_PLL0_OUT_MAIN, P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, - P_DSI1_PHY_PLL_OUT_DSICLK, + P_GPLL0_OUT_DIV, P_GPLL0_OUT_MAIN, P_SLEEP_CLK, }; @@ -82,8 +84,8 @@ static const struct clk_parent_data disp_cc_parent_data_1[] = { }; static const struct parent_map disp_cc_parent_map_2[] = { - { P_BI_TCXO, 0 }, - { P_GPLL0_OUT_MAIN, 4 }, + { P_BI_TCXO_AO, 0 }, + { P_GPLL0_OUT_DIV, 4 }, }; static const struct clk_parent_data disp_cc_parent_data_2[] = { @@ -106,13 +108,11 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = { static const struct parent_map disp_cc_parent_map_4[] = { { P_BI_TCXO, 0 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, - { P_DSI1_PHY_PLL_OUT_DSICLK, 2 }, }; static const struct clk_parent_data disp_cc_parent_data_4[] = { { .fw_name = "bi_tcxo" }, { .fw_name = "dsi0_phy_pll_out_dsiclk" }, - { .fw_name = "dsi1_phy_pll_out_dsiclk" }, }; static const struct parent_map disp_cc_parent_map_5[] = { @@ -133,7 +133,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), /* For set_rate and set_parent to succeed, parent(s) must be enabled */ - .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE | CLK_GET_RATE_NOCACHE, .ops = &clk_byte2_ops, }, }; @@ -153,9 +153,9 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { }; static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { - F(19200000, P_BI_TCXO, 1, 0, 0), - F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(19200000, P_BI_TCXO_AO, 1, 0, 0), + F(37500000, P_GPLL0_OUT_DIV, 8, 0, 0), + F(75000000, P_GPLL0_OUT_DIV, 4, 0, 0), { } }; @@ -226,7 +226,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .parent_data = disp_cc_parent_data_4, .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), /* For set_rate and set_parent to succeed, parent(s) must be enabled */ - .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE, + .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE | CLK_GET_RATE_NOCACHE, .ops = &clk_pixel_ops, }, }; @@ -295,7 +295,7 @@ static struct clk_branch disp_cc_mdss_byte0_clk = { &disp_cc_mdss_byte0_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, .ops = &clk_branch2_ops, }, }, @@ -313,7 +313,7 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = { &disp_cc_mdss_byte0_div_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, .ops = &clk_branch2_ops, }, }, @@ -403,7 +403,7 @@ static struct clk_branch disp_cc_mdss_pclk0_clk = { &disp_cc_mdss_pclk0_clk_src.clkr.hw, }, .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, .ops = &clk_branch2_ops, }, }, @@ -445,6 +445,10 @@ static struct clk_branch disp_cc_sleep_clk = { }, }; +static const struct qcom_reset_map disp_cc_qcm2290_resets[] = { + [DISP_CC_MDSS_CORE_BCR] = { 0x2000 }, +}; + static struct gdsc mdss_gdsc = { .gdscr = 0x3000, .pd = { @@ -494,6 +498,8 @@ static const struct qcom_cc_desc disp_cc_qcm2290_desc = { .num_clks = ARRAY_SIZE(disp_cc_qcm2290_clocks), .gdscs = disp_cc_qcm2290_gdscs, .num_gdscs = ARRAY_SIZE(disp_cc_qcm2290_gdscs), + .resets = disp_cc_qcm2290_resets, + .num_resets = ARRAY_SIZE(disp_cc_qcm2290_resets), }; static const struct of_device_id disp_cc_qcm2290_match_table[] = { diff --git a/drivers/clk/qcom/gcc-qcm2290.c b/drivers/clk/qcom/gcc-qcm2290.c index 7792b8f23704..bf9d17169b37 100644 --- a/drivers/clk/qcom/gcc-qcm2290.c +++ b/drivers/clk/qcom/gcc-qcm2290.c @@ -650,7 +650,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { .name = "gcc_usb30_prim_mock_utmi_clk_src", .parent_data = gcc_parents_0, .num_parents = ARRAY_SIZE(gcc_parents_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -686,7 +686,7 @@ static struct clk_rcg2 gcc_camss_axi_clk_src = { .name = "gcc_camss_axi_clk_src", .parent_data = gcc_parents_4, .num_parents = ARRAY_SIZE(gcc_parents_4), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -706,7 +706,7 @@ static struct clk_rcg2 gcc_camss_cci_clk_src = { .name = "gcc_camss_cci_clk_src", .parent_data = gcc_parents_9, .num_parents = ARRAY_SIZE(gcc_parents_9), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -728,7 +728,7 @@ static struct clk_rcg2 gcc_camss_csi0phytimer_clk_src = { .name = "gcc_camss_csi0phytimer_clk_src", .parent_data = gcc_parents_5, .num_parents = ARRAY_SIZE(gcc_parents_5), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -742,7 +742,7 @@ static struct clk_rcg2 gcc_camss_csi1phytimer_clk_src = { .name = "gcc_camss_csi1phytimer_clk_src", .parent_data = gcc_parents_5, .num_parents = ARRAY_SIZE(gcc_parents_5), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -764,7 +764,7 @@ static struct clk_rcg2 gcc_camss_mclk0_clk_src = { .parent_data = gcc_parents_3, .num_parents = ARRAY_SIZE(gcc_parents_3), .flags = CLK_OPS_PARENT_ENABLE, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -779,7 +779,7 @@ static struct clk_rcg2 gcc_camss_mclk1_clk_src = { .parent_data = gcc_parents_3, .num_parents = ARRAY_SIZE(gcc_parents_3), .flags = CLK_OPS_PARENT_ENABLE, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -794,7 +794,7 @@ static struct clk_rcg2 gcc_camss_mclk2_clk_src = { .parent_data = gcc_parents_3, .num_parents = ARRAY_SIZE(gcc_parents_3), .flags = CLK_OPS_PARENT_ENABLE, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -809,7 +809,7 @@ static struct clk_rcg2 gcc_camss_mclk3_clk_src = { .parent_data = gcc_parents_3, .num_parents = ARRAY_SIZE(gcc_parents_3), .flags = CLK_OPS_PARENT_ENABLE, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -830,7 +830,7 @@ static struct clk_rcg2 gcc_camss_ope_ahb_clk_src = { .name = "gcc_camss_ope_ahb_clk_src", .parent_data = gcc_parents_6, .num_parents = ARRAY_SIZE(gcc_parents_6), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -854,7 +854,7 @@ static struct clk_rcg2 gcc_camss_ope_clk_src = { .parent_data = gcc_parents_6, .num_parents = ARRAY_SIZE(gcc_parents_6), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -888,7 +888,7 @@ static struct clk_rcg2 gcc_camss_tfe_0_clk_src = { .name = "gcc_camss_tfe_0_clk_src", .parent_data = gcc_parents_7, .num_parents = ARRAY_SIZE(gcc_parents_7), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -912,7 +912,7 @@ static struct clk_rcg2 gcc_camss_tfe_0_csid_clk_src = { .name = "gcc_camss_tfe_0_csid_clk_src", .parent_data = gcc_parents_8, .num_parents = ARRAY_SIZE(gcc_parents_8), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -926,7 +926,7 @@ static struct clk_rcg2 gcc_camss_tfe_1_clk_src = { .name = "gcc_camss_tfe_1_clk_src", .parent_data = gcc_parents_7, .num_parents = ARRAY_SIZE(gcc_parents_7), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -940,7 +940,7 @@ static struct clk_rcg2 gcc_camss_tfe_1_csid_clk_src = { .name = "gcc_camss_tfe_1_csid_clk_src", .parent_data = gcc_parents_8, .num_parents = ARRAY_SIZE(gcc_parents_8), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -963,7 +963,7 @@ static struct clk_rcg2 gcc_camss_tfe_cphy_rx_clk_src = { .parent_data = gcc_parents_10, .num_parents = ARRAY_SIZE(gcc_parents_10), .flags = CLK_OPS_PARENT_ENABLE, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -984,7 +984,7 @@ static struct clk_rcg2 gcc_camss_top_ahb_clk_src = { .name = "gcc_camss_top_ahb_clk_src", .parent_data = gcc_parents_4, .num_parents = ARRAY_SIZE(gcc_parents_4), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1006,7 +1006,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { .name = "gcc_gp1_clk_src", .parent_data = gcc_parents_2, .num_parents = ARRAY_SIZE(gcc_parents_2), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1020,7 +1020,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { .name = "gcc_gp2_clk_src", .parent_data = gcc_parents_2, .num_parents = ARRAY_SIZE(gcc_parents_2), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1034,7 +1034,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { .name = "gcc_gp3_clk_src", .parent_data = gcc_parents_2, .num_parents = ARRAY_SIZE(gcc_parents_2), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1054,7 +1054,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { .name = "gcc_pdm2_clk_src", .parent_data = gcc_parents_0, .num_parents = ARRAY_SIZE(gcc_parents_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1082,7 +1082,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { .name = "gcc_qupv3_wrap0_s0_clk_src", .parent_data = gcc_parents_1, .num_parents = ARRAY_SIZE(gcc_parents_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { @@ -1098,7 +1098,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { .name = "gcc_qupv3_wrap0_s1_clk_src", .parent_data = gcc_parents_1, .num_parents = ARRAY_SIZE(gcc_parents_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { @@ -1114,7 +1114,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { .name = "gcc_qupv3_wrap0_s2_clk_src", .parent_data = gcc_parents_1, .num_parents = ARRAY_SIZE(gcc_parents_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { @@ -1130,7 +1130,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { .name = "gcc_qupv3_wrap0_s3_clk_src", .parent_data = gcc_parents_1, .num_parents = ARRAY_SIZE(gcc_parents_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { @@ -1146,7 +1146,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { .name = "gcc_qupv3_wrap0_s4_clk_src", .parent_data = gcc_parents_1, .num_parents = ARRAY_SIZE(gcc_parents_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { @@ -1162,7 +1162,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { .name = "gcc_qupv3_wrap0_s5_clk_src", .parent_data = gcc_parents_1, .num_parents = ARRAY_SIZE(gcc_parents_1), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }; static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { @@ -1219,7 +1219,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { .name = "gcc_sdcc1_ice_core_clk_src", .parent_data = gcc_parents_0, .num_parents = ARRAY_SIZE(gcc_parents_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1265,7 +1265,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { .name = "gcc_usb30_prim_master_clk_src", .parent_data = gcc_parents_0, .num_parents = ARRAY_SIZE(gcc_parents_0), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1279,7 +1279,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { .name = "gcc_usb3_prim_phy_aux_clk_src", .parent_data = gcc_parents_13, .num_parents = ARRAY_SIZE(gcc_parents_13), - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -1302,7 +1302,7 @@ static struct clk_rcg2 gcc_video_venus_clk_src = { .parent_data = gcc_parents_14, .num_parents = ARRAY_SIZE(gcc_parents_14), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; diff --git a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c index e384eff24859..dbcab0dca3ec 100644 --- a/drivers/gpu/drm/bridge/lontium-lt9611uxc.c +++ b/drivers/gpu/drm/bridge/lontium-lt9611uxc.c @@ -196,7 +196,7 @@ static void lt9611uxc_reset(struct lt9611uxc *lt9611uxc) msleep(20); gpiod_set_value_cansleep(lt9611uxc->reset_gpio, 1); - msleep(300); + msleep(1000); } static void lt9611uxc_assert_5v(struct lt9611uxc *lt9611uxc) diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c index 31fdee2052be..baab79ab6e74 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.c +++ b/drivers/gpu/drm/msm/dsi/dsi.c @@ -4,7 +4,6 @@ */ #include "dsi.h" -#include "dsi_cfg.h" bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) { @@ -173,8 +172,10 @@ static int dsi_dev_remove(struct platform_device *pdev) } static const struct of_device_id dt_match[] = { - { .compatible = "qcom,mdss-dsi-ctrl", .data = NULL /* autodetect cfg */ }, - { .compatible = "qcom,dsi-ctrl-6g-qcm2290", .data = &qcm2290_dsi_cfg_handler }, + { .compatible = "qcom,mdss-dsi-ctrl" }, + + /* Deprecated, don't use */ + { .compatible = "qcom,dsi-ctrl-6g-qcm2290" }, {} }; diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index 6d21f0b33411..29ccd755cc2e 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -21,8 +21,9 @@ static const struct msm_dsi_config apq8064_dsi_cfg = { .num_regulators = ARRAY_SIZE(apq8064_dsi_regulators), .bus_clk_names = dsi_v2_bus_clk_names, .num_bus_clks = ARRAY_SIZE(dsi_v2_bus_clk_names), - .io_start = { 0x4700000, 0x5800000 }, - .num_dsi = 2, + .io_start = { + { 0x4700000, 0x5800000 }, + }, }; static const char * const dsi_6g_bus_clk_names[] = { @@ -41,46 +42,40 @@ static const struct msm_dsi_config msm8974_apq8084_dsi_cfg = { .num_regulators = ARRAY_SIZE(msm8974_apq8084_regulators), .bus_clk_names = dsi_6g_bus_clk_names, .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names), - .io_start = { 0xfd922800, 0xfd922b00 }, - .num_dsi = 2, + .io_start = { + { 0xfd922800, 0xfd922b00 }, + }, }; -static const char * const dsi_8916_bus_clk_names[] = { +static const char * const dsi_v1_3_1_clk_names[] = { "mdp_core", "iface", "bus", }; -static const struct regulator_bulk_data msm8916_dsi_regulators[] = { +static const struct regulator_bulk_data dsi_v1_3_1_regulators[] = { { .supply = "vdda", .init_load_uA = 100000 }, /* 1.2 V */ { .supply = "vddio", .init_load_uA = 100000 }, /* 1.8 V */ }; static const struct msm_dsi_config msm8916_dsi_cfg = { .io_offset = DSI_6G_REG_SHIFT, - .regulator_data = msm8916_dsi_regulators, - .num_regulators = ARRAY_SIZE(msm8916_dsi_regulators), - .bus_clk_names = dsi_8916_bus_clk_names, - .num_bus_clks = ARRAY_SIZE(dsi_8916_bus_clk_names), - .io_start = { 0x1a98000 }, - .num_dsi = 1, -}; - -static const char * const dsi_8976_bus_clk_names[] = { - "mdp_core", "iface", "bus", -}; - -static const struct regulator_bulk_data msm8976_dsi_regulators[] = { - { .supply = "vdda", .init_load_uA = 100000 }, /* 1.2 V */ - { .supply = "vddio", .init_load_uA = 100000 }, /* 1.8 V */ + .regulator_data = dsi_v1_3_1_regulators, + .num_regulators = ARRAY_SIZE(dsi_v1_3_1_regulators), + .bus_clk_names = dsi_v1_3_1_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_v1_3_1_clk_names), + .io_start = { + { 0x1a98000 }, + }, }; static const struct msm_dsi_config msm8976_dsi_cfg = { .io_offset = DSI_6G_REG_SHIFT, - .regulator_data = msm8976_dsi_regulators, - .num_regulators = ARRAY_SIZE(msm8976_dsi_regulators), - .bus_clk_names = dsi_8976_bus_clk_names, - .num_bus_clks = ARRAY_SIZE(dsi_8976_bus_clk_names), - .io_start = { 0x1a94000, 0x1a96000 }, - .num_dsi = 2, + .regulator_data = dsi_v1_3_1_regulators, + .num_regulators = ARRAY_SIZE(dsi_v1_3_1_regulators), + .bus_clk_names = dsi_v1_3_1_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_v1_3_1_clk_names), + .io_start = { + { 0x1a94000, 0x1a96000 }, + }, }; static const struct regulator_bulk_data msm8994_dsi_regulators[] = { @@ -98,12 +93,9 @@ static const struct msm_dsi_config msm8994_dsi_cfg = { .num_regulators = ARRAY_SIZE(msm8994_dsi_regulators), .bus_clk_names = dsi_6g_bus_clk_names, .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names), - .io_start = { 0xfd998000, 0xfd9a0000 }, - .num_dsi = 2, -}; - -static const char * const dsi_8996_bus_clk_names[] = { - "mdp_core", "iface", "bus", "core_mmss", + .io_start = { + { 0xfd998000, 0xfd9a0000 }, + }, }; static const struct regulator_bulk_data msm8996_dsi_regulators[] = { @@ -116,10 +108,11 @@ static const struct msm_dsi_config msm8996_dsi_cfg = { .io_offset = DSI_6G_REG_SHIFT, .regulator_data = msm8996_dsi_regulators, .num_regulators = ARRAY_SIZE(msm8996_dsi_regulators), - .bus_clk_names = dsi_8996_bus_clk_names, - .num_bus_clks = ARRAY_SIZE(dsi_8996_bus_clk_names), - .io_start = { 0x994000, 0x996000 }, - .num_dsi = 2, + .bus_clk_names = dsi_6g_bus_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names), + .io_start = { + { 0x994000, 0x996000 }, + }, }; static const char * const dsi_msm8998_bus_clk_names[] = { @@ -137,8 +130,9 @@ static const struct msm_dsi_config msm8998_dsi_cfg = { .num_regulators = ARRAY_SIZE(msm8998_dsi_regulators), .bus_clk_names = dsi_msm8998_bus_clk_names, .num_bus_clks = ARRAY_SIZE(dsi_msm8998_bus_clk_names), - .io_start = { 0xc994000, 0xc996000 }, - .num_dsi = 2, + .io_start = { + { 0xc994000, 0xc996000 }, + }, }; static const char * const dsi_sdm660_bus_clk_names[] = { @@ -155,30 +149,29 @@ static const struct msm_dsi_config sdm660_dsi_cfg = { .num_regulators = ARRAY_SIZE(sdm660_dsi_regulators), .bus_clk_names = dsi_sdm660_bus_clk_names, .num_bus_clks = ARRAY_SIZE(dsi_sdm660_bus_clk_names), - .io_start = { 0xc994000, 0xc996000 }, - .num_dsi = 2, + .io_start = { + { 0xc994000, 0xc996000 }, + }, }; -static const char * const dsi_sdm845_bus_clk_names[] = { +static const char * const dsi_v2_4_clk_names[] = { "iface", "bus", }; -static const char * const dsi_sc7180_bus_clk_names[] = { - "iface", "bus", -}; - -static const struct regulator_bulk_data sdm845_dsi_regulators[] = { +static const struct regulator_bulk_data dsi_v2_4_regulators[] = { { .supply = "vdda", .init_load_uA = 21800 }, /* 1.2 V */ }; static const struct msm_dsi_config sdm845_dsi_cfg = { .io_offset = DSI_6G_REG_SHIFT, - .regulator_data = sdm845_dsi_regulators, - .num_regulators = ARRAY_SIZE(sdm845_dsi_regulators), - .bus_clk_names = dsi_sdm845_bus_clk_names, - .num_bus_clks = ARRAY_SIZE(dsi_sdm845_bus_clk_names), - .io_start = { 0xae94000, 0xae96000 }, - .num_dsi = 2, + .regulator_data = dsi_v2_4_regulators, + .num_regulators = ARRAY_SIZE(dsi_v2_4_regulators), + .bus_clk_names = dsi_v2_4_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names), + .io_start = { + { 0xae94000, 0xae96000 }, /* SDM845 / SDM670 */ + { 0x5e94000 }, /* QCM2290 / SM6115 / SM6125 / SM6375 */ + }, }; static const struct regulator_bulk_data sm8550_dsi_regulators[] = { @@ -189,28 +182,11 @@ static const struct msm_dsi_config sm8550_dsi_cfg = { .io_offset = DSI_6G_REG_SHIFT, .regulator_data = sm8550_dsi_regulators, .num_regulators = ARRAY_SIZE(sm8550_dsi_regulators), - .bus_clk_names = dsi_sdm845_bus_clk_names, - .num_bus_clks = ARRAY_SIZE(dsi_sdm845_bus_clk_names), - .io_start = { 0xae94000, 0xae96000 }, - .num_dsi = 2, -}; - -static const struct regulator_bulk_data sc7180_dsi_regulators[] = { - { .supply = "vdda", .init_load_uA = 21800 }, /* 1.2 V */ -}; - -static const struct msm_dsi_config sc7180_dsi_cfg = { - .io_offset = DSI_6G_REG_SHIFT, - .regulator_data = sc7180_dsi_regulators, - .num_regulators = ARRAY_SIZE(sc7180_dsi_regulators), - .bus_clk_names = dsi_sc7180_bus_clk_names, - .num_bus_clks = ARRAY_SIZE(dsi_sc7180_bus_clk_names), - .io_start = { 0xae94000 }, - .num_dsi = 1, -}; - -static const char * const dsi_sc7280_bus_clk_names[] = { - "iface", "bus", + .bus_clk_names = dsi_v2_4_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names), + .io_start = { + { 0xae94000, 0xae96000 }, + }, }; static const struct regulator_bulk_data sc7280_dsi_regulators[] = { @@ -221,28 +197,11 @@ static const struct msm_dsi_config sc7280_dsi_cfg = { .io_offset = DSI_6G_REG_SHIFT, .regulator_data = sc7280_dsi_regulators, .num_regulators = ARRAY_SIZE(sc7280_dsi_regulators), - .bus_clk_names = dsi_sc7280_bus_clk_names, - .num_bus_clks = ARRAY_SIZE(dsi_sc7280_bus_clk_names), - .io_start = { 0xae94000, 0xae96000 }, - .num_dsi = 2, -}; - -static const char * const dsi_qcm2290_bus_clk_names[] = { - "iface", "bus", -}; - -static const struct regulator_bulk_data qcm2290_dsi_cfg_regulators[] = { - { .supply = "vdda", .init_load_uA = 21800 }, /* 1.2 V */ -}; - -static const struct msm_dsi_config qcm2290_dsi_cfg = { - .io_offset = DSI_6G_REG_SHIFT, - .regulator_data = qcm2290_dsi_cfg_regulators, - .num_regulators = ARRAY_SIZE(qcm2290_dsi_cfg_regulators), - .bus_clk_names = dsi_qcm2290_bus_clk_names, - .num_bus_clks = ARRAY_SIZE(dsi_qcm2290_bus_clk_names), - .io_start = { 0x5e94000 }, - .num_dsi = 1, + .bus_clk_names = dsi_v2_4_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names), + .io_start = { + { 0xae94000, 0xae96000 }, + }, }; static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = { @@ -311,7 +270,7 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_0, &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1, - &sc7180_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0, &sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0, @@ -335,9 +294,3 @@ const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) return cfg_hnd; } - -/* Non autodetect configs */ -const struct msm_dsi_cfg_handler qcm2290_dsi_cfg_handler = { - .cfg = &qcm2290_dsi_cfg, - .ops = &msm_dsi_6g_v2_host_ops, -}; diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h index 44be4a88aa83..91bdaf50bb1a 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -32,14 +32,16 @@ #define DSI_6G_REG_SHIFT 4 +/* Maximum number of configurations matched against the same hw revision */ +#define VARIANTS_MAX 2 + struct msm_dsi_config { u32 io_offset; const struct regulator_bulk_data *regulator_data; int num_regulators; const char * const *bus_clk_names; const int num_bus_clks; - const resource_size_t io_start[DSI_MAX]; - const int num_dsi; + const resource_size_t io_start[VARIANTS_MAX][DSI_MAX]; }; struct msm_dsi_host_cfg_ops { @@ -63,8 +65,5 @@ struct msm_dsi_cfg_handler { const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor); -/* Non autodetect configs */ -extern const struct msm_dsi_cfg_handler qcm2290_dsi_cfg_handler; - #endif /* __MSM_DSI_CFG_H__ */ diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 18fa30e1e858..961689a255c4 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -214,10 +214,6 @@ static const struct msm_dsi_cfg_handler *dsi_get_config( int ret; u32 major = 0, minor = 0; - cfg_hnd = device_get_match_data(dev); - if (cfg_hnd) - return cfg_hnd; - ahb_clk = msm_clk_get(msm_host->pdev, "iface"); if (IS_ERR(ahb_clk)) { pr_err("%s: cannot get interface clock\n", __func__); @@ -1862,16 +1858,16 @@ static int dsi_host_get_id(struct msm_dsi_host *msm_host) struct platform_device *pdev = msm_host->pdev; const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; struct resource *res; - int i; + int i, j; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); if (!res) return -EINVAL; - for (i = 0; i < cfg->num_dsi; i++) { - if (cfg->io_start[i] == res->start) - return i; - } + for (i = 0; i < VARIANTS_MAX; i++) + for (j = 0; j < DSI_MAX; j++) + if (cfg->io_start[i][j] == res->start) + return j; return -EINVAL; } diff --git a/drivers/iio/adc/qcom-spmi-adc5.c b/drivers/iio/adc/qcom-spmi-adc5.c index c2d5e06f137a..cab07076955c 100644 --- a/drivers/iio/adc/qcom-spmi-adc5.c +++ b/drivers/iio/adc/qcom-spmi-adc5.c @@ -775,6 +775,18 @@ static const struct adc5_data adc5_data_pmic = { 1, 2, 4, 8, 16, 32, 64, 128}, }; +const struct adc5_data adc5_data_pmic_lite = { + .full_scale_code_volt = 0x70e4, + .full_scale_code_cur = 0x1388, + .adc_chans = adc5_chans_pmic, + .info = &adc5_info, + .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX]) + {250, 420, 840}, + .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX]) + {15, 100, 200, 300, 400, 500, 600, 700, + 800, 900, 1, 2, 4, 6, 8, 10}, +}; + static const struct adc5_data adc7_data_pmic = { .full_scale_code_volt = 0x70e4, .adc_chans = adc7_chans_pmic, @@ -808,6 +820,10 @@ static const struct of_device_id adc5_match_table[] = { .data = &adc5_data_pmic, }, { + .compatible = "qcom,spmi-adc5-lite", + .data = &adc5_data_pmic_lite, + }, + { .compatible = "qcom,spmi-adc7", .data = &adc7_data_pmic, }, diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index ab988926433c..d70fe621e08e 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -57,4 +57,4 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8450) += qnoc-sm8450.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8550) += qnoc-sm8550.o -obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o +obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o ddr-go-brr.o diff --git a/drivers/interconnect/qcom/ddr-go-brr.c b/drivers/interconnect/qcom/ddr-go-brr.c new file mode 100644 index 000000000000..2996e1b7456f --- /dev/null +++ b/drivers/interconnect/qcom/ddr-go-brr.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm QCM2290 Network-on-Chip (NoC) QoS driver + * + * Copyright (c) 2021, Linaro Ltd. + * + */ + +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/interconnect-provider.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/slab.h> + +#include "icc-rpm.h" +#include "smd-rpm.h" + +#define APPS_MAS_ID 0 +#define EBI_SLV_ID 0 + +extern int qcom_icc_rpm_set(u64 m, u64 s, u64 bw); +static int ddrbrr_probe(struct platform_device *pdev) { + int ret; + + /* wait for the RPM proxy */ + if (!qcom_icc_rpm_smd_available()) + return -EPROBE_DEFER; + + ret = qcom_icc_rpm_set(APPS_MAS_ID, EBI_SLV_ID, ULONG_MAX); + if (!ret) + pr_err("ddr went brr successfully\n"); + + return ret; +}; + +static const struct of_device_id ddrbrr_of_match[] = { + { .compatible = "qcom,ddr-brr" }, + { } +}; +MODULE_DEVICE_TABLE(of, ddrbrr_of_match); + +static struct platform_driver ddrbrr = { + .probe = ddrbrr_probe, + .driver = { + .name = "ddr-brr", + .of_match_table = ddrbrr_of_match, + }, +}; +module_platform_driver(ddrbrr); +MODULE_LICENSE("GPL"); diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 4180a06681b2..9ba85d18d4df 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -203,7 +203,7 @@ static int qcom_icc_qos_set(struct icc_node *node, u64 sum_bw) } } -static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw) +int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw) { int ret = 0; @@ -233,6 +233,7 @@ static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw) return ret; } +EXPORT_SYMBOL_GPL(qcom_icc_rpm_set); static int __qcom_icc_set(struct icc_node *n, struct qcom_icc_node *qn, u64 sum_bw) |