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author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2023-04-01 13:54:52 +0200 |
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committer | Konrad Dybcio <konrad.dybcio@linaro.org> | 2023-04-26 11:21:58 +0000 |
commit | fd709579d3d8725a26943be4ee11486802d8665e (patch) | |
tree | bb24a7a588418b329bcc8876c4db4afde08b13c6 /drivers/gpu/drm/msm/msm_submitqueue.c | |
parent | 1d8ac0e2b7ea65e1373fb2603d953534b140d5f0 (diff) |
drm/msm/a6xx: Add A610 speedbin support
A610 is implemented on at least three SoCs: SM6115 (bengal), SM6125
(trinket) and SM6225 (khaje). Trinket does not support speed binning
(only a single SKU exists) and we don't yet support khaje upstream.
Hence, add a fuse mapping table for bengal to allow for per-chip
frequency limiting.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Diffstat (limited to 'drivers/gpu/drm/msm/msm_submitqueue.c')
0 files changed, 0 insertions, 0 deletions