diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2021-06-14 17:25:21 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2021-09-13 08:55:53 +0200 |
| commit | 7248f5784b8a67f61a622b63d9ad971434524058 (patch) | |
| tree | 6d1bb921e1dc94b650f10f8a560d7d8778de47cc /arch/arm64/boot/dts/xilinx | |
| parent | 69f8aec4f900dc8af6e38957beefcd3b763bfb5a (diff) | |
arm64: zynqmp: Wire DP and DPDMA for dc1/dc4
Enable Display Port and Display Port DMA for zc1751 dc1 and dc4.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/dbbd212bcc587e835d6df2f91622f5baa124bff5.1623684253.git.michal.simek@xilinx.com
Diffstat (limited to 'arch/arm64/boot/dts/xilinx')
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 8 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 10 |
2 files changed, 17 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index dd129347174a..460aba6e7990 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -391,3 +391,11 @@ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; maximum-speed = "super-speed"; }; + +&zynqmp_dpdma { + status = "okay"; +}; + +&zynqmp_dpsub { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 2366cd9f091a..8046f0df0f35 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP zc1751-xm018-dc4 * - * (C) Copyright 2015 - 2019, Xilinx, Inc. + * (C) Copyright 2015 - 2021, Xilinx, Inc. * * Michal Simek <michal.simek@xilinx.com> */ @@ -176,3 +176,11 @@ &watchdog0 { status = "okay"; }; + +&zynqmp_dpdma { + status = "okay"; +}; + +&zynqmp_dpsub { + status = "okay"; +}; |