diff options
| author | Suman Anna <s-anna@ti.com> | 2020-06-12 17:53:56 -0500 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2020-07-28 17:08:27 -0700 |
| commit | c6caf22eaa2347e75ef639ccfafd277ce466e1ca (patch) | |
| tree | e78137d788e13e2e93d37fbec7f8242d91fb93d8 /Documentation/devicetree/bindings/remoteproc | |
| parent | 21a4d7386e7e8b5f6fb97ced6af3b8181f2c9bd5 (diff) | |
dt-bindings: remoteproc: k3-dsp: Update bindings for C71x DSPs
Some Texas Instruments K3 family of SoCs have one of more newer
generation TMS320C71x CorePac processor subsystem in addition to
the existing TMS320C66x CorePac processor subsystems. Update the
device tree bindings document for the C71x DSP devices.
The example is also updated to show the single C71 DSP present
on J721E SoCs.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Suman Anna <s-anna@ti.com>
Link: https://lore.kernel.org/r/20200612225357.8251-2-s-anna@ti.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/remoteproc')
| -rw-r--r-- | Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml | 68 |
1 files changed, 55 insertions, 13 deletions
diff --git a/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml index a7834bc1530f..24b0c50fa436 100644 --- a/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml @@ -30,21 +30,12 @@ allOf: properties: compatible: - const: ti,j721e-c66-dsp + enum: + - ti,j721e-c66-dsp + - ti,j721e-c71-dsp description: Use "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs - - reg: - items: - - description: Address and Size of the L2 SRAM internal memory region - - description: Address and Size of the L1 PRAM internal memory region - - description: Address and Size of the L1 DRAM internal memory region - - reg-names: - items: - - const: l2sram - - const: l1pram - - const: l1dram + Use "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs resets: description: | @@ -92,6 +83,40 @@ properties: should be defined as per the generic bindings in, Documentation/devicetree/bindings/sram/sram.yaml +if: + properties: + compatible: + enum: + - ti,j721e-c66-dsp +then: + properties: + reg: + items: + - description: Address and Size of the L2 SRAM internal memory region + - description: Address and Size of the L1 PRAM internal memory region + - description: Address and Size of the L1 DRAM internal memory region + reg-names: + items: + - const: l2sram + - const: l1pram + - const: l1dram +else: + if: + properties: + compatible: + enum: + - ti,j721e-c71-dsp + then: + properties: + reg: + items: + - description: Address and Size of the L2 SRAM internal memory region + - description: Address and Size of the L1 DRAM internal memory region + reg-names: + items: + - const: l2sram + - const: l1dram + required: - compatible - reg @@ -119,6 +144,7 @@ examples: #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ + <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */ <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */ <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */ @@ -138,5 +164,21 @@ examples: <&c66_0_memory_region>; mboxes = <&mailbox0_cluster3 &mbox_c66_0>; }; + + /* J721E C71_0 DSP node */ + c71_0: dsp@64800000 { + compatible = "ti,j721e-c71-dsp"; + reg = <0x00 0x64800000 0x00 0x00080000>, + <0x00 0x64e00000 0x00 0x0000c000>; + reg-names = "l2sram", "l1dram"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <15>; + ti,sci-proc-ids = <0x30 0xFF>; + resets = <&k3_reset 15 1>; + firmware-name = "j7-c71_0-fw"; + memory-region = <&c71_0_dma_memory_region>, + <&c71_0_memory_region>; + mboxes = <&mailbox0_cluster4 &mbox_c71_0>; + }; }; }; |