diff options
| author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2023-04-01 13:54:44 +0200 |
|---|---|---|
| committer | Konrad Dybcio <konrad.dybcio@linaro.org> | 2023-04-26 11:21:57 +0000 |
| commit | 98bb17991ad304320fbddbb2c7c1322e69357c4b (patch) | |
| tree | 760416deae89ee35c00d88ebcc903f207236a98b | |
| parent | 73ef38b09a55779539fdc15c674b8b9abeadc6c5 (diff) | |
drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init
Currently we're only deasserting REG_A6XX_RBBM_GBIF_HALT, but we also
need REG_A6XX_GBIF_HALT to be set to 0. For GMU-equipped GPUs this is
done in a6xx_bus_clear_pending_transactions(), but for the GMU-less
ones we have to do it *somewhere*. Unhalting both side by side sounds
like a good plan and it won't cause any issues if it's unnecessary.
Also, add a memory barrier to ensure it's gone through.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 857d726592ee..025f66196573 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1031,8 +1031,12 @@ static int hw_init(struct msm_gpu *gpu) } /* Clear GBIF halt in case GX domain was not collapsed */ - if (a6xx_has_gbif(adreno_gpu)) + if (a6xx_has_gbif(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_GBIF_HALT, 0); gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0); + /* Let's make extra sure that the GPU can access the memory.. */ + mb(); + } gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); |