diff options
| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2021-03-10 16:30:31 +0530 |
|---|---|---|
| committer | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2021-09-15 12:23:57 +0530 |
| commit | cdabdd478b92f0340803c9ebf666e385c3397cfd (patch) | |
| tree | eaf287c3c7b88ec77af92aab0370a041aba33966 | |
| parent | 6880fa6c56601bb8ed59df6c30fd390cc5f6dd8f (diff) | |
ARM: dts: qcom: sdx55: Add support for PCIe PHY
Add devicetree support for PCIe PHY used in SDX55 platform. This PHY is
used by the PCIe EP controller.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom-sdx55.dtsi | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 1e6ce035f76a..3aac8afed6e2 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -310,6 +310,41 @@ status = "disabled"; }; + pcie0_phy: phy@1c07000 { + compatible = "qcom,sdx55-qmp-pcie-phy"; + reg = <0x01c07000 0x1c4>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: lanes@1c06000 { + reg = <0x01c06000 0x104>, /* tx0 */ + <0x01c06200 0x328>, /* rx0 */ + <0x01c07200 0x1e8>, /* pcs */ + <0x01c06800 0x104>, /* tx1 */ + <0x01c06a00 0x328>, /* rx1 */ + <0x01c07600 0x800>; /* pcs_misc */ + clocks = <&gcc GCC_PCIE_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + clock-output-names = "pcie_pipe_clk"; + }; + }; + ipa: ipa@1e40000 { compatible = "qcom,sdx55-ipa"; |