From 71f66a632705bbc18c2c239a2453048e71f6ac0e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 6 Mar 2023 20:02:00 +0300 Subject: New rr-cache entries from ci-merge Signed-off-by: Dmitry Baryshkov --- .../5fcf3c095544425b03a927fd2e82476b9b70010c/preimage | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 rr-cache/5fcf3c095544425b03a927fd2e82476b9b70010c/preimage (limited to 'rr-cache/5fcf3c095544425b03a927fd2e82476b9b70010c/preimage') diff --git a/rr-cache/5fcf3c095544425b03a927fd2e82476b9b70010c/preimage b/rr-cache/5fcf3c095544425b03a927fd2e82476b9b70010c/preimage new file mode 100644 index 0000000..6394582 --- /dev/null +++ b/rr-cache/5fcf3c095544425b03a927fd2e82476b9b70010c/preimage @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +<<<<<<< + * Copyright (c) 2022, The Linux Foundation. All rights reserved. +======= + * Copyright (c) 2023, Linaro Limited +>>>>>>> + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V6_H_ + +/* Only for QMP V6 PHY - PCIE have different offsets than V5 */ +#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c +#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14 +#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 +#define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 + +#endif -- cgit v1.2.3