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-rw-r--r-- | rr-cache/815afa572fa45db64c322d7528fe70123fb7e0cd/thisimage.2 | 3309 |
1 files changed, 0 insertions, 3309 deletions
diff --git a/rr-cache/815afa572fa45db64c322d7528fe70123fb7e0cd/thisimage.2 b/rr-cache/815afa572fa45db64c322d7528fe70123fb7e0cd/thisimage.2 deleted file mode 100644 index ab009fe..0000000 --- a/rr-cache/815afa572fa45db64c322d7528fe70123fb7e0cd/thisimage.2 +++ /dev/null @@ -1,3309 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) 2021, Linaro Limited - */ - -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/clock/qcom,gcc-sm8450.h> -#include <dt-bindings/clock/qcom,rpmh.h> -#include <dt-bindings/clock/qcom,sm8450-camcc.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/mailbox/qcom-ipcc.h> -#include <dt-bindings/power/qcom-rpmpd.h> -#include <dt-bindings/interconnect/qcom,sm8450.h> -#include <dt-bindings/soc/qcom,rpmh-rsc.h> -#include <dt-bindings/thermal/thermal.h> - -/ { - interrupt-parent = <&intc>; - - #address-cells = <2>; - #size-cells = <2>; - - chosen { }; - - clocks { - xo_board: xo-board { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <76800000>; - }; - - sleep_clk: sleep-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32000>; - }; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - CPU0: cpu@0 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x0>; - enable-method = "psci"; - next-level-cache = <&L2_0>; - power-domains = <&CPU_PD0>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_0: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - L3_0: l3-cache { - compatible = "cache"; - }; - }; - }; - - CPU1: cpu@100 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x100>; - enable-method = "psci"; - next-level-cache = <&L2_100>; - power-domains = <&CPU_PD1>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_100: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU2: cpu@200 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x200>; - enable-method = "psci"; - next-level-cache = <&L2_200>; - power-domains = <&CPU_PD2>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_200: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU3: cpu@300 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x300>; - enable-method = "psci"; - next-level-cache = <&L2_300>; - power-domains = <&CPU_PD3>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 0>; - #cooling-cells = <2>; - L2_300: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU4: cpu@400 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x400>; - enable-method = "psci"; - next-level-cache = <&L2_400>; - power-domains = <&CPU_PD4>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_400: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU5: cpu@500 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x500>; - enable-method = "psci"; - next-level-cache = <&L2_500>; - power-domains = <&CPU_PD5>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_500: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - - }; - - CPU6: cpu@600 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x600>; - enable-method = "psci"; - next-level-cache = <&L2_600>; - power-domains = <&CPU_PD6>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 1>; - #cooling-cells = <2>; - L2_600: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - CPU7: cpu@700 { - device_type = "cpu"; - compatible = "qcom,kryo780"; - reg = <0x0 0x700>; - enable-method = "psci"; - next-level-cache = <&L2_700>; - power-domains = <&CPU_PD7>; - power-domain-names = "psci"; - qcom,freq-domain = <&cpufreq_hw 2>; - #cooling-cells = <2>; - L2_700: l2-cache { - compatible = "cache"; - next-level-cache = <&L3_0>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&CPU0>; - }; - - core1 { - cpu = <&CPU1>; - }; - - core2 { - cpu = <&CPU2>; - }; - - core3 { - cpu = <&CPU3>; - }; - - core4 { - cpu = <&CPU4>; - }; - - core5 { - cpu = <&CPU5>; - }; - - core6 { - cpu = <&CPU6>; - }; - - core7 { - cpu = <&CPU7>; - }; - }; - }; - - idle-states { - entry-method = "psci"; - - LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { - compatible = "arm,idle-state"; - idle-state-name = "silver-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <800>; - exit-latency-us = <750>; - min-residency-us = <4090>; - local-timer-stop; - }; - - BIG_CPU_SLEEP_0: cpu-sleep-1-0 { - compatible = "arm,idle-state"; - idle-state-name = "gold-rail-power-collapse"; - arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <600>; - exit-latency-us = <1550>; - min-residency-us = <4791>; - local-timer-stop; - }; - }; - - domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "domain-idle-state"; - idle-state-name = "cluster-l3-off"; - arm,psci-suspend-param = <0x41000044>; - entry-latency-us = <1050>; - exit-latency-us = <2500>; - min-residency-us = <5309>; - local-timer-stop; - }; - - CLUSTER_SLEEP_1: cluster-sleep-1 { - compatible = "domain-idle-state"; - idle-state-name = "cluster-power-collapse"; - arm,psci-suspend-param = <0x4100c344>; - entry-latency-us = <2700>; - exit-latency-us = <3500>; - min-residency-us = <13959>; - local-timer-stop; - }; - }; - }; - - firmware { - scm: scm { - compatible = "qcom,scm-sm8450", "qcom,scm"; - #reset-cells = <1>; - }; - }; - - clk_virt: interconnect@0 { - compatible = "qcom,sm8450-clk-virt"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - mc_virt: interconnect@1 { - compatible = "qcom,sm8450-mc-virt"; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - memory@a0000000 { - device_type = "memory"; - /* We expect the bootloader to fill in the size */ - reg = <0x0 0xa0000000 0x0 0x0>; - }; - - pmu { - compatible = "arm,armv8-pmuv3"; - interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - - CPU_PD0: cpu0 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD1: cpu1 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD2: cpu2 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD3: cpu3 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&LITTLE_CPU_SLEEP_0>; - }; - - CPU_PD4: cpu4 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD5: cpu5 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD6: cpu6 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CPU_PD7: cpu7 { - #power-domain-cells = <0>; - power-domains = <&CLUSTER_PD>; - domain-idle-states = <&BIG_CPU_SLEEP_0>; - }; - - CLUSTER_PD: cpu-cluster0 { - #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; - }; - }; - - reserved_memory: reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hyp_mem: memory@80000000 { - reg = <0x0 0x80000000 0x0 0x600000>; - no-map; - }; - - xbl_dt_log_mem: memory@80600000 { - reg = <0x0 0x80600000 0x0 0x40000>; - no-map; - }; - - xbl_ramdump_mem: memory@80640000 { - reg = <0x0 0x80640000 0x0 0x180000>; - no-map; - }; - - xbl_sc_mem: memory@807c0000 { - reg = <0x0 0x807c0000 0x0 0x40000>; - no-map; - }; - - aop_image_mem: memory@80800000 { - reg = <0x0 0x80800000 0x0 0x60000>; - no-map; - }; - - aop_cmd_db_mem: memory@80860000 { - compatible = "qcom,cmd-db"; - reg = <0x0 0x80860000 0x0 0x20000>; - no-map; - }; - - aop_config_mem: memory@80880000 { - reg = <0x0 0x80880000 0x0 0x20000>; - no-map; - }; - - tme_crash_dump_mem: memory@808a0000 { - reg = <0x0 0x808a0000 0x0 0x40000>; - no-map; - }; - - tme_log_mem: memory@808e0000 { - reg = <0x0 0x808e0000 0x0 0x4000>; - no-map; - }; - - uefi_log_mem: memory@808e4000 { - reg = <0x0 0x808e4000 0x0 0x10000>; - no-map; - }; - - /* secdata region can be reused by apps */ - smem: memory@80900000 { - compatible = "qcom,smem"; - reg = <0x0 0x80900000 0x0 0x200000>; - hwlocks = <&tcsr_mutex 3>; - no-map; - }; - - cpucp_fw_mem: memory@80b00000 { - reg = <0x0 0x80b00000 0x0 0x100000>; - no-map; - }; - - cdsp_secure_heap: memory@80c00000 { - reg = <0x0 0x80c00000 0x0 0x4600000>; - no-map; - }; - - camera_mem: memory@85200000 { - reg = <0x0 0x85200000 0x0 0x500000>; - no-map; - }; - - video_mem: memory@85700000 { - reg = <0x0 0x85700000 0x0 0x700000>; - no-map; - }; - - adsp_mem: memory@85e00000 { - reg = <0x0 0x85e00000 0x0 0x2100000>; - no-map; - }; - - slpi_mem: memory@88000000 { - reg = <0x0 0x88000000 0x0 0x1900000>; - no-map; - }; - - cdsp_mem: memory@89900000 { - reg = <0x0 0x89900000 0x0 0x2000000>; - no-map; - }; - - ipa_fw_mem: memory@8b900000 { - reg = <0x0 0x8b900000 0x0 0x10000>; - no-map; - }; - - ipa_gsi_mem: memory@8b910000 { - reg = <0x0 0x8b910000 0x0 0xa000>; - no-map; - }; - - gpu_micro_code_mem: memory@8b91a000 { - reg = <0x0 0x8b91a000 0x0 0x2000>; - no-map; - }; - - spss_region_mem: memory@8ba00000 { - reg = <0x0 0x8ba00000 0x0 0x180000>; - no-map; - }; - - /* First part of the "SPU secure shared memory" region */ - spu_tz_shared_mem: memory@8bb80000 { - reg = <0x0 0x8bb80000 0x0 0x60000>; - no-map; - }; - - /* Second part of the "SPU secure shared memory" region */ - spu_modem_shared_mem: memory@8bbe0000 { - reg = <0x0 0x8bbe0000 0x0 0x20000>; - no-map; - }; - - mpss_mem: memory@8bc00000 { - reg = <0x0 0x8bc00000 0x0 0x13200000>; - no-map; - }; - - cvp_mem: memory@9ee00000 { - reg = <0x0 0x9ee00000 0x0 0x700000>; - no-map; - }; - - rmtfs_mem: memory@9fd00000 { - compatible = "qcom,rmtfs-mem"; - reg = <0x0 0x9fd00000 0x0 0x280000>; - no-map; - - qcom,client-id = <1>; - qcom,vmid = <15>; - }; - - global_sync_mem: memory@a6f00000 { - reg = <0x0 0xa6f00000 0x0 0x100000>; - no-map; - }; - - /* uefi region can be reused by APPS */ - - /* Linux kernel image is loaded at 0xa0000000 */ - - oem_vm_mem: memory@bb000000 { - reg = <0x0 0xbb000000 0x0 0x5000000>; - no-map; - }; - - mte_mem: memory@c0000000 { - reg = <0x0 0xc0000000 0x0 0x20000000>; - no-map; - }; - - qheebsp_reserved_mem: memory@e0000000 { - reg = <0x0 0xe0000000 0x0 0x600000>; - no-map; - }; - - cpusys_vm_mem: memory@e0600000 { - reg = <0x0 0xe0600000 0x0 0x400000>; - no-map; - }; - - hyp_reserved_mem: memory@e0a00000 { - reg = <0x0 0xe0a00000 0x0 0x100000>; - no-map; - }; - - trust_ui_vm_mem: memory@e0b00000 { - reg = <0x0 0xe0b00000 0x0 0x4af3000>; - no-map; - }; - - trust_ui_vm_qrtr: memory@e55f3000 { - reg = <0x0 0xe55f3000 0x0 0x9000>; - no-map; - }; - - trust_ui_vm_vblk0_ring: memory@e55fc000 { - reg = <0x0 0xe55fc000 0x0 0x4000>; - no-map; - }; - - trust_ui_vm_swiotlb: memory@e5600000 { - reg = <0x0 0xe5600000 0x0 0x100000>; - no-map; - }; - - tz_stat_mem: memory@e8800000 { - reg = <0x0 0xe8800000 0x0 0x100000>; - no-map; - }; - - tags_mem: memory@e8900000 { - reg = <0x0 0xe8900000 0x0 0x1200000>; - no-map; - }; - - qtee_mem: memory@e9b00000 { - reg = <0x0 0xe9b00000 0x0 0x500000>; - no-map; - }; - - trusted_apps_mem: memory@ea000000 { - reg = <0x0 0xea000000 0x0 0x3900000>; - no-map; - }; - - trusted_apps_ext_mem: memory@ed900000 { - reg = <0x0 0xed900000 0x0 0x3b00000>; - no-map; - }; - }; - - smp2p-adsp { - compatible = "qcom,smp2p"; - qcom,smem = <443>, <429>; - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <2>; - - smp2p_adsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_adsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-cdsp { - compatible = "qcom,smp2p"; - qcom,smem = <94>, <432>; - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - smp2p_cdsp_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_cdsp_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-modem { - compatible = "qcom,smp2p"; - qcom,smem = <435>, <428>; - interrupts-extended = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <1>; - - smp2p_modem_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_modem_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - - ipa_smp2p_out: ipa-ap-to-modem { - qcom,entry-name = "ipa"; - #qcom,smem-state-cells = <1>; - }; - - ipa_smp2p_in: ipa-modem-to-ap { - qcom,entry-name = "ipa"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - smp2p-slpi { - compatible = "qcom,smp2p"; - qcom,smem = <481>, <430>; - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_SMP2P>; - - qcom,local-pid = <0>; - qcom,remote-pid = <3>; - - smp2p_slpi_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; - - smp2p_slpi_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - interrupt-controller; - #interrupt-cells = <2>; - }; - }; - - soc: soc@0 { - #address-cells = <2>; - #size-cells = <2>; - ranges = <0 0 0 0 0x10 0>; - dma-ranges = <0 0 0 0 0x10 0>; - compatible = "simple-bus"; - - gcc: clock-controller@100000 { - compatible = "qcom,gcc-sm8450"; - reg = <0x0 0x00100000 0x0 0x1f4200>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&pcie0_lane>, - <&pcie1_lane>, - <&sleep_clk>; - clock-names = "bi_tcxo", - "pcie_0_pipe_clk", - "pcie_1_pipe_clk", - "sleep_clk"; - }; - - qupv3_id_2: geniqup@8c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x008c0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - uart20: serial@894000 { - compatible = "qcom,geni-uart"; - reg = <0 0x00894000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart20_default>; - interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - qupv3_id_0: geniqup@9c0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x009c0000 0x0 0x2000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c6: i2c@998000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00998000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c6_data_clk>; - interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - uart7: serial@99c000 { - compatible = "qcom,geni-debug-uart"; - reg = <0 0x0099c000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; - interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - qupv3_id_1: geniqup@ac0000 { - compatible = "qcom,geni-se-qup"; - reg = <0x0 0x00ac0000 0x0 0x6000>; - clock-names = "m-ahb", "s-ahb"; - clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, - <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - i2c13: i2c@a94000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a94000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c13_data_clk>; - interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c14: i2c@a98000 { - compatible = "qcom,geni-i2c"; - reg = <0 0x00a98000 0 0x4000>; - clock-names = "se"; - clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c14_data_clk>; - interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; - - pcie0: pci@1c00000 { - compatible = "qcom,pcie-sm8450-pcie0"; - reg = <0 0x01c00000 0 0x3000>, - <0 0x60000000 0 0xf1d>, - <0 0x60000f20 0 0xa8>, - <0 0x60001000 0 0x1000>, - <0 0x60100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; - device_type = "pci"; - linux,pci-domain = <0>; - bus-range = <0x00 0xff>; - num-lanes = <1>; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, - <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; - - interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "msi8"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, - <&pcie0_lane>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_AXI_CLK>, - <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, - <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; - clock-names = "pipe", - "pipe_mux", - "phy_pipe", - "ref", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "ddrss_sf_tbu", - "aggre0", - "aggre1"; - - iommus = <&apps_smmu 0x1c00 0x7f>; - iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, - <0x100 &apps_smmu 0x1c01 0x1>; - - resets = <&gcc GCC_PCIE_0_BCR>; - reset-names = "pci"; - - power-domains = <&gcc PCIE_0_GDSC>; - power-domain-names = "gdsc"; - - phys = <&pcie0_lane>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_default_state>; - - interconnects = <&pcie_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "pci"; - - status = "disabled"; - }; - - pcie0_phy: phy@1c06000 { - compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; - reg = <0 0x01c06000 0 0x200>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, - <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_0_CLKREF_EN>, - <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; - - resets = <&gcc GCC_PCIE_0_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - - pcie0_lane: lanes@1c06200 { - reg = <0 0x1c06e00 0 0x200>, /* tx */ - <0 0x1c07000 0 0x200>, /* rx */ - <0 0x1c06200 0 0x200>, /* pcs */ - <0 0x1c06600 0 0x200>; /* pcs_pcie */ - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - #phy-cells = <0>; - clock-output-names = "pcie_0_pipe_clk"; - }; - }; - - pcie1: pci@1c08000 { - compatible = "qcom,pcie-sm8450-pcie1"; - reg = <0 0x01c08000 0 0x3000>, - <0 0x40000000 0 0xf1d>, - <0 0x40000f20 0 0xa8>, - <0 0x40001000 0 0x1000>, - <0 0x40100000 0 0x100000>; - reg-names = "parf", "dbi", "elbi", "atu", "config"; - device_type = "pci"; - linux,pci-domain = <1>; - bus-range = <0x00 0xff>; - num-lanes = <2>; - - #address-cells = <3>; - #size-cells = <2>; - - ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, - <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; - - interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi"; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ - - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, - <&pcie1_lane>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_PCIE_1_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_AXI_CLK>, - <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, - <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; - clock-names = "pipe", - "pipe_mux", - "phy_pipe", - "ref", - "aux", - "cfg", - "bus_master", - "bus_slave", - "slave_q2a", - "ddrss_sf_tbu", - "aggre1"; - - iommus = <&apps_smmu 0x1c80 0x7f>; - iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, - <0x100 &apps_smmu 0x1c81 0x1>; - - resets = <&gcc GCC_PCIE_1_BCR>; - reset-names = "pci"; - - power-domains = <&gcc PCIE_1_GDSC>; - power-domain-names = "gdsc"; - - phys = <&pcie1_lane>; - phy-names = "pciephy"; - - perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>; - enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; - - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_default_state>; - - interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "pci"; - - status = "disabled"; - }; - - pcie1_phy: phy@1c0f000 { - compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; - reg = <0 0x01c0f000 0 0x200>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_1_CLKREF_EN>, - <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; - - resets = <&gcc GCC_PCIE_1_PHY_BCR>; - reset-names = "phy"; - - assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - status = "disabled"; - - pcie1_lane: lanes@1c0e000 { - reg = <0 0x1c0e000 0 0x200>, /* tx */ - <0 0x1c0e200 0 0x300>, /* rx */ - <0 0x1c0f200 0 0x200>, /* pcs */ - <0 0x1c0e800 0 0x200>, /* tx */ - <0 0x1c0ea00 0 0x300>, /* rx */ - <0 0x1c0f400 0 0xc00>; /* pcs_pcie */ - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - #phy-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - }; - }; - - config_noc: interconnect@1500000 { - compatible = "qcom,sm8450-config-noc"; - reg = <0 0x01500000 0 0x1c000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system_noc: interconnect@1680000 { - compatible = "qcom,sm8450-system-noc"; - reg = <0 0x01680000 0 0x1e200>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - pcie_noc: interconnect@16c0000 { - compatible = "qcom,sm8450-pcie-anoc"; - reg = <0 0x016c0000 0 0xe280>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre1_noc: interconnect@16e0000 { - compatible = "qcom,sm8450-aggre1-noc"; - reg = <0 0x016e0000 0 0x1c080>; - #interconnect-cells = <2>; - clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - aggre2_noc: interconnect@1700000 { - compatible = "qcom,sm8450-aggre2-noc"; - reg = <0 0x01700000 0 0x31080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&rpmhcc RPMH_IPA_CLK>; - }; - - mmss_noc: interconnect@1740000 { - compatible = "qcom,sm8450-mmss-noc"; - reg = <0 0x01740000 0 0x1f080>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex"; - reg = <0x0 0x01f40000 0x0 0x40000>; - #hwlock-cells = <1>; - }; - - usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sm8450-usb-hs-phy", - "qcom,usb-snps-hs-7nm-phy"; - reg = <0 0x088e3000 0 0x400>; - status = "disabled"; - #phy-cells = <0>; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref"; - - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; - }; - - usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sm8450-qmp-usb3-phy"; - reg = <0 0x088e9000 0 0x200>, - <0 0x088e8000 0 0x20>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; - clock-names = "aux", "ref_clk_src", "com_aux"; - - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, - <&gcc GCC_USB3_PHY_PRIM_BCR>; - reset-names = "phy", "common"; - - usb_1_ssphy: phy@88e9200 { - reg = <0 0x088e9200 0 0x200>, - <0 0x088e9400 0 0x200>, - <0 0x088e9c00 0 0x400>, - <0 0x088e9600 0 0x200>, - <0 0x088e9800 0 0x200>, - <0 0x088e9a00 0 0x100>; - #phy-cells = <0>; - #clock-cells = <1>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; - }; - }; - - remoteproc_slpi: remoteproc@2400000 { - compatible = "qcom,sm8450-slpi-pas"; - reg = <0 0x02400000 0 0x4000>; - - interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8450_LCX>, - <&rpmhpd SM8450_LMX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&slpi_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_slpi_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_SLPI - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "slpi"; - qcom,remote-pid = <3>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "sdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x0541 0x0>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x0542 0x0>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x0543 0x0>; - /* note: shared-cb = <4> in downstream */ - }; - }; - }; - }; - - remoteproc_adsp: remoteproc@30000000 { - compatible = "qcom,sm8450-adsp-pas"; - reg = <0 0x030000000 0 0x100>; - - interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8450_LCX>, - <&rpmhpd SM8450_LMX>; - power-domain-names = "lcx", "lmx"; - - memory-region = <&adsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_adsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - remoteproc_adsp_glink: glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "lpass"; - qcom,remote-pid = <2>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "adsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x1803 0x0>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x1804 0x0>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x1805 0x0>; - }; - }; - }; - }; - - remoteproc_cdsp: remoteproc@32300000 { - compatible = "qcom,sm8450-cdsp-pas"; - reg = <0 0x032300000 0 0x1400000>; - - interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", - "handover", "stop-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd SM8450_CX>, - <&rpmhpd SM8450_MXC>; - power-domain-names = "cx", "mxc"; - - memory-region = <&cdsp_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_cdsp_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_CDSP - IPCC_MPROC_SIGNAL_GLINK_QMP>; - - label = "cdsp"; - qcom,remote-pid = <5>; - - fastrpc { - compatible = "qcom,fastrpc"; - qcom,glink-channels = "fastrpcglink-apps-dsp"; - label = "cdsp"; - #address-cells = <1>; - #size-cells = <0>; - - compute-cb@1 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <1>; - iommus = <&apps_smmu 0x2161 0x0400>, - <&apps_smmu 0x1021 0x1420>; - }; - - compute-cb@2 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <2>; - iommus = <&apps_smmu 0x2162 0x0400>, - <&apps_smmu 0x1022 0x1420>; - }; - - compute-cb@3 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <3>; - iommus = <&apps_smmu 0x2163 0x0400>, - <&apps_smmu 0x1023 0x1420>; - }; - - compute-cb@4 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <4>; - iommus = <&apps_smmu 0x2164 0x0400>, - <&apps_smmu 0x1024 0x1420>; - }; - - compute-cb@5 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <5>; - iommus = <&apps_smmu 0x2165 0x0400>, - <&apps_smmu 0x1025 0x1420>; - }; - - compute-cb@6 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <6>; - iommus = <&apps_smmu 0x2166 0x0400>, - <&apps_smmu 0x1026 0x1420>; - }; - - compute-cb@7 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <7>; - iommus = <&apps_smmu 0x2167 0x0400>, - <&apps_smmu 0x1027 0x1420>; - }; - - compute-cb@8 { - compatible = "qcom,fastrpc-compute-cb"; - reg = <8>; - iommus = <&apps_smmu 0x2168 0x0400>, - <&apps_smmu 0x1028 0x1420>; - }; - - /* note: secure cb9 in downstream */ - }; - }; - }; - - remoteproc_mpss: remoteproc@4080000 { - compatible = "qcom,sm8450-mpss-pas"; - reg = <0x0 0x04080000 0x0 0x4040>; - - interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, - <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, - <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "wdog", "fatal", "ready", "handover", - "stop-ack", "shutdown-ack"; - - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; - - power-domains = <&rpmhpd 0>, - <&rpmhpd 12>; - power-domain-names = "cx", "mss"; - - memory-region = <&mpss_mem>; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&smp2p_modem_out 0>; - qcom,smem-state-names = "stop"; - - status = "disabled"; - - glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_MPSS - IPCC_MPROC_SIGNAL_GLINK_QMP>; - interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; - label = "modem"; - qcom,remote-pid = <1>; - }; - }; - - cci0: cci@ac15000 { - compatible = "qcom,sm8450-cci"; - reg = <0 0xac15000 0 0x1000>; - interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; - power-domains = <&camcc TITAN_TOP_GDSC>; - - clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, - <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&camcc CAM_CC_CPAS_AHB_CLK>, - <&camcc CAM_CC_CCI_0_CLK>, - <&camcc CAM_CC_CCI_0_CLK_SRC>; - clock-names = "camnoc_axi", - "slow_ahb_src", - "cpas_ahb", - "cci", - "cci_src"; - pinctrl-0 = <&cci0_default &cci1_default>; - pinctrl-1 = <&cci0_sleep &cci1_sleep>; - pinctrl-names = "default", "sleep"; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - cci0_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci0_i2c1: i2c-bus@1 { - reg = <1>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - cci1: cci@ac16000 { - compatible = "qcom,sm8450-cci"; - reg = <0 0xac16000 0 0x1000>; - interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; - power-domains = <&camcc TITAN_TOP_GDSC>; - - clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, - <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, - <&camcc CAM_CC_CPAS_AHB_CLK>, - <&camcc CAM_CC_CCI_1_CLK>, - <&camcc CAM_CC_CCI_1_CLK_SRC>; - clock-names = "camnoc_axi", - "slow_ahb_src", - "cpas_ahb", - "cci", - "cci_src"; - pinctrl-0 = <&cci2_default &cci2_default>; - pinctrl-1 = <&cci3_sleep &cci3_sleep>; - pinctrl-names = "default", "sleep"; - - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - - cci1_i2c0: i2c-bus@0 { - reg = <0>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - - cci1_i2c1: i2c-bus@1 { - reg = <1>; - clock-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - - camcc: clock-controller@ade0000 { - compatible = "qcom,sm8450-camcc"; - reg = <0 0x0ade0000 0 0x20000>; - status = "disabled"; - clocks = <&gcc GCC_CAMERA_AHB_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; - clock-names = "iface", - "bi_tcxo", - "bi_tcxo_ao", - "sleep_clk"; - power-domains = <&rpmhpd SM8450_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; - - pdc: interrupt-controller@b220000 { - compatible = "qcom,sm8450-pdc", "qcom,pdc"; - reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; - qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, - <94 609 31>, <125 63 1>, <126 716 12>; - #interrupt-cells = <2>; - interrupt-parent = <&intc>; - interrupt-controller; - }; - - tsens0: thermal-sensor@c263000 { - compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; - reg = <0 0x0c263000 0 0x1000>, /* TM */ - <0 0x0c222000 0 0x1000>; /* SROT */ - #qcom,sensors = <16>; - interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - tsens1: thermal-sensor@c265000 { - compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; - reg = <0 0x0c265000 0 0x1000>, /* TM */ - <0 0x0c223000 0 0x1000>; /* SROT */ - #qcom,sensors = <16>; - interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", "critical"; - #thermal-sensor-cells = <1>; - }; - - aoss_qmp: power-controller@c300000 { - compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; - reg = <0 0x0c300000 0 0x400>; - interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; - - #clock-cells = <0>; - }; - - spmi_bus: spmi@c42d000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0x0 0x0c400000 0x0 0x00003000>, - <0x0 0x0c500000 0x0 0x00400000>, - <0x0 0x0c440000 0x0 0x00080000>, - <0x0 0x0c4c0000 0x0 0x00010000>, - <0x0 0x0c42d000 0x0 0x00010000>; - reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; - interrupt-names = "periph_irq"; - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; - qcom,ee = <0>; - qcom,channel = <0>; - qcom,bus-id = <0>; - #address-cells = <2>; - #size-cells = <0>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - ipcc: mailbox@ed18000 { - compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; - reg = <0 0x0ed18000 0 0x1000>; - interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <3>; - #mbox-cells = <2>; - }; - - tlmm: pinctrl@f100000 { - compatible = "qcom,sm8450-tlmm"; - reg = <0 0x0f100000 0 0x300000>; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 211>; - wakeup-parent = <&pdc>; - -<<<<<<< - cam_sensor_mclk0_default: cam-sensor-mclk0-default-state { - pins = "gpio100"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk0_sleep: cam-sensor-mclk0-sleep-state { - pins = "gpio100"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk1_default: cam-sensor-mclk1-default-state { - pins = "gpio101"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk1_sleep: cam-sensor-mclk1-sleep-state { - pins = "gpio101"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk2_default: cam-sensor-mclk2-default-state { - pins = "gpio102"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk2_sleep: cam-sensor-mclk2-sleep-state { - pins = "gpio102"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk3_default: cam-sensor-mclk3-default-state { - pins = "gpio103"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk3_sleep: cam-sensor-mclk3-sleep-state { - pins = "gpio103"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk4_default: cam-sensor-mclk4-default-state { - pins = "gpio104"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk4_sleep: cam-sensor-mclk4-sleep-state { - pins = "gpio104"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk5_default: cam-sensor-mclk5-default-state { - pins = "gpio105"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk5_sleep: cam-sensor-mclk5-sleep-state { - pins = "gpio105"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cam_sensor_mclk6_default: cam-sensor-mclk6-default-state { - pins = "gpio106"; - function = "cam_mclk"; - drive-strength = <6>; - bias-disable; - }; - - cam_sensor_mclk6_sleep: cam-sensor-mclk6-sleep-state { - pins = "gpio106"; - function = "cam_mclk"; - drive-strength = <6>; - bias-pull-down; - }; - - cci0_default: cci0-default-state { - /* SDA, SCL */ - pins = "gpio110", "gpio111"; - function = "cci_i2c"; -======= - pcie0_default_state: pcie0-default-state { - perst { - pins = "gpio94"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq { - pins = "gpio95"; - function = "pcie0_clkreqn"; - drive-strength = <2>; - bias-pull-up; - }; - - wake { - pins = "gpio96"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - pcie1_default_state: pcie1-default-state { - perst { - pins = "gpio97"; - function = "gpio"; - drive-strength = <2>; - bias-pull-down; - }; - - clkreq { - pins = "gpio98"; - function = "pcie1_clkreqn"; - drive-strength = <2>; - bias-pull-up; - }; - - wake { - pins = "gpio99"; - function = "gpio"; - drive-strength = <2>; - bias-pull-up; - }; - }; - - qup_i2c6_data_clk: qup-i2c6-data-clk { - pins = "gpio20", "gpio21"; - function = "qup6"; ->>>>>>> - drive-strength = <2>; - bias-pull-up; - }; - -<<<<<<< -======= - cci0_sleep: cci0-sleep-state { - /* SDA, SCL */ - pins = "gpio110", "gpio111"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - - cci1_default: cci1-default-state { - /* SDA, SCL */ - pins = "gpio112", "gpio113"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; - }; - - cci1_sleep: cci1-sleep-state { - /* SDA, SCL */ - pins = "gpio112", "gpio113"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - - cci2_default: cci2-default-state { - /* SDA, SCL */ - pins = "gpio114", "gpio115"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; - }; - - cci2_sleep: cci2-sleep-state { - /* SDA, SCL */ - pins = "gpio114", "gpio115"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - - cci3_default: cci3-default-state { - /* SDA, SCL */ - pins = "gpio208", "gpio209"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-up; - }; - - cci3_sleep: cci3-sleep-state { - /* SDA, SCL */ - pins = "gpio208", "gpio209"; - function = "cci_i2c"; - drive-strength = <2>; - bias-pull-down; - }; - ->>>>>>> - qup_i2c13_data_clk: qup-i2c13-data-clk { - pins = "gpio48", "gpio49"; - function = "qup13"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_i2c14_data_clk: qup-i2c14-data-clk { - pins = "gpio52", "gpio53"; - function = "qup14"; - drive-strength = <2>; - bias-pull-up; - }; - - qup_uart7_rx: qup-uart7-rx { - pins = "gpio26"; - function = "qup7"; - drive-strength = <2>; - bias-disable; - }; - - qup_uart7_tx: qup-uart7-tx { - pins = "gpio27"; - function = "qup7"; - drive-strength = <2>; - bias-disable; - }; - - qup_uart20_default: qup-uart20-default { - mux { - pins = "gpio76", "gpio77", - "gpio78", "gpio79"; - function = "qup20"; - }; - }; - - }; - - apps_smmu: iommu@15000000 { - compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; - reg = <0 0x15000000 0 0x100000>; - #iommu-cells = <2>; - #global-interrupts = <1>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; - }; - - intc: interrupt-controller@17100000 { - compatible = "arm,gic-v3"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - #interrupt-cells = <3>; - interrupt-controller; - #redistributor-regions = <1>; - redistributor-stride = <0x0 0x40000>; - reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ - <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - - gic_its: msi-controller@17140000 { - compatible = "arm,gic-v3-its"; - msi-controller; - #msi-cells = <1>; - reg = <0x0 0x17140000 0x0 0x20000>; - }; - }; - - timer@17420000 { - compatible = "arm,armv7-timer-mem"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - reg = <0x0 0x17420000 0x0 0x1000>; - clock-frequency = <19200000>; - - frame@17421000 { - frame-number = <0>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17421000 0x0 0x1000>, - <0x0 0x17422000 0x0 0x1000>; - }; - - frame@17423000 { - frame-number = <1>; - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17423000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17425000 { - frame-number = <2>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17425000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17427000 { - frame-number = <3>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17427000 0x0 0x1000>; - status = "disabled"; - }; - - frame@17429000 { - frame-number = <4>; - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x17429000 0x0 0x1000>; - status = "disabled"; - }; - - frame@1742b000 { - frame-number = <5>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x1742b000 0x0 0x1000>; - status = "disabled"; - }; - - frame@1742d000 { - frame-number = <6>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x0 0x1742d000 0x0 0x1000>; - status = "disabled"; - }; - }; - - apps_rsc: rsc@17a00000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x0 0x17a00000 0x0 0x10000>, - <0x0 0x17a10000 0x0 0x10000>, - <0x0 0x17a20000 0x0 0x10000>, - <0x0 0x17a30000 0x0 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, - <WAKE_TCS 2>, <CONTROL_TCS 0>; - - apps_bcm_voter: bcm-voter { - compatible = "qcom,bcm-voter"; - }; - - rpmhcc: clock-controller { - compatible = "qcom,sm8450-rpmh-clk"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmhpd: power-controller { - compatible = "qcom,sm8450-rpmhpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmhpd_opp_table>; - - rpmhpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmhpd_opp_ret: opp1 { - opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; - }; - - rpmhpd_opp_min_svs: opp2 { - opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; - }; - - rpmhpd_opp_low_svs: opp3 { - opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; - }; - - rpmhpd_opp_svs: opp4 { - opp-level = <RPMH_REGULATOR_LEVEL_SVS>; - }; - - rpmhpd_opp_svs_l1: opp5 { - opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; - }; - - rpmhpd_opp_nom: opp6 { - opp-level = <RPMH_REGULATOR_LEVEL_NOM>; - }; - - rpmhpd_opp_nom_l1: opp7 { - opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; - }; - - rpmhpd_opp_nom_l2: opp8 { - opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; - }; - - rpmhpd_opp_turbo: opp9 { - opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; - }; - - rpmhpd_opp_turbo_l1: opp10 { - opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; - }; - }; - }; - }; - - cpufreq_hw: cpufreq@17d91000 { - compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; - reg = <0 0x17d91000 0 0x1000>, - <0 0x17d92000 0 0x1000>, - <0 0x17d93000 0 0x1000>; - reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; - clock-names = "xo", "alternate"; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; - #freq-domain-cells = <1>; - }; - - gem_noc: interconnect@19100000 { - compatible = "qcom,sm8450-gem-noc"; - reg = <0 0x19100000 0 0xbb800>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - system-cache-controller@19200000 { - compatible = "qcom,sm8450-llcc"; - reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; - }; - - ufs_mem_hc: ufshc@1d84000 { - compatible = "qcom,sm8450-ufshc", "qcom,ufshc", - "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>; - interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; - phys = <&ufs_mem_phy_lanes>; - phy-names = "ufsphy"; - lanes-per-direction = <2>; - #reset-cells = <1>; - resets = <&gcc GCC_UFS_PHY_BCR>; - reset-names = "rst"; - - power-domains = <&gcc UFS_PHY_GDSC>; - - iommus = <&apps_smmu 0xe0 0x0>; - - interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; - interconnect-names = "ufs-ddr", "cpu-ufs"; - clock-names = - "core_clk", - "bus_aggr_clk", - "iface_clk", - "core_clk_unipro", - "ref_clk", - "tx_lane0_sync_clk", - "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; - clocks = - <&gcc GCC_UFS_PHY_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, - <&gcc GCC_UFS_PHY_AHB_CLK>, - <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; - freq-table-hz = - <75000000 300000000>, - <0 0>, - <0 0>, - <75000000 300000000>, - <75000000 300000000>, - <0 0>, - <0 0>, - <0 0>; - status = "disabled"; - }; - - ufs_mem_phy: phy@1d87000 { - compatible = "qcom,sm8450-qmp-ufs-phy"; - reg = <0 0x01d87000 0 0xe10>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - clock-names = "ref", "ref_aux", "qref"; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, - <&gcc GCC_UFS_0_CLKREF_EN>; - - resets = <&ufs_mem_hc 0>; - reset-names = "ufsphy"; - status = "disabled"; - - ufs_mem_phy_lanes: lanes@1d87400 { - reg = <0 0x01d87400 0 0x108>, - <0 0x01d87600 0 0x1e0>, - <0 0x01d87c00 0 0x1dc>, - <0 0x01d87800 0 0x108>, - <0 0x01d87a00 0 0x1e0>; - #phy-cells = <0>; - #clock-cells = <0>; - }; - }; - - usb_1: usb@a6f8800 { - compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; - status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB3_0_CLKREF_EN>; - clock-names = "cfg_noc", "core", "iface", "mock_utmi", - "sleep", "xo"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; - - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 14 IRQ_TYPE_EDGE_BOTH>, - <&pdc 15 IRQ_TYPE_EDGE_BOTH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", - "dm_hs_phy_irq", "ss_phy_irq"; - - power-domains = <&gcc USB30_PRIM_GDSC>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - iommus = <&apps_smmu 0x0 0x0>; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; - phy-names = "usb2-phy", "usb3-phy"; - }; - }; - - nsp_noc: interconnect@320c0000 { - compatible = "qcom,sm8450-nsp-noc"; - reg = <0 0x320c0000 0 0x10000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - - lpass_ag_noc: interconnect@3c40000 { - compatible = "qcom,sm8450-lpass-ag-noc"; - reg = <0 0x3c40000 0 0x17200>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - }; - - thermal-zones { - aoss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 0>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 1>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 2>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 3>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpuss4-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 4>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu4-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 5>; - - trips { - cpu4_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu4-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 6>; - - trips { - cpu4_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu4_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu4_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 7>; - - trips { - cpu5_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu5-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 8>; - - trips { - cpu5_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu5_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu5_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 9>; - - trips { - cpu6_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_top_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_top_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu6-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 10>; - - trips { - cpu6_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu6_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu6_bottom_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_bottom_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-top-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 11>; - - trips { - cpu7_top_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_top_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_top_alert0>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_top_alert1>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-middle-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 12>; - - trips { - cpu7_middle_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_middle_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_middle_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_middle_alert0>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_middle_alert1>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu7-bottom-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens0 13>; - - trips { - cpu7_bottom_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu7_bottom_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu7_bottom_alert0>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_bottom_alert1>; - cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - gpu-top-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens0 14>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpu0_tj_cfg: tj_cfg { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - gpu-bottom-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens0 15>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - gpu1_tj_cfg: tj_cfg { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - aoss1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 0>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cpu0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 1>; - - trips { - cpu0_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu0_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 2>; - - trips { - cpu1_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu1_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 3>; - - trips { - cpu2_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu2_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 4>; - - trips { - cpu3_alert0: trip-point0 { - temperature = <90000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_alert1: trip-point1 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu3_crit: cpu_crit { - temperature = <110000>; - hysteresis = <1000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cdsp0-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 5>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - cdsp_0_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cdsp1-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 6>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - cdsp_1_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - cdsp2-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 7>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - thermal-hal-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - - cdsp_2_config: junction-config { - temperature = <95000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - video-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 8>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - mem-thermal { - polling-delay-passive = <10>; - polling-delay = <0>; - thermal-sensors = <&tsens1 9>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - ddr_config0: ddr0-config { - temperature = <90000>; - hysteresis = <5000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 10>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss0_config0: mdmss0-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss0_config1: mdmss0-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 11>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss1_config0: mdmss1-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss1_config1: mdmss1-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem2-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 12>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss2_config0: mdmss2-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss2_config1: mdmss2-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - modem3-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 13>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - mdmss3_config0: mdmss3-config0 { - temperature = <102000>; - hysteresis = <3000>; - type = "passive"; - }; - - mdmss3_config1: mdmss3-config1 { - temperature = <105000>; - hysteresis = <3000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - camera0-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 14>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - - camera1-thermal { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens1 15>; - - trips { - thermal-engine-config { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - - reset-mon-cfg { - temperature = <115000>; - hysteresis = <5000>; - type = "passive"; - }; - }; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; - clock-frequency = <19200000>; - }; -}; |