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2018-12-12MLK-20577 imx8qxp: Fix wrong LPCG register address for MIPI i2cYe Li
The previous LPCG register addresses seem wrong. By checking the LPCG with JTAG, the ipg_clk, ipg_s_clk, and perclk uses one register as the standard implementation method, not use 3 registers. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 10f8f616d50f0f13f32a75ed390245d902ae0d9b)
2018-12-11MLK-20528-2 imx8: Enable clocks LPCGYe Li
To support partition reboot, the u-boot has to enable clocks by LPCG. The LPCG will reset to default value only when the subsystem is totally power off and reset. However, the resources in one subsystem may belong to different partitions, so the partition reboot may not reboot the entire subsystem. Powers, clocks/lpcg, GPR, IP may not reset depends on various cases and HW design. Thus, AP software has to ensure everything is reset by SW itself to support such above cases. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 484104758d3c2f98d3c9ae493f778b1427e2630c)
2018-12-11MLK-20528-1 imx8: Add lpcg driver for iMX8QM/QXPYe Li
Each module may have one or more lpcg registers for SW/HW enabling its clocks. Add lpcg register address and its driver for accessing lpcg. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 19f234266e07c18ab8364336779bf2d3d1f51c81)
2018-11-22TEE-329-1: OP-TEE: Allow ATF to pass boot arg to u-bootSilvano di Ninno
u-boot currently needs information from ATF to know if OP-TEE os has been loaded. this information is transmitted via bootargs. this patch enables saving those bootargs into a structure. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit 697cfe9dbdc079b68d8b5685b728a7283c837607)
2018-11-15MLK-20373-1 Intrdouce xen header filesPeng Fan
Introduce xen header files from Linux Kernel commit e2b623fbe6a3("Merge tag 's390-4.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Flynn xu <flynn.xu@nxp.com>
2018-11-02MLK-20163-02 imx8m: ddr: update the dram driver for i.MX8MBai Ping
Sometimes, SPL need to pass the trained FSP drate to ATF if DDR PHY bypass mode is not enabled. So add a fsp_table to pass these info to ATF. additionally, add more clock frequency point config to support for code reuse for i.MX8MQ. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-11-02MLK-10163-01 imx8mq: Re-desine the dram_pll_init functionBai Ping
Change the dram_pll_init function API to make it same as i.MX8MM, so the dram init flow can use call the same API for these two different SOC. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-11-02MA-13276 [Auto] Generate key blob when set the rpmb keyJi Luo
Generate the key blob and store it to the last block of boot1 partition after setting the rpmb key. The key blob should be checked in spl and be passed to Trusty OS if it's valid. If the key blob are damaged, RPMB storage proxy service will return fail and should make the device hang. Test: Build and boot ok on imx8qm/qxp. Change-Id: Ia274cd72109ab6ae15920e91b2a2008e1f1e667c Signed-off-by: Ji Luo <ji.luo@nxp.com>
2018-11-02MLK-19877-1: iMX8QXP: Add NAND SPL supportTeo Hall
Add implementation necessary for supporting SPL on QXP ARM2 board with dynamic offset detection from container header. Signed-off-by: Teo Hall <teo.hall@nxp.com>
2018-11-02MLK-20116-1 imx7ulp: Update iomux pins header file for Rev B0 chipYe Li
i.MX7ULP B0 silicon has below updates in iomux - GPIO function input buffer enable (IBE)/output buffer enable (OBE) is now controlled by RGPIO module. IOMUXC IBE/OBE is used as an override. - LPUART2_TX (I/O) to PTB12 (ALT4) - LPUART2_RX (I) to PTB13 (ALT4) - USB0_ID (I) to PTC13 (ALT11), PTC18 (ALT11) and PTC19 (ALT10) - VIU_DE (I) to PTC18 (ALT12), PTC19 (ALT12) and PTE5 (ALT12) - RTC_CLKOUT (O) to PTB5 (ALT11) and PTB14 (ALT11) - SEC_VIO_B (I) to PTB4 (ALT11) - Added new Input Selection Registers PSMI1_USB0_ID Address: 0x40ac_0338 To select USB_ID input pad/source PSMI1_VIU_DE Address: 0x40ac_033c To select VIU_DE input pad/source Copy the imx7ulp-pinfunc.h from latest kernel dts (commit 18cdeadfe1967ea33d3bdfc7ccead6d6d06a98a6), and update the mx7ulp-pins.h accordingly. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-10-29MLK-20031-1 imx8qm/qxp: Update SCFW API to latest versionYe Li
Update API files generated from latest SCFW commit: commit b5dbcf59157cf758da2b96c395e3f4cb2674437f Author: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com> Date: Sat Oct 27 02:04:47 2018 -0500 SCF-248 Fix Linux boot fail on iMX8QX Signed-off-by: Ye Li <ye.li@nxp.com>
2018-10-24MLK-20049-1 imx8mm: Update DRAM PLL settings for 266Mhz and 167MhzYe Li
Added two DRAM PLL frequencies 266Mhz and 167Mhz output support. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-10-17MLK-19960-1 imx8mm: Add support for variant partsYe Li
iMX8MM family has several variant parts below. Add CPU type and relevant updates i.MX 8M Mini Quad Full featured, 4x A53 i.MX 8M Mini QuadLite No VPU, 4x A53 i.MX 8M Mini Dual Full featured, 2x A53 i.MX 8M Mini DualLite No VPU, 2x A53 i.MX 8M Mini Solo Full featured, 1x A53 i.MX 8M Mini SoloLite No VPU, 1x A53 Signed-off-by: Ye Li <ye.li@nxp.com>
2018-10-15MLK-19945 mx6dq: hab: Fix chip version in hab.h codeBreno Lima
Since commit 8891410c729b ("MLK-19848 mx6dq: Fix chip version issue for rev1.3") it's not possible to call the HAB API functions on i.MX6DQ SoC Rev 1.3: Authenticate image from DDR location 0x12000000... undefined instruction pc : [<412c00dc>] lr : [<8ff560bc>] reloc pc : [<c8b6d0dc>] lr : [<178030bc>] sp : 8ef444a8 ip : 126e8068 fp : 8ff59aa8 r10: 8ffd51e4 r9 : 8ef50eb0 r8 : 006e8000 r7 : 00000000 r6 : 126ea01f r5 : 0000002b r4 : 126e8000 r3 : 412c00dd r2 : 00000001 r1 : 00000001 r0 : 00000063 Flags: nzCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... resetting ... The hab.h code is defining the HAB API base address according to the old SoC revision number, thus failing when calling the HAB API authenticate_image() function. Fix this issue by using mx6dq rev 1.3 instead of mx6dq rev 1.5. Signed-off-by: Breno Lima <breno.lima@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2018-10-10MLK-19869-1 imx6: improve the is_boot_from_usb implementationYe Li
Currently the is_boot_from_usb is checking the USB PHY Powerdown bit. This way has a defect that if we run any usb function in u-boot the checking will always return true. This patch improves the way to avoid such problem above. A new arch-specific flag is added to indicate if it is USB boot. We check the USB PHY PWD bit at early of boot stage then set that flag. So any following calling of is_boot_from_usb will return correct value. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-10-01MLK-19789 mach-imx: imx8: Make the eMMC container offset SOC dependantAbel Vesa
This is a hack for imx8qm-mek, since the offset of the flash.bin image on eMMC differs when compared to imx8qxp-mek. Basically, the default value is 32K, but for 8qm-mek it's 0. This can go away once the qm and qxp get aligned (again) from this point of view. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2018-10-01MLK-19777-02 imx8mm: rename lpddr4_timing variable to dram_timing.Bai Ping
For LPDDR4 and DDR4, we use the same dram_timing struct to config parameters. rename the 'lpddr4_timing' to 'dram_timing' for common use. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-10-01MLK-19777-01: imx8mm: rename the lpddr4_ddrphy_train fileBai Ping
For LPDDR4 or DDR4, the ddr phy train flow is the same. So rename the 'lpddr4_ddrphy_train.c' to 'ddrphy_train.c'. make it more common for reuse and move it to driver/ddr/imx8m/. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-09-19MLK-19627 arm: Round the dma_alloc_coherent memory size to cache line alignedYe Li
When running uuu on iMX8MQ, meet USB enumeration failure in fastboot. The root cause is a cache issue in dwc3 driver. When the issue happens, the ctrl_req in gadget driver is allocated at 0xfe932f40, and the usb_composite_dev (cdev) is allocated at 0xfe932f60. So after we submit the setup request (cache flushed) to USB controller, any accessing to usb_composite_dev variable will cause the cache refill, then when setup transfer is completed, reading the setup data in ctrl_req will gets old value from cache not from memory. The ctrl_req is allocated by API dma_alloc_coherent, but u-boot don't have cohernet memory. so it still needs cache maintain operations before/after HW accessing. Since the cache flush or invalidate bases on cache line, so when the allocated memory size is not cache line aligned, potentially it may meet such issue. This patch modifies the dma_alloc_coherent API to round the size to cache line aligned. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-09-18MLK-19219-4 iMX8QXP/QM: Add support to get container image set size from QSPIAbel Vesa
This transforms almost all related functions from mmc specific to device independent. This allows the container size to be computed from QSPI and other future devices that will be supported for boot. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2018-09-14MLK-19589 baord: imx6ulz: add imx6ulz supportBai Ping
Add i.MX6ULZ support. the i.MX6ULZ is SW compatible with i.MX6ULL. so most code of i.MX6ULL can be reused by i.MX6ULZ. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-09-11MLK-19526-5 imx8mq: Power down core 2/3 for iMX8MDYe Li
CPU 2/3 are fused on iMX8MD, power down the two cores in SPL to save power. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-09-11MLK-19526-1 imx8mq: Add CPU ID for iMX8MD and iMX8MQLiteYe Li
iMX8MQ has two variant versions: iMX8MD and iMX8MQLite. Add dummy CPU ID for these two, and check the fuses to get correct versions. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-09-04MLK-19433-1 imx: Add macro for chip rev 2.1Ye Li
Add common CHIP_REV_2_1 for chip revision 2.1 Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit f7fc83ffb0f204d9f6ec6c77c08d23869d9ecde4)
2018-08-28MLK-18901-4 imx8qm/qxp: Add clocks command supportYe Li
Add "clocks" command to list clocks values for core and some peripherals on QM/QXP. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit c2c9b6487440946a52564ee20c2b1943a4085152)
2018-08-23MLK-19308 mx7d_lpddr3_arm2: Fix plugin boot failed issueYe Li
The QOS relevant registers are not defined in register header file. When building plugin, these addresses are set to 0 and cause plugin failed. Move the QOS registers definitions from set_epdc_qos to register header file to fix the issue. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-08-21MLK-19223 arm: imx8mm: add MXC_XXX_CLK clock map for imx common codeHaibo Chen
Now fsl_esdhc driver require the index of USDHCx_CLK_ROOT should be defined sequentially. otherwise driver may get the wrong usdhc root clock. e.g. for imx8mm, usdhc3, driver actually get the rate of I2C1_CLK_ROOT This patch add MXC_XXX_CLK, map to the real defined clock index. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> (cherry picked from commit 5cddab6e02e99a748f66e32880906aa427dc8e60) Conflicts: arch/arm/cpu/armv8/imx8m/clock_imx8mm.c
2018-08-20[iot] Make dcache inner shareableHaoran.Wang
As u-boot use no SMP so not care shareable cache. But the Trusty OS will check the memory attr for inner shareable. So add the flag to mark the memory to be inner shareable for ARMv7 only. Change-Id: I322101d01346834aa3fad30ac788fe394336aa1a Signed-off-by: Haoran.Wang <elven.wang@nxp.com>
2018-08-16MLK-18502: board:imx8mm_evk enable tzascSilvano di Ninno
Enable TZASC on i.MX 8mm. There is a need on 8MM to enable the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-08-14MLK-19219-2 imx8qm/qxp: Add support to get container image set sizeYe Li
Add relevant functions and files to parse the container image set from mmc/sd and get the total size of it. So we can get the offset of u-boot-atf.bin image when it is padded to container image set at 1KB alignment position. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-08-05MLK-18431-02: add a more generic dram init flow for imx8mBai Ping
the dram init is board related. But there is still some common part can be reused on different board. The basic flow is common for all the board. only the DDRC and DDR PHY config register setting is different on different board. So extract the LPDDR4 init common flow to make it more generic. baord level only need to provide the DDRC and PHY config register parameter to the common code to finish the dram init. the same method can be use for DDR4. will be added later. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 220d0cc79a3f340e0da664242bb19ccda7a071d1)
2018-07-19MLK-18945-9 imx8mm: Update SOC codes to support LCDIFYe Li
Enable the video PLL (594Mhz) and clocks in displaymix. Add the LCDIF clock set interface to change its dot clock rate. Update registers header file for LCDIF base address. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 3c27bc4bfa35dbebee2b5797c9137a2257946eca)
2018-07-03MLK-18732-1: Add SMC based fuse command for MX8Teo Hall
Modify the fuse subsystem to add a SMC call for writing/reading to the OTP memory. Signed-off-by: Teo Hall <teo.hall@nxp.com>
2018-07-01MLK-18639-1 imx8mm: clock: Add API to enable/disable DDR bypass clockYe Li
The DRAM PLL generates clock to both DRAM controller & PHY, from 166.7MHz to 800MHz. So it can't be used when we need lower DDR frequency. The DRAM PHY supports a bypass mode to allow lower frequency operation from DDR-50 to DDR-666. In this mode, the PLL inside PHY is disabled, the PHY clock is provided externally as BypassPclk which is generated from dram_alt_clk_root. We add APIs for this bypass mode, to support frequencies for DDR-100, DDR-250 and DDR-400, which are needed when training DDR4. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 323b7377dd3babc03f883355c140690259dd12d5)
2018-06-13MLK-18577-6 imx8: boot0: add boot headerPeng Fan
Starting U-Boot in a XEN VM, needs a header, just like Linux Kernel. Without it, xen tool will take is as a file not supported. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 344ddf76c6de808699ab742d3c11728ca62f36ee)
2018-06-13MLK-18577-5 imx8: update soc code to support uboot in XEN VMPeng Fan
Update SOC code to support U-Boot in a XEN VM. Currently we only support to boot android using uboot in a VM, so there is hardcode that using MMC1_BOOT boot. There are a few small fixes included. For the mmu configuration, the mem map is used from xen guest VM and our iomem space in vm cfg file. The VM use a different MU, so use a wrap for SC_IPC_CH. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 533087bc1bce0c35fead0956b0613971862c280f)
2018-06-13MLK-18591-3 android: Add FSL android fastboot supportYe Li
Porting the FSL android fastboot features from imx u-boot v2017.03 to support all SoCs: imx6/imx7/imx7ulp/imx8/imx8m Signed-off-by: Ye Li <ye.li@nxp.com>
2018-06-13MLK-18591-2 crypto: caam: Add fsl caam driverYe Li
Add the fsl CAAM driver and new commands to implement DEK blob operations, like "caam genblob" to generate encrypted blob and "caam decap" to output orignal plain data. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-05-23MLK-18325 imx8mm_evk: add pmic BD71837/BD71840 support in splRobin Gong
Since default values of some registers of pmic not match well our board design, add BD71837/BD71840 pmic support in spl, for example, RESET key (PWRON_B) pushing time, VDD_DRAM too low for 3Ghz DDR. Signed-off-by: Robin Gong <yibin.gong@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-05-23MLK-18322 imx8mm: Add hab suportYe Li
The imx8mm has changed the address of rvt_hab, use new address for imx8mm. Also enable fuse driver in SPL and update registers maps. The authentication procedure is same as imx8mq. In u-boot, the authentication uses SIP call to trap ATF to run HAB authenticate. Need to work with ATF commit: (commit 7a4d6f90e999ed413d520310cc199901b52b7a04) Users need to add CONFIG_SECURE_BOOT=y to imx8mm_evk_defconfig to enable the feature. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 1118c9960c22c80a452181c6857fd1df86fe05ae)
2018-05-23MLK-18316 imx8: Fix USBOTG disconnect when XRDC blocking is enabledYe Li
We clean USBOTG register USBCMD if it is used in serial download mode. When XRDC blocking is enabled, we can't write this register directly, must enable the OTG power, otherwise the kernel will get SError exception in mfgtool. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit cf2143dc97b2a8f21b828c7386c59ee965d981f2)
2018-05-23MLK-18318: mx7ulp: Enable QSPI interrupt as a wakeup source on MX7ULPFabio Estevam
MX7ULP needs to have the QSPI interrupt configured as a wakeup source in the SIM_WKPU_WAKEUP_ENABLE register, otherwise the QSPI interrupts do not wakeup the CPU from idle mode leading to poor performance in Linux. The SIM_WKPU_WAKEUP_ENABLE register only exists in B0 silicon, so make sure to only write to this register in the B0 version (or greater). Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> (cherry picked from commit 1ab33446d6843f560fb6d14c781f6417225f8f3d)
2018-05-23MLK-18290-3 imx8mm: Add SOC level support for OTG USBYe Li
Enable the OTG power on, add clock fuction and USB base address. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit d4f12cd92b18283daca35b35339a96c557f5127c)
2018-05-23MLK-18243-12 arm: imx8m: add cpu revision for i.MX8MMPeng Fan
Add cpu revision for i.MX8MM Add helper function Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 5fdfc7d73157a5eb9254b43f65edd1bb5f13fd16)
2018-05-23MLK-18243-5 arm: mach-imx: iomux: add i.MX8MM PE propertyYe Li
i.MX8MM has a PE property, it does not have LVTTL Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 96169c1f2de1ac90a244166ab5bb6c874cdfd6bd)
2018-05-23MLK-18243-4 arm: imx8m: add pin header for i.MX8MMPeng Fan
Add pin header file for i.MX8MM To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION needs to be selected. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit e5d3d27f79df1c3a2b8261929e666e6bfdb69abc)
2018-05-23MLK-18243-3 arm: imx8m: add clocks definition for i.MX8MMPeng Fan
Add clock definition for i.MX8MM Move the original definition in clock.h to clock_imx8mq.h Use CONFIG_IMX8MQ/M in clock.h to choose the correct header file. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 5584bcfbf1deb09d48172c21e6e02455095ef9fb)
2018-05-23MLK-18243-2 arm: imx8m: add regs definition for i.MX8MMPeng Fan
Move the original imx-regs.h to imx-regs-imx8mq.h Introduce a new file dedicated for i.MX8MM Use CONFIG_IMX8MQ/M to choose the header in imx-regs.h Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 94d2bfa86cebfc775870d9dbb43f936593fb3aa1)
2018-05-23MLK-18384 imx8mq: Add mfgtool boot checkYe Li
Need to define the is_boot_from_usb, so that u-boot can check whether it is booted for mfgtool. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-05-23MLK-18197: Use MU1 for SCFW API callsTeo Hall
In i.MX8QXP & i.MX8QM MU0 is used as the boot container MU. This is taken by ATF so change the MU that is used for SCFW API to MU1. Signed-off-by: Teo Hall <teo.hall@nxp.com> (cherry picked from commit d5aa444f3e83550e934d09982c76ea74e53fbedf)
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