diff options
| author | Haibo Chen <haibo.chen@nxp.com> | 2018-08-21 11:31:39 +0800 |
|---|---|---|
| committer | Haibo Chen <haibo.chen@nxp.com> | 2018-08-21 14:41:33 +0800 |
| commit | ece4a31cdcce239cd35a49929935a8c20312b1aa (patch) | |
| tree | 3796624d59c9a7aa0b9f011e1e473c5f8268802a /arch/arm/include | |
| parent | b918c85c45f81e4759ed45a0ff40ec9642130388 (diff) | |
MLK-19223 arm: imx8mm: add MXC_XXX_CLK clock map for imx common code
Now fsl_esdhc driver require the index of USDHCx_CLK_ROOT should be
defined sequentially. otherwise driver may get the wrong usdhc root
clock.
e.g. for imx8mm, usdhc3, driver actually get the rate of I2C1_CLK_ROOT
This patch add MXC_XXX_CLK, map to the real defined clock index.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 5cddab6e02e99a748f66e32880906aa427dc8e60)
Conflicts:
arch/arm/cpu/armv8/imx8m/clock_imx8mm.c
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-imx8m/clock_imx8mm.h | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h index ad4d455cf2..52358d4294 100644 --- a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h @@ -9,6 +9,19 @@ #ifndef _ASM_ARCH_IMX8MM_CLOCK_H #define _ASM_ARCH_IMX8MM_CLOCK_H +/* Mainly for compatible to imx common code. */ +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_IPG_CLK, + MXC_CSPI_CLK, + MXC_ESDHC_CLK, + MXC_ESDHC2_CLK, + MXC_ESDHC3_CLK, + MXC_I2C_CLK, + MXC_UART_CLK, + MXC_QSPI_CLK, +}; + enum pll_clocks { ANATOP_ARM_PLL, ANATOP_VPU_PLL, @@ -33,7 +46,6 @@ enum clk_slice_type { }; enum clk_root_index { - MXC_ARM_CLK = 0, ARM_A53_CLK_ROOT = 0, ARM_M4_CLK_ROOT = 1, VPU_A53_CLK_ROOT = 2, @@ -54,7 +66,6 @@ enum clk_root_index { AHB_CLK_ROOT = 32, /* TODO: IPG Not sure */ IPG_CLK_ROOT = 33, - MXC_IPG_CLK = 33, AUDIO_AHB_CLK_ROOT = 34, MIPI_DSI_ESC_RX_CLK_ROOT = 36, DRAM_SEL_CFG = 48, @@ -83,12 +94,9 @@ enum clk_root_index { ENET_PHY_REF_CLK_ROOT = 85, NAND_CLK_ROOT = 86, QSPI_CLK_ROOT = 87, - MXC_ESDHC_CLK = 88, USDHC1_CLK_ROOT = 88, - MXC_ESDHC2_CLK = 89, USDHC2_CLK_ROOT = 89, I2C1_CLK_ROOT = 90, - MXC_I2C_CLK = 90, I2C2_CLK_ROOT = 91, I2C3_CLK_ROOT = 92, I2C4_CLK_ROOT = 93, @@ -99,7 +107,6 @@ enum clk_root_index { USB_CORE_REF_CLK_ROOT = 98, USB_PHY_REF_CLK_ROOT = 99, GIC_CLK_ROOT = 100, - MXC_CSPI_CLK = 101, ECSPI1_CLK_ROOT = 101, ECSPI2_CLK_ROOT = 102, PWM1_CLK_ROOT = 103, @@ -867,7 +874,7 @@ void dram_disable_bypass(void); u32 imx_get_fecclk(void); u32 imx_get_uartclk(void); int clock_init(void); -unsigned int mxc_get_clock(enum clk_root_index clk); +u32 mxc_get_clock(enum mxc_clock clk); int clock_enable(enum clk_ccgr_index index, bool enable); int clock_root_enabled(enum clk_root_index clock_id); int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div, |