diff options
| author | Bai Ping <ping.bai@nxp.com> | 2018-11-01 17:50:34 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@nxp.com> | 2018-11-02 20:50:11 -0500 |
| commit | cb43368096b45abb2e20d169f73d57f60fb75204 (patch) | |
| tree | 45d56b3ae02ff21906d84be49cafcd259f7c09e1 /arch/arm/include | |
| parent | 048327a4f276289c76b7e4280e332f79cb6aa10e (diff) | |
MLK-20163-02 imx8m: ddr: update the dram driver for i.MX8M
Sometimes, SPL need to pass the trained FSP drate to ATF
if DDR PHY bypass mode is not enabled. So add a fsp_table
to pass these info to ATF. additionally, add more clock
frequency point config to support for code reuse for i.MX8MQ.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-imx8m/imx8m_ddr.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-imx8m/imx8m_ddr.h b/arch/arm/include/asm/arch-imx8m/imx8m_ddr.h index ec698cfd88..b319592c93 100644 --- a/arch/arm/include/asm/arch-imx8m/imx8m_ddr.h +++ b/arch/arm/include/asm/arch-imx8m/imx8m_ddr.h @@ -46,6 +46,8 @@ struct dram_timing_info { /* ddr phy PIE */ struct dram_cfg_param *ddrphy_pie; unsigned int ddrphy_pie_num; + /* initialized drate table */ + unsigned int fsp_table[4]; }; extern struct dram_timing_info dram_timing; |