MLK-18639-1 imx8mm: clock: Add API to enable/disable DDR bypass clock

The DRAM PLL generates clock to both DRAM controller & PHY, from 166.7MHz to 800MHz.
So it can't be used when we need lower DDR frequency.
The DRAM PHY supports a bypass mode to allow lower frequency operation from DDR-50 to
DDR-666. In this mode, the PLL inside PHY is disabled, the PHY clock is provided externally
as BypassPclk which is generated from dram_alt_clk_root.

We add APIs for this bypass mode, to support frequencies for DDR-100, DDR-250 and DDR-400,
which are needed when training DDR4.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 323b7377dd3babc03f883355c140690259dd12d5)

1 files changed, 8 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
index 3193449ea6..ad4d455cf2 100644
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
@@ -465,6 +465,12 @@ enum dram_pll_out_val {
 	DRAM_PLL_OUT_800M,
 };
 
+enum dram_bypassclk_val {
+	DRAM_BYPASSCLK_100M,
+	DRAM_BYPASSCLK_250M,
+	DRAM_BYPASSCLK_400M,
+};
+
 #define AUDIO_PLL1_GNRL_CTL			(0x30360000)
 #define AUDIO_PLL1_FDIV_CTL0			(0x30360004)
 #define AUDIO_PLL1_FDIV_CTL1			(0x30360008)
@@ -856,6 +862,8 @@ enum enet_freq {
 	ENET_125MHZ,
 };
 void dram_pll_init(enum dram_pll_out_val pll_val);
+void dram_enable_bypass(enum dram_bypassclk_val clk_val);
+void dram_disable_bypass(void);
 u32 imx_get_fecclk(void);
 u32 imx_get_uartclk(void);
 int clock_init(void);