diff options
| author | Ye Li <ye.li@nxp.com> | 2018-08-22 22:04:22 -0700 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2018-08-23 01:40:28 -0700 |
| commit | 11b519b7805d1467cb4c35a5fa96f38da7d78497 (patch) | |
| tree | 4a0e9d54155c2f87fdf6e8d230be8c640d23bdfc /arch/arm/include | |
| parent | b1c1ad38c24e757d27f480923a3f840d8ad267eb (diff) | |
MLK-19308 mx7d_lpddr3_arm2: Fix plugin boot failed issue
The QOS relevant registers are not defined in register header file.
When building plugin, these addresses are set to 0 and cause plugin
failed.
Move the QOS registers definitions from set_epdc_qos to register
header file to fix the issue.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-mx7/imx-regs.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index 3726f02af5..7058b3f7fe 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -213,6 +213,10 @@ #define SEMAPHORE1_BASE_ADDR SEMA41_IPS_BASE_ADDR #define SEMAPHORE2_BASE_ADDR SEMA42_IPS_BASE_ADDR #define RDC_BASE_ADDR RDC_IPS_BASE_ADDR +#define REGS_QOS_BASE QOSC_IPS_BASE_ADDR +#define REGS_QOS_EPDC (QOSC_IPS_BASE_ADDR + 0x3400) +#define REGS_QOS_PXP0 (QOSC_IPS_BASE_ADDR + 0x2C00) +#define REGS_QOS_PXP1 (QOSC_IPS_BASE_ADDR + 0x3C00) #define FEC_QUIRK_ENET_MAC #define SNVS_LPGPR 0x68 |