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/** @file
*
* Copyright (c) 2013-2016, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#include <arm_gic.h>
#include <plat_arm.h>
#include <platform.h>
#define CLUSTER_1_MASK 0x100
#define CORE_PRESENT 1
#if IMAGE_NS_BL2U
extern unsigned long __RO_SIZE__;
#define NS_BL2U_RO_SIZE (unsigned long)(&__RO_SIZE__)
#endif /* IMAGE_NS_BL2U */
/*
* Table of regions to map using the MMU.
*/
#if IMAGE_NS_BL1U
static const mmap_region_t mmap[] = {
{ FLASH_BASE, FLASH_BASE, FLASH_SIZE,
MT_MEMORY | MT_RO | MT_NS },
{ DRAM_BASE, DRAM_BASE, DRAM_SIZE,
MT_MEMORY | MT_RW | MT_NS },
{ DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE,
MT_DEVICE | MT_RW | MT_NS },
{ NSRAM_BASE, NSRAM_BASE, NSRAM_SIZE,
MT_MEMORY | MT_RW | MT_NS },
{0}
};
#elif IMAGE_NS_BL2U
static const mmap_region_t mmap[] = {
{ DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_NS },
{ DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS },
{ FLASH_BASE, FLASH_BASE, FLASH_SIZE, MT_DEVICE | MT_RW | MT_NS },
{ DRAM_BASE, DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS },
{ NS_BL2U_BASE, NS_BL2U_BASE, NS_BL2U_RO_SIZE, MT_MEMORY | MT_RO | MT_NS }, /* Program text */
{ 0 }
};
#elif IMAGE_TFTF
static const mmap_region_t mmap[] = {
{ DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_NS },
{ DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS },
#if USE_NVM
{ FLASH_BASE, FLASH_BASE, FLASH_SIZE, MT_DEVICE | MT_RW | MT_NS },
#endif
{ DRAM_BASE, DRAM_BASE, TFTF_BASE - DRAM_BASE, MT_MEMORY | MT_RW | MT_NS },
{ TFTF_BASE, TFTF_BASE, L2_BLOCK_SIZE, MT_MEMORY | MT_RO | MT_NS }, /* Program text */
{ TFTF_BASE + L2_BLOCK_SIZE, TFTF_BASE + L2_BLOCK_SIZE,
(DRAM_BASE + DRAM_SIZE) - (TFTF_BASE + L2_BLOCK_SIZE), MT_MEMORY | MT_RW | MT_NS },
{ 0xFFFFFFFF - DRAM_TZ_SIZE + 1, 0xFFFFFFFF - DRAM_TZ_SIZE + 1, DRAM_TZ_SIZE, MT_MEMORY | MT_RW | MT_NS },
{ ARM_SECURE_SERVICE_BUFFER_BASE, ARM_SECURE_SERVICE_BUFFER_BASE,
ARM_SECURE_SERVICE_BUFFER_SIZE, MT_MEMORY | MT_RW | MT_NS },
{ 0 }
};
#endif /* IMAGE_NS_BL1U */
const mmap_region_t *tftf_platform_get_mmap(void)
{
return mmap;
}
void plat_arm_gic_init(void)
{
arm_gic_init(GICC_BASE, GICD_BASE, GICR_BASE);
}
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