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/*
* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <arm_def.h>
#include "../fvp_def.h"
/*******************************************************************************
* Platform definitions used by common code
******************************************************************************/
#ifndef __PLATFORM_DEF_H__
#define __PLATFORM_DEF_H__
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
#ifndef AARCH32
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
#else
#define PLATFORM_LINKER_FORMAT "elf32-littlearm"
#define PLATFORM_LINKER_ARCH arm
#endif
/*******************************************************************************
* Run-time address of the TFTF image.
* It has to match the location where the trusted firmware loads the BL3-3
* image.
******************************************************************************/
#define TFTF_BASE 0x88000000
/* Base address of non-trusted watchdog (SP805) */
#define SP805_WDOG_BASE 0x1C0F0000
/*******************************************************************************
* Base address and size of external NVM flash
******************************************************************************/
#define FLASH_BASE 0x08000000
/*
* The flash memory in FVP resembles as a SCSP package of 2-die's and
* of a total size of 512Mb, we are using only the main blocks of size
* 128KB for storing results. Also the FVP performs data striping and
* splits the word into half to each flash die's which leads to a
* virtual block size of 256KB to software.
*/
#define NOR_FLASH_BLOCK_SIZE 0x40000 /* 256KB */
#define NOR_FLASH_BLOCKS_COUNT 255
#define FLASH_SIZE (NOR_FLASH_BLOCK_SIZE * NOR_FLASH_BLOCKS_COUNT)
/*******************************************************************************
* Base address and size for the FIP that contains FWU images.
******************************************************************************/
#define PLAT_ARM_FWU_FIP_BASE (FLASH_BASE + 0x400000)
#define PLAT_ARM_FWU_FIP_SIZE (0x100000)
/*******************************************************************************
* Base address and size for non-trusted SRAM.
******************************************************************************/
#define NSRAM_BASE (0x2e000000)
#define NSRAM_SIZE (0x00010000)
/*******************************************************************************
* Corresponds to the function ID of the BL1 SMC handler for FWU process.
******************************************************************************/
#define BL1_SMC_CALL_COUNT 0x0
#define BL1_SMC_UID 0x1
/* SMC #0x2 reserved */
#define BL1_SMC_VERSION 0x3
#define FWU_SMC_IMAGE_COPY 0x10
#define FWU_SMC_IMAGE_AUTH 0x11
#define FWU_SMC_IMAGE_EXECUTE 0x12
#define FWU_SMC_IMAGE_RESUME 0x13
#define FWU_SMC_SEC_IMAGE_DONE 0x14
#define FWU_SMC_UPDATE_DONE 0x15
#define FWU_SMC_IMAGE_RESET 0x16
/*******************************************************************************
* NS_BL1U specific defines.
* NS_BL1U RW data is relocated from NS-ROM to NS-RAM at runtime so we
* need 2 sets of addresses.
******************************************************************************/
#define NS_BL1U_RO_BASE (0x08000000 + 0x03EB8000)
#define NS_BL1U_RO_LIMIT (NS_BL1U_RO_BASE + 0x8000)
/*******************************************************************************
* Put NS_BL1U RW at the top of the Non-Trusted SRAM. NS_BL1U_RW_BASE is
* calculated using the current NS_BL1U RW debug size plus a little space
* for growth.
******************************************************************************/
#define NS_BL1U_RW_SIZE (0x5000)
#define NS_BL1U_RW_BASE (NSRAM_BASE)
#define NS_BL1U_RW_LIMIT (NS_BL1U_RW_BASE + NS_BL1U_RW_SIZE)
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
#define DRAM_BASE 0x80000000
#define DRAM_SIZE 0x80000000
/*******************************************************************************
* Base address and limit for NS_BL2U image.
******************************************************************************/
#define NS_BL2U_BASE DRAM_BASE
#define NS_BL2U_LIMIT (NS_BL2U_BASE + 0x4C000)
/******************************************************************************
* Memory mapped Generic timer interfaces
******************************************************************************/
/* AP_REFCLK CNTBase1, Generic Timer. */
#define SYS_CNT_BASE1 0x2a830000
/* Size of a block as mapped by a second-level translation table */
#define L2_BLOCK_SIZE 0x200000
/* V2M motherboard system registers & offsets */
#define VE_SYSREGS_BASE 0x1c010000
#define V2M_SYS_LED 0x8
/*
* Size of memory region configured as secure DRAM by the trusted firmware
* through the TrustZone Controller
*/
#define DRAM_TZ_SIZE 0x01000000ull
/*******************************************************************************
* Generic platform constants
******************************************************************************/
/* Size of cacheable stacks */
#if IMAGE_NS_BL1U || IMAGE_NS_BL2U
#define PLATFORM_STACK_SIZE 0x800
#else
#define PLATFORM_STACK_SIZE 0xb80
#endif
/* Size of coherent stacks for debug and release builds */
#if DEBUG
#define PCPU_DV_MEM_STACK_SIZE 0x400
#else
#define PCPU_DV_MEM_STACK_SIZE 0x300
#endif
#define PLATFORM_CORE_COUNT (FVP_CLUSTER_COUNT * \
FVP_MAX_CPUS_PER_CLUSTER)
#define PLATFORM_NUM_AFFS (1 + FVP_CLUSTER_COUNT + \
PLATFORM_CORE_COUNT)
#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
/* TODO : Migrate complete TFTF from affinity level to power levels */
#define PLAT_MAX_PWR_LEVEL PLATFORM_MAX_AFFLVL
#define PLAT_MAX_PWR_STATES_PER_LVL 2
#if IMAGE_NS_BL1U
#define MAX_IO_DEVICES 2
#define MAX_IO_HANDLES 2
#else
#define MAX_IO_DEVICES 1
#define MAX_IO_HANDLES 1
#endif
/* Local state bit width for each level in the state-ID field of power state */
#define PLAT_LOCAL_PSTATE_WIDTH 4
#if USE_NVM
/*
* The Flash memory is used to store the TFTF data on FVP.
* However, it might contain other data that must not be overwritten.
* For example, when using the ARM Trusted Firmware, the FIP image
* (containing the bootloader images) is also stored in Flash.
* Hence, consider the first 40MB of Flash as reserved for firmware usage.
* The TFTF can use the rest of the Flash memory.
*/
#define TFTF_NVM_OFFSET 0x2800000 /* 40 MB */
#define TFTF_NVM_SIZE (FLASH_SIZE - TFTF_NVM_OFFSET)
#else
/*
* If you want to run without support for non-volatile memory (due to
* e.g. unavailability of a flash driver), DRAM can be used instead as
* a workaround. The TFTF binary itself is loaded at 0x88000000 so the
* first 128MB can be used
* Please note that this won't be suitable for all test scenarios and
* for this reason some tests will be disabled in this configuration.
*/
#define TFTF_NVM_OFFSET 0x0
#define TFTF_NVM_SIZE (TFTF_BASE - DRAM_BASE - TFTF_NVM_OFFSET)
#endif
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define ADDR_SPACE_SIZE (1ull << 32)
#if IMAGE_TFTF
#define MAX_XLAT_TABLES 5
#define MAX_MMAP_REGIONS 16
#else
#define MAX_XLAT_TABLES 4
#define MAX_MMAP_REGIONS 16
#endif
/*******************************************************************************
* Used to align variables on the biggest cache line size in the platform.
* This is known only to the platform as it might have a combination of
* integrated and external caches.
******************************************************************************/
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
/*******************************************************************************
* Non-Secure Software Generated Interupts IDs
******************************************************************************/
#define IRQ_NS_SGI_0 0
#define IRQ_NS_SGI_1 1
#define IRQ_NS_SGI_2 2
#define IRQ_NS_SGI_3 3
#define IRQ_NS_SGI_4 4
#define IRQ_NS_SGI_5 5
#define IRQ_NS_SGI_6 6
#define IRQ_NS_SGI_7 7
/*
* On FVP, consider that the last SPI is the Trusted Random Number Generator
* interrupt.
*/
#define PLAT_MAX_SPI_OFFSET_ID 107
/* AP_REFCLK, Generic Timer, CNTPSIRQ1. */
#define IRQ_CNTPSIRQ1 58
/* Per-CPU Hypervisor Timer Interrupt ID */
#define IRQ_PCPU_HP_TIMER 26
/* Per-CPU Non-Secure Timer Interrupt ID */
#define IRQ_PCPU_NS_TIMER 30
/* Times(in ms) used by test code for completion of different events */
#define PLAT_SUSPEND_ENTRY_TIME 15
#define PLAT_SUSPEND_ENTRY_EXIT_TIME 30
#endif /* __PLATFORM_DEF_H__ */
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