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/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <asm_macros.S>
#include <tftf.h>
.globl tftf_entrypoint
.globl tftf_hotplug_entry
/* ----------------------------------------------------------------------------
* Cold boot entry point for the primary CPU.
* ----------------------------------------------------------------------------
*/
func tftf_entrypoint
/* --------------------------------------------------------------------
* Set the exception vectors
* --------------------------------------------------------------------
*/
ldr r0, =tftf_vector
/* check hypervisor mode support status */
mrs r2, cpsr
and r1, r2, #0x1f @ mask mode bits
teq r1, #0x1a @ test for HYP mode
bne non_hyp_setup
stcopr r0, HVBAR
/* --------------------------------------------------------------------
* Enable the instruction cache and asynchronous interrupts.
* --------------------------------------------------------------------
*/
ldcopr r0, HSCTLR
ldr r1, =(HSCTLR_I_BIT | HSCTLR_A_BIT)
orr r0, r0, r1
stcopr r0, HSCTLR
b entrypoint_exit
non_hyp_setup:
/* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
mrc p15, 0, r1, c1, c0, 0 @ Read CP15 SCTLR Register
bic r1, #0x2000 @ V = 0
mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
stcopr r0, VBAR
ldcopr r0, SCTLR
ldr r1, =(HSCTLR_I_BIT | HSCTLR_A_BIT)
orr r0, r0, r1
stcopr r0, SCTLR
entrypoint_exit:
isb
/* --------------------------------------------------------------------
* This code is expected to be executed only by the primary CPU.
* Save the mpid for the first core that executes and if a secondary
* CPU has lost its way make it spin forever.
* --------------------------------------------------------------------
*/
bl save_primary_mpid
/* --------------------------------------------------------------------
* Zero out NOBITS sections. There are 2 of them:
* - the .bss section;
* - the coherent memory section.
* --------------------------------------------------------------------
*/
ldr r0, =__BSS_START__
ldr r1, =__BSS_SIZE__
bl zeromem
ldr r0, =__COHERENT_RAM_START__
ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__
bl zeromem
/* --------------------------------------------------------------------
* Give ourselves a small coherent stack to ease the pain of
* initializing the MMU
* --------------------------------------------------------------------
*/
ldcopr r0, MPIDR
bl platform_set_coherent_stack
bl tftf_early_platform_setup
bl tftf_plat_arch_setup
/* --------------------------------------------------------------------
* Give ourselves a stack allocated in Normal -IS-WBWA memory
* --------------------------------------------------------------------
*/
ldcopr r0, MPIDR
bl platform_set_stack
/* --------------------------------------------------------------------
* tftf_cold_boot_main() will perform the remaining architectural and
* platform setup, initialise the test framework's state, then run the
* tests.
* --------------------------------------------------------------------
*/
b tftf_cold_boot_main
endfunc tftf_entrypoint
/* ----------------------------------------------------------------------------
* Entry point for a CPU that has just been powered up.
* In : r0 - context_id
* ----------------------------------------------------------------------------
*/
func tftf_hotplug_entry
/* --------------------------------------------------------------------
* Preserve the context_id in a callee-saved register
* --------------------------------------------------------------------
*/
mov r4, r0
/* --------------------------------------------------------------------
* Set the exception vectors
* --------------------------------------------------------------------
*/
ldr r0, =tftf_vector
/* check hypervisor mode support status */
mrs r2, cpsr
and r1, r2, #0x1f @ mask mode bits
teq r1, #0x1a @ test for HYP mode
bne non_hyp_hotplug
stcopr r0, HVBAR
/* --------------------------------------------------------------------
* Enable the instruction cache and asynchronous interrupts.
* --------------------------------------------------------------------
*/
ldcopr r0, HSCTLR
ldr r1, =(HSCTLR_I_BIT | HSCTLR_A_BIT)
orr r0, r0, r1
stcopr r0, HSCTLR
b non_hyp_hotplug_done
non_hyp_hotplug:
stcopr r0, VBAR
ldcopr r0, SCTLR
ldr r1, =(HSCTLR_I_BIT | HSCTLR_A_BIT)
orr r0, r0, r1
stcopr r0, SCTLR
non_hyp_hotplug_done:
isb
/* --------------------------------------------------------------------
* Give ourselves a small coherent stack to ease the pain of
* initializing the MMU
* --------------------------------------------------------------------
*/
ldcopr r0, MPIDR
bl platform_set_coherent_stack
/* --------------------------------------------------------------------
* Enable the MMU
* --------------------------------------------------------------------
*/
bl tftf_plat_enable_mmu
/* --------------------------------------------------------------------
* Give ourselves a stack in normal memory.
* --------------------------------------------------------------------
*/
ldcopr r0, MPIDR
bl platform_set_stack
/* --------------------------------------------------------------------
* Save the context_id for later retrieval by tests
* --------------------------------------------------------------------
*/
ldcopr r0, MPIDR
ldr r1, =MPID_MASK
and r0, r0, r1
bl platform_get_core_pos
mov r1, r4
bl tftf_set_cpu_on_ctx_id
/* --------------------------------------------------------------------
* Jump to warm boot main function
* --------------------------------------------------------------------
*/
b tftf_warm_boot_main
endfunc tftf_hotplug_entry
/* ----------------------------------------------------------------------------
* Saves the mpid of the primary core and if the primary core
* is already saved then it loops infinitely.
* ----------------------------------------------------------------------------
*/
func save_primary_mpid
ldr r1, =tftf_primary_core
ldr r0, [r1]
mov r2, #INVALID_MPID
cmp r0, r2
bne panic
ldr r2, =MPID_MASK
ldcopr r0, MPIDR
and r0, r0, r2
str r0, [r1]
bx lr
panic:
/* Primary core MPID already saved */
b panic
endfunc save_primary_mpid
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