diff options
Diffstat (limited to 'drivers/arm/gic/ns_gic_v2.c')
| -rw-r--r-- | drivers/arm/gic/ns_gic_v2.c | 159 |
1 files changed, 0 insertions, 159 deletions
diff --git a/drivers/arm/gic/ns_gic_v2.c b/drivers/arm/gic/ns_gic_v2.c deleted file mode 100644 index 0091c22..0000000 --- a/drivers/arm/gic/ns_gic_v2.c +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include <arch.h> -#include <arch_helpers.h> -#include <assert.h> -#include <gic_v2.h> -#include <pl011.h> -#include <platform.h> -#include <string.h> - -static uint64_t gicc_base_addr; -static uint64_t gicd_base_addr; -static uint64_t gicr_base_addr; - -/******************************************************************************* - * Enable NS interrupts and disable legacy bypass and set the priority mask - * register to allow all interrupts to trickle in. - ******************************************************************************/ -void ns_gic_cpuif_setup(void) -{ - uint32_t gicc_ctlr; - - assert(gicc_base_addr); - - gicc_write_pmr(gicc_base_addr, GIC_PRI_MASK); - - gicc_ctlr = NS_ENABLE_GRP1 | NS_FIQ_BYP_DIS_GRP1 | NS_IRQ_BYP_DIS_GRP1; - gicc_write_ctlr(gicc_base_addr, gicc_ctlr); -} - -/******************************************************************************* - * Place the cpu interface in a state where it can never make a cpu exit wfi as - * as result of an asserted interrupt. This is critical for powering down a cpu - ******************************************************************************/ -void ns_gic_cpuif_deactivate(void) -{ - uint32_t gicc_ctlr; - - assert(gicc_base_addr); - - /* Disable non-secure interrupts and disable their bypass */ - gicc_ctlr = gicc_read_ctlr(gicc_base_addr); - gicc_ctlr &= ~NS_ENABLE_GRP1; - gicc_ctlr |= NS_FIQ_BYP_DIS_GRP1 | NS_IRQ_BYP_DIS_GRP1; - gicc_write_ctlr(gicc_base_addr, gicc_ctlr); -} - -/******************************************************************************* - * Global gic distributor setup which will be done by the primary cpu after a - * cold boot. It marks out the NS SPIs, PPIs & SGIs and enables them. It - * then enables the NS GIC distributor interface. - ******************************************************************************/ -static void ns_gic_distif_setup(void) -{ - uint32_t gicd_ctlr; - - assert(gicd_base_addr); - - /* Enable the distributor */ - gicd_ctlr = gicd_read_ctlr(gicd_base_addr); - gicd_ctlr |= NS_ENABLE_GRP1; - gicd_write_ctlr(gicd_base_addr, gicd_ctlr); -} - -/* - * The only difference between this function and gicd_set_ipriorityr() - * is the absence of the assertion. Non-secure software can only configure - * non-secure interrupts, and the GICD IGROUP register reads as 0 in normal - * world. - */ -void arm_gicd_set_ns_ipriorityr(unsigned int id, unsigned int pri) -{ - uint64_t reg = gicd_base_addr + GICD_IPRIORITYR + (id & ~3); - uint32_t shift = (id & 3) << 3; - uint32_t reg_val = mmio_read_32(reg); - - reg_val &= ~(GIC_PRI_MASK << shift); - reg_val |= (pri & GIC_PRI_MASK) << shift; - mmio_write_32(reg, reg_val); -} - -void arm_gicd_write_sgir(uint32_t sgir_val) -{ - assert(gicd_base_addr); - gicd_write_sgir(gicd_base_addr, sgir_val); -} - -void arm_gicd_set_itargetsr(unsigned int num, unsigned int linear_id) -{ - assert(gicd_base_addr); - gicd_set_itargetsr(gicd_base_addr, num, linear_id); -} - -void arm_gicd_set_isenabler(unsigned int num) -{ - assert(gicd_base_addr); - gicd_set_isenabler(gicd_base_addr, num); -} - -uint32_t arm_gicc_read_IAR(void) -{ - assert(gicc_base_addr); - return gicc_read_IAR(gicc_base_addr); -} - -uint8_t arm_gicd_get_itargetsr(unsigned int id) -{ - assert(gicd_base_addr); - return gicd_read_itargetsr(gicd_base_addr, id); -} - -void arm_gicc_write_EOIR(uint32_t val) -{ - assert(gicc_base_addr); - gicc_write_EOIR(gicc_base_addr, val); -} - -void ns_gic_setup(void) -{ - ns_gic_cpuif_setup(); - ns_gic_distif_setup(); -} - -void ns_gic_init(uint64_t gicc_base, - uint64_t gicd_base, - uint64_t gicr_base) -{ - gicc_base_addr = gicc_base; - gicd_base_addr = gicd_base; - gicr_base_addr = gicr_base; -} |