imx8m: Add iomux and clock setting

Add iomux and clock setting and change BL2 location in SRAM.
Thus ATF will be the first bootloader after boot ROM.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Change-Id: Iebe05c5bff449d7fb337052423e182541e0cc261

3 files changed, 88 insertions, 8 deletions

diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c
index 2c3a5f25..49f6f627 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c
@@ -23,9 +23,58 @@
 #include <common/desc_image_load.h>
 #include <lib/optee_utils.h>
 
+#include <imx_regs.h>
 #include <imx_uart.h>
 #include <imx_usdhc.h>
+#include <imx8_iomux.h>
+#include <imx8m_clock.h>
 
+#define UART1_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
+			  CCM_TARGET_MUX(1))
+
+#define IMX8MM_WDOG_MUX \
+	IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_ALT1_WDOG1_B
+
+#define IMX8MM_WDOG_FEATURES \
+	(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_DSE_3_X6	| \
+	 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_ODE		| \
+	 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUE_EN	| \
+	 IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PE_EN)
+
+#define IMX8MM_UART2_RX_MUX \
+	IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_ALT0_UART2_RX_DATA
+
+#define IMX8MM_UART2_TX_MUX \
+	IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_ALT0_UART2_TX_DATA
+
+#define IMX8MM_UART2_FEATURES \
+	 (IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_SRE_SLOW	| \
+	  IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_DSE_3_X6)
+
+static void imx8mm_setup_pinmux(void)
+{
+	/* Configure wdog */
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_OFFSET,
+					 IMX8MM_WDOG_MUX);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_OFFSET,
+				     IMX8MM_WDOG_FEATURES);
+
+	/* Configure UART2 */
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_OFFSET,
+					 IMX8MM_UART2_TX_MUX);
+	imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_OFFSET,
+					 IMX8MM_UART2_RX_MUX);
+
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_OFFSET,
+				     IMX8MM_UART2_FEATURES);
+	imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_OFFSET,
+				     IMX8MM_UART2_FEATURES);
+
+	imx_io_muxc_select_pad_input(IOMUXC_UART2_RXD_SELECT_INPUT_OFFSET,
+				     IOMUXC_UART2_RXD_SELECT_INPUT_UART2_RXD_ALT0);
+}
+
+#if 0
 static void imx8mm_aips_config(void)
 {
 	/* config the AIPSTZ1 */
@@ -64,6 +113,7 @@ static void imx8mm_aips_config(void)
 	mmio_write_32(0x32df004c, 0x0);
 	mmio_write_32(0x32df0050, 0x0);
 }
+#endif
 
 static void imx8mm_usdhc_setup(void)
 {
@@ -82,9 +132,10 @@ static void imx8mm_usdhc_setup(void)
 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
 				  u_register_t arg3, u_register_t arg4)
 {
-	int i;
+//	int i;
 	static console_uart_t console;
 
+#if 0
 	/* enable CSU NS access permission */
 	for (i = 0; i < 64; i++) {
 		mmio_write_32(0x303e0000 + i * 4, 0x00ff00ff);
@@ -92,10 +143,30 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
 
 	/* config the aips access permission */
 	imx8mm_aips_config();
+#endif
+	/* Initialize clocks */
+	imx_clock_init();
+	/* Setup wdog */
+	mmio_write_16(WDOG1_BASE + WDOG_WMCR, 0);
+	mmio_write_16(WDOG2_BASE + WDOG_WMCR, 0);
+	mmio_write_16(WDOG3_BASE + WDOG_WMCR, 0);
+
+	imx_clock_enable_uart(1, UART1_CLK_SELECT);
+
+	/* Setup pin-muxes */
+	imx8mm_setup_pinmux();
 
+// Add dead loop for JTAG connection
+//asm volatile("b .");
+	/* Reset wdog */
+//	mmio_write_16(IMX_WDOG_BASE + WDOG_WCR, WDOG_WCR_WDT | WDOG_WCR_WDZST);
+
+//asm volatile("b .");
 	console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
 		IMX_CONSOLE_BAUDRATE, &console);
 
+VERBOSE("\tIMX8MM up============\n");
+
 	generic_delay_timer_init();
 
 	/* select the CKIL source to 32K OSC */
@@ -105,7 +176,6 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
 
 	/* Open handles to a FIP image */
 	plat_imx8mm_io_setup();
-
 }
 
 void bl2_el3_plat_arch_setup(void)
diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h
index 8dfb41ba..c5940697 100644
--- a/plat/imx/imx8m/imx8mm/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mm/include/platform_def.h
@@ -32,7 +32,7 @@
 #define PLAT_STOP_OFF_STATE		U(3)
 
 #if defined(BUILD_BL2)
-#define BL2_BASE			U(0x920000)
+#define BL2_BASE			U(0x7E1000)
 #define BL2_LIMIT			U(0x940000)
 #define BL31_BASE			U(0x900000)
 #define BL31_LIMIT			U(0x920000)
@@ -107,7 +107,7 @@
 #define IMX_GIC_BASE			PLAT_GICD_BASE
 #define IMX_GIC_SIZE			U(0x200000)
 
-#define WDOG_WSR			U(0x2)
+#define WDOG_WCR			U(0x0)
 #define WDOG_WCR_WDZST			BIT(0)
 #define WDOG_WCR_WDBG			BIT(1)
 #define WDOG_WCR_WDE			BIT(2)
@@ -117,6 +117,15 @@
 #define WDOG_WCR_SRE			BIT(6)
 #define WDOG_WCR_WDW			BIT(7)
 
+#define WDOG_WSR			U(0x2)
+
+#define WDOG_WRSR			U(0x4)
+
+#define WDOG_WICR			U(0x6)
+
+#define WDOG_WMCR			U(0x8)
+#define WDOG_WMCR_PDE			BIT(0)
+
 #define SRC_A53RCR0			U(0x4)
 #define SRC_A53RCR1			U(0x8)
 #define SRC_OTG1PHY_SCR			U(0x20)
@@ -136,10 +145,6 @@
 
 #define MAX_CSU_NUM			U(64)
 
-#define OCRAM_S_BASE			U(0x00180000)
-#define OCRAM_S_SIZE			U(0x8000)
-#define OCRAM_S_LIMIT			(OCRAM_S_BASE + OCRAM_S_SIZE)
-
 #define COUNTER_FREQUENCY		8000000 /* 8MHz */
 
 #define IMX_WDOG_B_RESET
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index 3f75d954..3d81d976 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -39,7 +39,10 @@ BL31_SOURCES		+=	plat/imx/common/imx8_helpers.S			\
 
 ifneq (${BUILD_BL2},)
 BL2_SOURCES		+=	common/desc_image_load.c			\
+				plat/imx/common/imx_clock.c			\
+				plat/imx/common/imx8_clock.c			\
 				plat/imx/common/imx8_helpers.S			\
+				plat/imx/common/imx_io_mux.c			\
 				plat/imx/common/imx_uart_console.S		\
 				plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c	\
 				plat/imx/imx8m/imx8mm/gpc.c			\
@@ -87,6 +90,8 @@ LOAD_IMAGE_V2		:=	1
 BL2_AT_EL3		:=	1
 endif
 
+$(eval $(call add_define,SOC_IMX8M))
+
 ifneq (${SPD},none)
 $(eval $(call add_define,TEE_IMX8))
 endif