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| author | Achin Gupta <achin.gupta@arm.com> | 2014-06-17 16:59:13 +0100 |
|---|---|---|
| committer | Achin Gupta <achin.gupta@arm.com> | 2014-08-12 14:15:05 +0100 |
| commit | 196231425e14afa6ae8c7c2693a99ba206b8d91e (patch) | |
| tree | f0c2a3c874bce0f6da90a9595dd13774615dd1f2 | |
| parent | 8be9e39d9bab1e6191852caeec7cdbe78bac40ad (diff) | |
Add barriers to handle Secure Timer interrupts correctlyv0.4-Juno-0.6-rc1
This patch adds instruction synchronization barriers around the code which
handles the timer interrupt in the TSP. This ensures that the interrupt is not
acknowledged after or EOIed before it is deactivated at the peripheral.
Change-Id: Ie2f01f4f2e5c032ba61c7014d09ad86a3c5a0b97
| -rw-r--r-- | bl32/tsp/tsp_timer.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/bl32/tsp/tsp_timer.c b/bl32/tsp/tsp_timer.c index a7fdfdaf..e2b3e970 100644 --- a/bl32/tsp/tsp_timer.c +++ b/bl32/tsp/tsp_timer.c @@ -68,9 +68,14 @@ void tsp_generic_timer_handler(void) /* Ensure that the timer did assert the interrupt */ assert(get_cntp_ctl_istatus(read_cntps_ctl_el1())); - /* Disable the timer and reprogram it */ + /* + * Disable the timer and reprogram it. The barriers ensure that there is + * no reordering of instructions around the reprogramming code. + */ + isb(); write_cntps_ctl_el1(0); tsp_generic_timer_start(); + isb(); } /******************************************************************************* |