From d6dc67ba1b592b08ef1c0ff2e327d8c4d33aea55 Mon Sep 17 00:00:00 2001 From: Olivier Martin Date: Tue, 6 Aug 2013 10:59:19 +0000 Subject: ARM: Remove NSACR from the common code NSACR (Non-Secure Access Control Register) is AArch32 specific. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14522 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Include/Chipset/AArch64.h | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) (limited to 'ArmPkg/Include/Chipset/AArch64.h') diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h index 7f1f44ccc..8b6478600 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -34,15 +34,6 @@ // ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions #define AARCH64_PFR0_FP (0xF << 16) -// NSACR - Non-Secure Access Control Register definitions -#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF) -#define NSACR_NSD32DIS (1 << 14) -#define NSACR_NSASEDIS (1 << 15) -#define NSACR_PLE (1 << 16) -#define NSACR_TL (1 << 17) -#define NSACR_NS_SMP (1 << 18) -#define NSACR_RFR (1 << 19) - // SCR - Secure Configuration Register definitions #define SCR_NS (1 << 0) #define SCR_IRQ (1 << 1) @@ -176,4 +167,9 @@ GcdAttributeToPageAttribute ( IN UINT64 GcdAttributes ); +UINTN +ArmWriteCptr ( + IN UINT64 Cptr + ); + #endif // __AARCH64_H__ -- cgit v1.2.3