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2014-08-19ARM Packages: Corrected non-DOS line endingsRonald Cron
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15832 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-04ArmPkg/ArmSmcLib: Fixed SMC helper functionsOlivier Martin
The SMC helper functions were buggy as they were assuming that the values in x1-x7 registers were preserved across an SMC call, which is not the case. This patch fixes this issue. It also simplifies the code by providing only 1 version of the SMC helper function. We used to have 4 versions depending on the number of arguments. The problem with this approach was that the number of arguments also dictated the number of return values, which is completely unrelated. E.g. you can have an SMC call that takes 1 argument but returns 4 values. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15748 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-04ArmPkg/IndustryStandard/ArmStdSmc.h: Update Standard Service SMC CallsOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15747 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-29ArmPkg: Remove BasePeCoffLibHarry Liebel
ArmPkg contains unused and outdated code for runtime PE/COFF image relocation. - Use the version in MdePkg instead. - Remove references to this package from BeagleBoardPkg. ArmPkg/BasePeCoffLib was added to deal with MOVT instruction that was not part of the PE/COFF specification at that time. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15712 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-29ArmPkg/ArmLib.h: Fixed name of the argumentOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15711 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-29ArmPkg/CpuDxe: Fixed some typo issues in the AArch64 exception codeOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15710 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-29ArmPkg/AArch64.h: Added Exception Syndrome Register definitionsOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15709 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-29ArmPkg/AArch64: Added ARM_HCR_TSC definitionOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15708 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-29ArmPkg/ArmPkg.dec: Added the interrupt numbers for the Hypervisor and ↵Olivier Martin
Virtual Timers These numbers are mainly to reduce hardcoded numbers into the ACPI GTDT table. And also to match with the use of PcdArmArchTimerSecIntrNum and PcdArmArchTimerIntrNum into the GTDT ACPI Table. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15707 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-29ArmPkg/AArch64.h: Added SPSR and Timer register definitionsOlivier Martin
These timer register definitions are AArch64 specific. It is the reason why they are into this file and not into Chipset/ArmArchTimer.h. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15706 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-15ArmPkg/ArmLib.h: Removed GET_CORE_POS macroRonald Cron
The platform independant GET_CORE_POS has been replaced by the platform dependent function ArmPlatformGetCorePosition(). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15661 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-15ARM Packages: Force the SEC modules to be 2K aligned for AArch64Olivier Martin
The AArch64 Vector Table must be aligned on a 2K boundary. The FDF specification does not support 2K alignment but support 4K. A clear comment has been added to help integrator to understand why the assertion fails when porting to a new AArch64 platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15659 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-15ArmPkg/BdsLib: Removed PSCI discoverability from the Linux loaderOlivier Martin
Some platforms might decide to not support PSCI in their FDT-aware Linux system even if their firmware supports it. It is the responsibility of the platform engineer to provide the appropriate FDT. The PCD gArmTokenSpaceGuid.PcdArmPsciSupport is not required anymore. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15658 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-09ArmPkg/ArmLib: Improved ArmConfigureMmu PerformanceEugene Cohen
Data & Instruction Caches can be kept enabled while the new translation table is filled. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15647 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Returned the InterruptId in ArmGicAcknowledgeInterrupt()Olivier Martin
The InterruptId has a different width for GicV2 and GicV3 (respectively 10bit and 24bit). The function prototype has been changed to return this value to make the caller GIC architecture version independent. Otherwise, we would have need to expose a different mask to allow the caller to retrieve this value from the read register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15628 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Introduced support for GicV2 to ArmGicDxeOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15627 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Introduced support for GicV2 to ArmGicLibOlivier Martin
The support for GIcV2 was already existing. This change separate the GicV2 specific functions from the common Gic code (in preparation for GicV3 support). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15626 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Moved ArmGicDisableDistributor() to ArmGicLib.cOlivier Martin
The implementation is the same when we run in Secure or Non-Secure world. This change makes this function available for ArmGicSec.inf and ArmGicNonSec.inf. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15625 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Move RegisterInterruptSource() to the common GicDxe fileOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15624 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Move the installation and the registration to ↵Olivier Martin
InstallAndRegisterInterruptService() It will allow reusing the same code for GICv2 and GICv3 only drivers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15623 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Make the GicDxe driver depends on ArmGicLib (cont)Olivier Martin
... and also rename the ArmGicLib sources to use an explicit 'Lib' suffix. The renaming did not work well with SVN. Files were missing from the initial commit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15622 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Introduced helper functions to access the GIC controllerOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15621 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Make the GicDxe driver depends on ArmGicLibOlivier Martin
... and also rename the ArmGicLib sources to use an explicit 'Lib' suffix. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15620 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Move out the EndOfInterrupt from the interrupt acknowledgementOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15619 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/Drivers/ArmGic: Introduced ArmGicEndOfInterrupt()Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15618 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-01ArmPkg/BdsLib: Prevent memory leak whith TFTPOlivier Martin
In some case, the size of the downloaded TFTP image cannot be known. An arbitrary larger buffer is allocated to receive the image. We need to make sure when we free the buffer we free the size of the allocated buffer and not the size of the actual image. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15609 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-01ArmPkg/ArmCacheMaintenanceLib: Fixed comment (and coding style)Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15608 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-01ArmPkg/CpuDxe/ArmV6: Return error status when ExceptionHandlersStart is not ↵Olivier Martin
32-byte aligned The function should detect and return the error in non-debug builds when the ASSERT does nothing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15606 6f19259b-4bc3-4df7-8a09-765794883524
2014-06-20ARM Packages: Fixed missing braces (the warning was disabled by GCC)Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15578 6f19259b-4bc3-4df7-8a09-765794883524
2014-06-03ArmPkg/AsmMacroIoLib: Add support for ARM Compiler 6.00Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15554 6f19259b-4bc3-4df7-8a09-765794883524
2014-06-03ArmPkg/CpuDxe: Stack Pointer is not 8-bytes aligned in AArch32 interrupt ↵Olivier Martin
handling See section "2.1 The need to align SP to a multiple of 8 at conforming call sites" in "Advisory Note. SP must be 8-byte aligned on entry to AAPCS-conforming functions" Source: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0046b/IHI0046B_ABI_Advisory_1.pdf Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15553 6f19259b-4bc3-4df7-8a09-765794883524
2014-06-03ArmPkg: Added new ARM Processor Feature Register definitionsOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15552 6f19259b-4bc3-4df7-8a09-765794883524
2014-06-03ArmPkg/ArmLib: Drain Write Buffer before DCache maintenance operations.Olivier Martin
Cache maintenance operations by Set/Way require that the Write Buffer be drained before the cache is flushed. Without that, the flush can miss the most recent values written as they are still "pipelined". That has unfortunate consequences, especially where code is being copied to RAM. The fix is to add DSB instructions before the affected operations. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15551 6f19259b-4bc3-4df7-8a09-765794883524
2014-06-03ArmPkg/DefaultExceptionHandlerLib/Aarch64: Added friendly debug messageOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15549 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-19ArmPkg/BdsLib: Added support for TFTP servers without 'tsize' extensionOlivier Martin
Some TFTP servers do not have 'tsize' extension. This change allows to download files from TFTP servers that do not have this extension by trying to download the file into a pre-allocated buffer. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15539 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-14ArmPkg/BdsLib/AArch64: Added more useful error messages when loading LinuxBrendan Jackman
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <Brendan.JackMan@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15528 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-14ArmPkg/BdsLib: Fix allocating kernel buffer in TFTPBrendan Jackman
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <Brendan.JackMan@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15527 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-14ArmPkg/CpuDxe/AArch64: Fixed SyncCacheConfig() when first entry is in 3-levelOlivier Martin
If the first entry of the memory map is in the third level (case when the region at 0x0 is smaller than 4KB) then its descriptor type would be TT_TYPE_BLOCK_ENTRY_LEVEL3 (=0x3) which has the same value as TT_TYPE_TABLE_ENTRY (=0x3). The first condition in GetFirstPageAttribute() needed the table level to not mix these two descriptor types. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15526 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ArmPkg/BdsLib: Fix booting with partial pathsMark Salter
Boot entries created by efibootmgr may contain a partial device path to the EFI application to boot. These entries begin with a partition device path whereas entries created via ARM Boot Manager contain a full path to the EFI application. The ARM BDS code will fill in the missing parts of this partial device path as it does for removeable device paths. This allows the application to be loaded and started. However, the current code passes the original partial device path to gBS->LoadImage() and thus LoadImage is unable to find a DeviceHandle for the path. This means the application being booted cannot find the boot device from the Loaded Image Protocol structure. In the case of grub, this prevents the grub config file from being found. This patch fixes this by making sure the full path is propagated back to the caller of gBS->LoadImage() so that a proper DeviceHandle gets passed to the application being booted. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15518 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ARM Packages: Use .8byte instead of .dword for pointersBrendan Jackman
Clang doesn't recognise .dword Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15510 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ARM Packages: Use AND instead of BIC instruction with immediateBrendan Jackman
AARCH64 does not have a BIC-with-immediate instruction. GAS assembles it as a AND with the immediate inverted, but Clang's integrated assembler emits an error. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15509 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ArmPkg/CpuDxe/AArch64: use STUR instruction for signed offsetBrendan Jackman
The AARCH64 LDR and STR instructions only support signed offsets for post- and pre-indexed addressing. For normal signed offset addressing, the mnemonic is STUR. GNU As automatically assembles STR with signed offset as STUR, but Clang's integrated assembler doesn't. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15508 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ArmPkg/CpuDxe/AArch64/ExceptionSupport.S: Fix immediate syntaxBrendan Jackman
GNU as assembles instructions without the '#' before immediates. Clang doesn't. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15507 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ARM Packages: use GCC_ASM_EXPORT to export functionsBrendan Jackman
This ensures the .type directive is used to mark them as function symbols Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15506 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ArmLib/AArch64Support.S: remove export of unimplemented functionBrendan Jackman
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15505 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ARM Packages: Remove GCC filter for AARCH64 assembly filesBrendan Jackman
Some non-GCC toolchain might support the GNU assembly language. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15504 6f19259b-4bc3-4df7-8a09-765794883524
2014-04-24ArmPkg/ArmLib: Fixed AArch64 MMU code when a region overlaps 2 level-3 page ↵Olivier Martin
tables Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15483 6f19259b-4bc3-4df7-8a09-765794883524
2014-04-23ArmPkg/CpuDxe: Restore AArch64 system registers before returning from exceptionoliviermartin
Current EDK2 source code does actually trigger nested interrupted (even if the PI spec says interrupt should not be nested). This issue has highlighted the lack of restoring ELR_EL2/ELR_EL1 register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off: Vijayakumar Subbu <vsubbu@nvidia.com> Signed-off: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15481 6f19259b-4bc3-4df7-8a09-765794883524
2014-04-02ArmPkg: Fixed GetEnvironmentVariable() when the UEFI Variable did not existOlivier Martin
The function was allocating a buffer for the read value from the UEFI Variable. But it was returning the pointer of the default value when the variable was not present. It could cause error when the default value and the returned value were free when these addresses were the same (double FreePool on the same address). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15427 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-26ArmPkg/ArmCpuLib: Added A57 Errata 806969Olivier Martin
This rare errata only affects r0p0 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15400 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 22:23:50 +0000