diff options
319 files changed, 42578 insertions, 90 deletions
diff --git a/AppPkg/AppPkg.dsc b/AppPkg/AppPkg.dsc index d0aac2c50..491332a8d 100644 --- a/AppPkg/AppPkg.dsc +++ b/AppPkg/AppPkg.dsc @@ -82,7 +82,7 @@ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
FileHandleLib|ShellPkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf
- PathLib|ShellPkg/Library/BasePathLib/BasePathLib.inf
+ PathLib|MdeModulePkg/Library/BasePathLib/BasePathLib.inf
CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.c b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.c new file mode 100644 index 000000000..5151039c0 --- /dev/null +++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.c @@ -0,0 +1,49 @@ +/** @file + + Copyright (c) 2011-2012, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Library/ArmLib.h> +#include <Library/ArmCpuLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/PcdLib.h> + +#include <Chipset/ArmCortexA5.h> + +VOID +ArmCpuSetup ( + IN UINTN MpId + ) +{ + // Enable SWP instructions + ArmEnableSWPInstruction (); + + // Enable program flow prediction, if supported. + ArmEnableBranchPrediction (); + + // If MPCore then Enable the SCU + if (ArmIsMpCore()) { + // Turn on SMP coherency + ArmSetAuxCrBit (A5_FEATURE_SMP); + } + +} + + +VOID +ArmCpuSetupSmpNonSecure ( + IN UINTN MpId + ) +{ +} diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.inf b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.inf new file mode 100644 index 000000000..f2b42a2f4 --- /dev/null +++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.inf @@ -0,0 +1,38 @@ +#/* @file +# Copyright (c) 2011-2012, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = ArmCortexA5Lib + FILE_GUID = c9709ea3-1beb-4806-889a-8a1d5e5e1697 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmCpuLib + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + +[LibraryClasses] + ArmLib + IoLib + PcdLib + +[Sources.common] + ArmCortexA5Lib.c + +[FeaturePcd] + +[FixedPcd] + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore diff --git a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c index 4fc6a08b9..aed43cb3e 100644 --- a/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c +++ b/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.c @@ -49,9 +49,6 @@ ArmCpuSetup ( // If MPCore then Enable the SCU
if (ArmIsMpCore()) {
- // Signals the Cortex-A9 processor is taking part in coherency
- ArmSetAuxCrBit (A9_FEATURE_SMP);
-
ArmEnableScu ();
}
}
@@ -64,6 +61,8 @@ ArmCpuSetupSmpNonSecure ( {
INTN ScuBase;
+ ArmSetAuxCrBit (A9_FEATURE_SMP); + // Make the SCU accessible in Non Secure world
if (ArmPlatformIsPrimaryCore (MpId)) {
ScuBase = ArmGetScuBaseAddress();
diff --git a/ArmPkg/Include/Chipset/ArmCortexA5.h b/ArmPkg/Include/Chipset/ArmCortexA5.h new file mode 100644 index 000000000..cba2eb3d9 --- /dev/null +++ b/ArmPkg/Include/Chipset/ArmCortexA5.h @@ -0,0 +1,25 @@ +/** @file + + Copyright (c) 2012, ARM Limited. All rights reserved. + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __ARM_CORTEX_A5_H__ +#define __ARM_CORTEX_A5_H__ + +#include <Chipset/ArmV7.h> + +// +// Cortex A5 feature bit definitions +// +#define A5_FEATURE_SMP (1<<6) + +#endif diff --git a/ArmPkg/Library/BdsLib/Arm/BdsLinuxLoader.c b/ArmPkg/Library/BdsLib/Arm/BdsLinuxLoader.c index 0e8113cb3..d0eb075c6 100644 --- a/ArmPkg/Library/BdsLib/Arm/BdsLinuxLoader.c +++ b/ArmPkg/Library/BdsLib/Arm/BdsLinuxLoader.c @@ -26,8 +26,8 @@ PreparePlatformHardware ( //Note: Interrupts will be disabled by the GIC driver when ExitBootServices() will be called.
// Clean, invalidate, disable data cache
- ArmDisableDataCache();
ArmCleanInvalidateDataCache();
+ ArmDisableDataCache(); // Invalidate and disable the Instruction cache
ArmDisableInstructionCache ();
diff --git a/ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec b/ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec new file mode 100755 index 000000000..ac23bcd36 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec @@ -0,0 +1,40 @@ +#
+# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = ArmJunoPkg
+ PACKAGE_GUID = a1147a20-3144-4f8d-8295-b48311c8e4a4
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
+[Guids.common]
+ gArmJunoTokenSpaceGuid = { 0xa1147a20, 0x3144, 0x4f8d, { 0x82, 0x95, 0xb4, 0x83, 0x11, 0xc8, 0xe4, 0xa4 } }
+
+[PcdsFixedAtBuild.common]
+ gArmJunoTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT32|0x00000001
+ gArmJunoTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT32|0x00000002
+ gArmJunoTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000003
+
+ gArmJunoTokenSpaceGuid.PcdSynopsysUsbOhciBaseAddress|0x7FFB0000|UINT32|0x00000004
+ gArmJunoTokenSpaceGuid.PcdSynopsysUsbEhciBaseAddress|0x7FFC0000|UINT32|0x00000005
diff --git a/ArmPlatformPkg/ArmJunoPkg/ArmJuno.dsc b/ArmPlatformPkg/ArmJunoPkg/ArmJuno.dsc new file mode 100755 index 000000000..48a825adc --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/ArmJuno.dsc @@ -0,0 +1,237 @@ +#
+# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = ArmJuno
+ PLATFORM_GUID = ca0722fd-7d3d-45ea-948c-d62b2199807d
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/ArmJuno
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = ArmPlatformPkg/ArmJunoPkg/ArmJuno.fdf
+
+# On RTSM, most peripherals are VExpress Motherboard peripherals
+!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc
+
+[LibraryClasses.common]
+ ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
+ ArmPlatformLib|ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+
+ ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
+ NorFlashPlatformLib|ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/NorFlashJunoLib.inf
+ EfiResetSystemLib|ArmPlatformPkg/ArmJunoPkg/Library/ResetSystemLib/ResetSystemLib.inf
+
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+
+ # USB Requirements
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+[LibraryClasses.common.SEC]
+ PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+ ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+ LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+ HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+ PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+ MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+
+[BuildOptions]
+ GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmJunoPkg/Include
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
+
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+ # It could be set FALSE to save size.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+ gArmTokenSpaceGuid.PcdArmPsciSupport|TRUE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+[PcdsFixedAtBuild.common]
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Juno"
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"0.2"
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmJuno"
+
+ #
+ # NV Storage PCDs. Use base of 0x08000000 for NOR0
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0BFC0000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0BFD0000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0BFE0000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
+
+ # System Memory (2GB - 16MB of Trusted DRAM at the top of the 32bit address space)
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000
+
+ # Juno Dual-Cluster profile
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|6
+ gArmPlatformTokenSpaceGuid.PcdClusterCount|2
+
+ gArmTokenSpaceGuid.PcdVFPEnabled|1
+
+ #
+ # ARM PrimeCell
+ #
+
+ ## PL011 - Serial Terminal
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x7FF80000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gArmPlatformTokenSpaceGuid.PL011UartInteger|4
+ gArmPlatformTokenSpaceGuid.PL011UartFractional|0
+
+ ## PL031 RealTimeClock
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000
+
+ # LAN9118 Ethernet Driver
+ gEmbeddedTokenSpaceGuid.PcdLan9118DxeBaseAddress|0x18000000
+ gEmbeddedTokenSpaceGuid.PcdLan9118DefaultMacAddress|0x1215161822242628
+
+ #
+ # ARM General Interrupt Controller
+ #
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C010000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C02F000
+
+ # List of Device Paths that support BootMonFs
+ gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)"
+
+ #
+ # ARM OS Loader
+ #
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from NOR Flash"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/Image"
+ gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/juno"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,115200 earlyprintk=pl011,0x7ff80000 rootwait verbose debug root=/dev/sda2"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2
+
+ # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+
+ #
+ # ARM Architectural Timer Frequency
+ #
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
+ gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000
+
+[PcdsPatchableInModule]
+ # Console Resolution (Full HD)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1920
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|1080
+
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+ #
+ # PEI Phase modules
+ #
+ ArmPlatformPkg/PrePi/PeiMPCore.inf {
+ <LibraryClasses>
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf
+ }
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ EmbeddedPkg/SerialDxe/SerialDxe.inf
+
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ ArmPlatformPkg/ArmJunoPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ # Networking stack
+ EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf
+
+ #
+ # Usb Support
+ #
+ MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # Juno platform driver
+ #
+ ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ ArmPlatformPkg/Bds/Bds.inf
diff --git a/ArmPlatformPkg/ArmJunoPkg/ArmJuno.fdf b/ArmPlatformPkg/ArmJunoPkg/ArmJuno.fdf new file mode 100755 index 000000000..bf7918a9e --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/ArmJuno.fdf @@ -0,0 +1,307 @@ +#
+# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.BL32_AP_UEFI]
+BaseAddress = 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0xF0
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x000F0000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF EmbeddedPkg/SerialDxe/SerialDxe.inf
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ INF ArmPlatformPkg/ArmJunoPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf
+
+ # NOR Flash driver
+ INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
+
+ # Versatile Express FileSystem
+ INF ArmPlatformPkg/FileSystem/BootMonFs/BootMonFs.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatBinPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ # FV Filesystem^M
+ INF MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemDxe.inf
+
+ #
+ # Usb Support
+ #
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+
+ #
+ # Networking stack
+ #
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+ INF EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf
+
+ #
+ # UEFI applications
+ #
+ INF ShellBinPkg/UefiShell/UefiShell.inf
+
+ #
+ # Juno platform driver
+ #
+ INF ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF ArmPlatformPkg/Bds/Bds.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/PrePi/PeiMPCore.inf
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 1K $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c new file mode 100755 index 000000000..6555b0e1e --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.c @@ -0,0 +1,34 @@ +/** @file
+*
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+
+EFI_STATUS
+PciEmulationEntryPoint (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+ArmJunoEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = PciEmulationEntryPoint ();
+
+ return Status;
+}
diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf new file mode 100755 index 000000000..3c83e2ed5 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf @@ -0,0 +1,54 @@ +#
+# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmJunoDxe
+ FILE_GUID = 1484ebe8-2681-45f1-a2e5-12ecad893b62
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = ArmJunoEntryPoint
+
+[Sources.common]
+ ArmJunoDxe.c
+ PciEmulation.c
+ PciRootBridgeIo.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ DebugLib
+ DmaLib
+ IoLib
+ PcdLib
+ UefiBootServicesTableLib
+ UefiLib
+ UefiDriverEntryPoint
+
+[Protocols]
+ gEfiBlockIoProtocolGuid
+ gEfiPciIoProtocolGuid
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+
+ gArmJunoTokenSpaceGuid.PcdSynopsysUsbEhciBaseAddress
+ gArmJunoTokenSpaceGuid.PcdSynopsysUsbOhciBaseAddress
+
+[Depex]
+ TRUE
diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.c new file mode 100755 index 000000000..31f9fc083 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.c @@ -0,0 +1,486 @@ +/** @file
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PciEmulation.h"
+
+#define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ PCI_DEVICE_PATH PciDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_IO_DEVICE_PATH;
+
+typedef struct {
+ UINT32 Signature;
+ EFI_PCI_IO_DEVICE_PATH DevicePath;
+ EFI_PCI_IO_PROTOCOL PciIoProtocol;
+ PCI_TYPE00 *ConfigSpace;
+ PCI_ROOT_BRIDGE RootBridge;
+ UINTN Segment;
+} EFI_PCI_IO_PRIVATE_DATA;
+
+#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', 'o')
+#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR (a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)
+
+EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =
+{
+ {
+ { ACPI_DEVICE_PATH, ACPI_DP, {sizeof (ACPI_HID_DEVICE_PATH), 0} },
+ EISA_PNP_ID(0x0A03), // HID
+ 0 // UID
+ },
+ {
+ { HARDWARE_DEVICE_PATH, HW_PCI_DP, {sizeof (PCI_DEVICE_PATH), 0}},
+ 0,
+ 0
+ },
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, {sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}}
+};
+
+STATIC
+VOID
+ConfigureUSBHost (
+ VOID
+ )
+{
+}
+
+
+EFI_STATUS
+PciIoPollMem (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoPollIo (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoMemRead (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
+
+ return PciRootBridgeIoMemRead (&Private->RootBridge.Io,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ Private->ConfigSpace->Device.Bar[BarIndex] + Offset, //Fix me ConfigSpace
+ Count,
+ Buffer
+ );
+}
+
+EFI_STATUS
+PciIoMemWrite (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
+
+ return PciRootBridgeIoMemWrite (&Private->RootBridge.Io,
+ (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ Private->ConfigSpace->Device.Bar[BarIndex] + Offset, //Fix me ConfigSpace
+ Count,
+ Buffer
+ );
+}
+
+EFI_STATUS
+PciIoIoRead (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoIoWrite (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 BarIndex,
+ IN UINT64 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoPciRead (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT32 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
+ EFI_STATUS Status;
+
+ Status = PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,
+ Count,
+ TRUE,
+ (PTR)(UINTN)Buffer,
+ TRUE,
+ (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset) //Fix me ConfigSpace
+ );
+ return Status;
+}
+
+EFI_STATUS
+PciIoPciWrite (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT32 Offset,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
+
+ return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
+ Count,
+ TRUE,
+ (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset), //Fix me ConfigSpace
+ TRUE,
+ (PTR)(UINTN)Buffer
+ );
+}
+
+EFI_STATUS
+PciIoCopyMem (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
+ IN UINT8 DestBarIndex,
+ IN UINT64 DestOffset,
+ IN UINT8 SrcBarIndex,
+ IN UINT64 SrcOffset,
+ IN UINTN Count
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoMap (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ )
+{
+ DMA_MAP_OPERATION DmaOperation;
+
+ if (Operation == EfiPciIoOperationBusMasterRead) {
+ DmaOperation = MapOperationBusMasterRead;
+ } else if (Operation == EfiPciIoOperationBusMasterWrite) {
+ DmaOperation = MapOperationBusMasterWrite;
+ } else if (Operation == EfiPciIoOperationBusMasterCommonBuffer) {
+ DmaOperation = MapOperationBusMasterCommonBuffer;
+ } else {
+ return EFI_INVALID_PARAMETER;
+ }
+ return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);
+}
+
+EFI_STATUS
+PciIoUnmap (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN VOID *Mapping
+ )
+{
+ return DmaUnmap (Mapping);
+}
+
+EFI_STATUS
+PciIoAllocateBuffer (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
+ )
+{
+ if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {
+ // Check this
+ return EFI_UNSUPPORTED;
+ }
+
+ return DmaAllocateBuffer (MemoryType, Pages, HostAddress);
+}
+
+
+EFI_STATUS
+PciIoFreeBuffer (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ IN VOID *HostAddress
+ )
+{
+ return DmaFreeBuffer (Pages, HostAddress);
+}
+
+
+EFI_STATUS
+PciIoFlush (
+ IN EFI_PCI_IO_PROTOCOL *This
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciIoGetLocation (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ OUT UINTN *SegmentNumber,
+ OUT UINTN *BusNumber,
+ OUT UINTN *DeviceNumber,
+ OUT UINTN *FunctionNumber
+ )
+{
+ EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);
+
+ if (SegmentNumber != NULL) {
+ *SegmentNumber = Private->Segment;
+ }
+
+ if (BusNumber != NULL) {
+ *BusNumber = 0xff;
+ }
+
+ if (DeviceNumber != NULL) {
+ *DeviceNumber = 0;
+ }
+
+ if (FunctionNumber != NULL) {
+ *FunctionNumber = 0;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciIoAttributes (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
+ IN UINT64 Attributes,
+ OUT UINT64 *Result OPTIONAL
+ )
+{
+ switch (Operation) {
+ case EfiPciIoAttributeOperationGet:
+ case EfiPciIoAttributeOperationSupported:
+ if (Result == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ // We are not a real PCI device so just say things we kind of do
+ *Result = EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER | EFI_PCI_DEVICE_ENABLE;
+ break;
+
+ case EfiPciIoAttributeOperationSet:
+ case EfiPciIoAttributeOperationEnable:
+ case EfiPciIoAttributeOperationDisable:
+ // Since we are not a real PCI device no enable/set or disable operations exist.
+ return EFI_SUCCESS;
+
+ default:
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ };
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciIoGetBarAttributes (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT8 BarIndex,
+ OUT UINT64 *Supports, OPTIONAL
+ OUT VOID **Resources OPTIONAL
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+PciIoSetBarAttributes (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT64 Attributes,
+ IN UINT8 BarIndex,
+ IN OUT UINT64 *Offset,
+ IN OUT UINT64 *Length
+ )
+{
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_PCI_IO_PROTOCOL PciIoTemplate =
+{
+ PciIoPollMem,
+ PciIoPollIo,
+ { PciIoMemRead, PciIoMemWrite},
+ { PciIoIoRead, PciIoIoWrite },
+ { PciIoPciRead, PciIoPciWrite},
+ PciIoCopyMem,
+ PciIoMap,
+ PciIoUnmap,
+ PciIoAllocateBuffer,
+ PciIoFreeBuffer,
+ PciIoFlush,
+ PciIoGetLocation,
+ PciIoAttributes,
+ PciIoGetBarAttributes,
+ PciIoSetBarAttributes,
+ 0,
+ 0
+};
+
+EFI_STATUS
+PciInstallDevice (
+ IN UINTN DeviceId,
+ IN PHYSICAL_ADDRESS MemoryStart,
+ IN UINT64 MemorySize,
+ IN UINTN ClassCode1,
+ IN UINTN ClassCode2,
+ IN UINTN ClassCode3
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ EFI_PCI_IO_PRIVATE_DATA *Private;
+
+ // Configure USB host
+ ConfigureUSBHost ();
+
+ // Create a private structure
+ Private = AllocatePool (sizeof (EFI_PCI_IO_PRIVATE_DATA));
+ if (Private == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ return Status;
+ }
+
+ Private->Signature = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; // Fill in signature
+ Private->RootBridge.Signature = PCI_ROOT_BRIDGE_SIGNATURE; // Fake Root Bridge structure needs a signature too
+ Private->RootBridge.MemoryStart = MemoryStart; // Get the USB capability register base
+ Private->Segment = 0; // Default to segment zero
+
+ // Calculate the total size of the USB controller (OHCI + EHCI).
+ Private->RootBridge.MemorySize = MemorySize; //CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1));
+
+ // Create fake PCI config space: OHCI + EHCI
+ Private->ConfigSpace = AllocateZeroPool (sizeof (PCI_TYPE00));
+ if (Private->ConfigSpace == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ FreePool (Private);
+ return Status;
+ }
+
+ //
+ // Configure PCI config space: OHCI + EHCI
+ //
+ Private->ConfigSpace->Hdr.VendorId = 0x3530; //TODO: Define one
+ Private->ConfigSpace->Hdr.DeviceId = 0x3530; //TODO: Define one
+ Private->ConfigSpace->Hdr.ClassCode[0] = ClassCode1;
+ Private->ConfigSpace->Hdr.ClassCode[1] = ClassCode2;
+ Private->ConfigSpace->Hdr.ClassCode[2] = ClassCode3;
+ Private->ConfigSpace->Device.Bar[0] = MemoryStart;
+
+ Handle = NULL;
+
+ // Unique device path.
+ CopyMem (&Private->DevicePath, &PciIoDevicePathTemplate, sizeof (PciIoDevicePathTemplate));
+ Private->DevicePath.AcpiDevicePath.UID = 0;
+ Private->DevicePath.PciDevicePath.Device = DeviceId;
+
+ // Copy protocol structure
+ CopyMem (&Private->PciIoProtocol, &PciIoTemplate, sizeof (PciIoTemplate));
+
+ Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
+ &gEfiPciIoProtocolGuid, &Private->PciIoProtocol,
+ &gEfiDevicePathProtocolGuid, &Private->DevicePath,
+ NULL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces () failed.\n"));
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+PciEmulationEntryPoint (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ Status = PciInstallDevice (0, FixedPcdGet32 (PcdSynopsysUsbOhciBaseAddress), SIZE_64KB, PCI_IF_OHCI, PCI_CLASS_SERIAL_USB, PCI_CLASS_SERIAL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "PciEmulation: failed to install OHCI device.\n"));
+ }
+
+ Status = PciInstallDevice (1, FixedPcdGet32 (PcdSynopsysUsbEhciBaseAddress), SIZE_64KB, PCI_IF_EHCI, PCI_CLASS_SERIAL_USB, PCI_CLASS_SERIAL);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "PciEmulation: failed to install EHCI device.\n"));
+ }
+
+ return Status;
+}
diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.h b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.h new file mode 100755 index 000000000..1066839b8 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciEmulation.h @@ -0,0 +1,285 @@ +/** @file
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCI_ROOT_BRIDGE_H_
+#define _PCI_ROOT_BRIDGE_H_
+
+#include <PiDxe.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PciLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DmaLib.h>
+
+#include <Protocol/EmbeddedExternalDevice.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+
+#include <IndustryStandard/Pci23.h>
+#include <IndustryStandard/Acpi.h>
+
+#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL
+#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
+#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL
+
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+
+
+#define ACPI_CONFIG_IO 0
+#define ACPI_CONFIG_MMIO 1
+#define ACPI_CONFIG_BUS 2
+
+typedef struct {
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Desc[3];
+ EFI_ACPI_END_TAG_DESCRIPTOR EndDesc;
+} ACPI_CONFIG_INFO;
+
+
+#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('P', 'c', 'i', 'F')
+
+typedef struct {
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;
+ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath;
+
+ UINT8 StartBus;
+ UINT8 EndBus;
+ UINT16 Type;
+ UINT32 MemoryStart;
+ UINT32 MemorySize;
+ UINTN IoOffset;
+ UINT32 IoStart;
+ UINT32 IoSize;
+ UINT64 PciAttributes;
+
+ ACPI_CONFIG_INFO *Config;
+
+} PCI_ROOT_BRIDGE;
+
+
+#define INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE, Io, PCI_ROOT_BRIDGE_SIGNATURE)
+
+
+typedef union {
+ UINT8 volatile *Buffer;
+ UINT8 volatile *Ui8;
+ UINT16 volatile *Ui16;
+ UINT32 volatile *Ui32;
+ UINT64 volatile *Ui64;
+ UINTN volatile Ui;
+} PTR;
+
+
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPollMem (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPollIo (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINT64 Mask,
+ IN UINT64 Value,
+ IN UINT64 Delay,
+ OUT UINT64 *Result
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoIoRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 UserAddress,
+ IN UINTN Count,
+ IN OUT VOID *UserBuffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoIoWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 UserAddress,
+ IN UINTN Count,
+ IN OUT VOID *UserBuffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoCopyMem (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 DestAddress,
+ IN UINT64 SrcAddress,
+ IN UINTN Count
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPciRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPciWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMap (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
+ IN VOID *HostAddress,
+ IN OUT UINTN *NumberOfBytes,
+ OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
+ OUT VOID **Mapping
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoUnmap (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN VOID *Mapping
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoAllocateBuffer (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_ALLOCATE_TYPE Type,
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Pages,
+ OUT VOID **HostAddress,
+ IN UINT64 Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoFreeBuffer (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN UINTN Pages,
+ OUT VOID *HostAddress
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoFlush (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoGetAttributes (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ OUT UINT64 *Supported,
+ OUT UINT64 *Attributes
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoSetAttributes (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN UINT64 Attributes,
+ IN OUT UINT64 *ResourceBase,
+ IN OUT UINT64 *ResourceLength
+ );
+
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoConfiguration (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ OUT VOID **Resources
+ );
+
+//
+// Private Function Prototypes
+//
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemRW (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINTN Count,
+ IN BOOLEAN InStrideFlag,
+ IN PTR In,
+ IN BOOLEAN OutStrideFlag,
+ OUT PTR Out
+ );
+
+BOOLEAN
+PciIoMemAddressValid (
+ IN EFI_PCI_IO_PROTOCOL *This,
+ IN UINT64 Address
+ );
+
+EFI_STATUS
+EmulatePciIoForEhci (
+ INTN MvPciIfMaxIf
+ );
+
+#endif
diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciRootBridgeIo.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciRootBridgeIo.c new file mode 100755 index 000000000..2a4706501 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/PciRootBridgeIo.c @@ -0,0 +1,299 @@ +/** @file
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PciEmulation.h"
+
+BOOLEAN
+PciRootBridgeMemAddressValid (
+ IN PCI_ROOT_BRIDGE *Private,
+ IN UINT64 Address
+ )
+{
+ if ((Address >= Private->MemoryStart) && (Address < (Private->MemoryStart + Private->MemorySize))) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+
+EFI_STATUS
+PciRootBridgeIoMemRW (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINTN Count,
+ IN BOOLEAN InStrideFlag,
+ IN PTR In,
+ IN BOOLEAN OutStrideFlag,
+ OUT PTR Out
+ )
+{
+ UINTN Stride;
+ UINTN InStride;
+ UINTN OutStride;
+
+ Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ Stride = (UINTN)1 << Width;
+ InStride = InStrideFlag ? Stride : 0;
+ OutStride = OutStrideFlag ? Stride : 0;
+
+ //
+ // Loop for each iteration and move the data
+ //
+ switch (Width) {
+ case EfiPciWidthUint8:
+ for (;Count > 0; Count--, In.Buffer += InStride, Out.Buffer += OutStride) {
+ *In.Ui8 = *Out.Ui8;
+ }
+ break;
+ case EfiPciWidthUint16:
+ for (;Count > 0; Count--, In.Buffer += InStride, Out.Buffer += OutStride) {
+ *In.Ui16 = *Out.Ui16;
+ }
+ break;
+ case EfiPciWidthUint32:
+ for (;Count > 0; Count--, In.Buffer += InStride, Out.Buffer += OutStride) {
+ *In.Ui32 = *Out.Ui32;
+ }
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+PciRootBridgeIoPciRW (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN BOOLEAN Write,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 UserAddress,
+ IN UINTN Count,
+ IN OUT VOID *UserBuffer
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @param Address The base address of the memory operations.
+ @param Count The number of memory operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ PCI_ROOT_BRIDGE *Private;
+ UINTN AlignMask;
+ PTR In;
+ PTR Out;
+
+ if ( Buffer == NULL ) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+
+ if (!PciRootBridgeMemAddressValid (Private, Address)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ AlignMask = (1 << (Width & 0x03)) - 1;
+ if (Address & AlignMask) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ In.Buffer = Buffer;
+ Out.Buffer = (VOID *)(UINTN) Address;
+
+ switch (Width) {
+ case EfiPciWidthUint8:
+ case EfiPciWidthUint16:
+ case EfiPciWidthUint32:
+ case EfiPciWidthUint64:
+ return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);
+
+ case EfiPciWidthFifoUint8:
+ case EfiPciWidthFifoUint16:
+ case EfiPciWidthFifoUint32:
+ case EfiPciWidthFifoUint64:
+ return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);
+
+ case EfiPciWidthFillUint8:
+ case EfiPciWidthFillUint16:
+ case EfiPciWidthFillUint32:
+ case EfiPciWidthFillUint64:
+ return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);
+
+ default:
+ break;
+ }
+
+ return EFI_INVALID_PARAMETER;
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @param Address The base address of the memory operations.
+ @param Count The number of memory operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoMemWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ PCI_ROOT_BRIDGE *Private;
+ UINTN AlignMask;
+ PTR In;
+ PTR Out;
+
+ if ( Buffer == NULL ) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
+
+ if (!PciRootBridgeMemAddressValid (Private, Address)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ AlignMask = (1 << (Width & 0x03)) - 1;
+ if (Address & AlignMask) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ In.Buffer = (VOID *)(UINTN) Address;
+ Out.Buffer = Buffer;
+
+ switch (Width) {
+ case EfiPciWidthUint8:
+ case EfiPciWidthUint16:
+ case EfiPciWidthUint32:
+ case EfiPciWidthUint64:
+ return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out);
+
+ case EfiPciWidthFifoUint8:
+ case EfiPciWidthFifoUint16:
+ case EfiPciWidthFifoUint32:
+ case EfiPciWidthFifoUint64:
+ return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out);
+
+ case EfiPciWidthFillUint8:
+ case EfiPciWidthFillUint16:
+ case EfiPciWidthFillUint32:
+ case EfiPciWidthFillUint64:
+ return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out);
+
+ default:
+ break;
+ }
+
+ return EFI_INVALID_PARAMETER;
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @param Address The base address of the memory operations.
+ @param Count The number of memory operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPciRead (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return PciRootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);
+}
+
+/**
+ Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
+
+ @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
+ @param Width Signifies the width of the memory operations.
+ @param Address The base address of the memory operations.
+ @param Count The number of memory operations to perform.
+ @param Buffer For read operations, the destination buffer to store the results. For write
+ operations, the source buffer to write data from.
+
+ @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
+ @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
+ @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
+
+**/
+EFI_STATUS
+EFIAPI
+PciRootBridgeIoPciWrite (
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
+ IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
+ IN UINT64 Address,
+ IN UINTN Count,
+ IN OUT VOID *Buffer
+ )
+{
+ if (Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return PciRootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);
+}
diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c b/ArmPlatformPkg/ArmJunoPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c new file mode 100755 index 000000000..959a453d4 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c @@ -0,0 +1,354 @@ +/** @file
+*
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD
+* License which accompanies this distribution. The full text of the license
+* may be found at http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/ArmArchTimerLib.h>
+
+#include <Protocol/WatchdogTimer.h>
+#include <Protocol/HardwareInterrupt.h>
+
+#include <Drivers/GenericWatchdog.h>
+
+// The number of 100ns periods (the unit of time passed to these functions)
+// in a second
+#define TIME_UNITS_PER_SECOND 10000000
+
+// Tick frequency of the generic timer that is the basis of the generic watchdog
+UINTN mTimerFrequencyHz = 0;
+
+// In cases where the compare register was set manually, information about
+// how long the watchdog was asked to wait cannot be retrieved from hardware.
+// It is therefore stored here. 0 means the timer is not running.
+UINT64 mNumTimerTicks = 0;
+
+EFI_HARDWARE_INTERRUPT_PROTOCOL *mInterruptProtocol;
+
+EFI_STATUS
+WatchdogWriteOffsetRegister (
+ UINT32 Value
+ )
+{
+ return MmioWrite32 (GENERIC_WDOG_OFFSET_REG, Value);
+}
+
+EFI_STATUS
+WatchdogWriteCompareRegister (
+ UINT64 Value
+ )
+{
+ return MmioWrite64 (GENERIC_WDOG_COMPARE_VALUE_REG, Value);
+}
+
+EFI_STATUS
+WatchdogEnable (
+ VOID
+ )
+{
+ return MmioWrite32 (GENERIC_WDOG_CONTROL_STATUS_REG, GENERIC_WDOG_ENABLED);
+}
+
+EFI_STATUS
+WatchdogDisable (
+ VOID
+ )
+{
+ return MmioWrite32 (GENERIC_WDOG_CONTROL_STATUS_REG, GENERIC_WDOG_DISABLED);
+}
+
+/**
+ On exiting boot services we must make sure the Watchdog Timer
+ is stopped.
+**/
+VOID
+EFIAPI
+WatchdogExitBootServicesEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ WatchdogDisable ();
+ mNumTimerTicks = 0;
+}
+
+/*
+ This function is called when the watchdog's first signal (WS0) goes high.
+ It uses the ResetSystem Runtime Service to reset the board.
+*/
+VOID
+EFIAPI
+WatchdogInterruptHandler (
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ STATIC CONST CHAR16 ResetString[] = L"The generic watchdog timer ran out.";
+
+ WatchdogDisable ();
+
+ mInterruptProtocol->EndOfInterrupt (mInterruptProtocol, Source);
+
+ gRT->ResetSystem (
+ EfiResetCold,
+ EFI_TIMEOUT,
+ StrSize (ResetString),
+ &ResetString
+ );
+
+ // If we got here then the reset didn't work
+ ASSERT (FALSE);
+}
+
+/**
+ This function registers the handler NotifyFunction so it is called every time
+ the watchdog timer expires. It also passes the amount of time since the last
+ handler call to the NotifyFunction.
+ If NotifyFunction is not NULL and a handler is not already registered,
+ then the new handler is registered and EFI_SUCCESS is returned.
+ If NotifyFunction is NULL, and a handler is already registered,
+ then that handler is unregistered.
+ If an attempt is made to register a handler when a handler is already registered,
+ then EFI_ALREADY_STARTED is returned.
+ If an attempt is made to unregister a handler when a handler is not registered,
+ then EFI_INVALID_PARAMETER is returned.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param NotifyFunction The function to call when a timer interrupt fires.
+ This function executes at TPL_HIGH_LEVEL. The DXE
+ Core will register a handler for the timer interrupt,
+ so it can know how much time has passed. This
+ information is used to signal timer based events.
+ NULL will unregister the handler.
+
+ @retval EFI_SUCCESS The watchdog timer handler was registered.
+ @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
+ registered.
+ @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
+ previously registered.
+
+**/
+EFI_STATUS
+EFIAPI
+WatchdogRegisterHandler (
+ IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
+ IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction
+ )
+{
+ // ERROR: This function is not supported.
+ // The watchdog will reset the board
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ This function sets the amount of time to wait before firing the watchdog
+ timer to TimerPeriod 100 nS units. If TimerPeriod is 0, then the watchdog
+ timer is disabled.
+
+ @param This The EFI_WATCHDOG_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod The amount of time in 100 nS units to wait before the watchdog
+ timer is fired. If TimerPeriod is zero, then the watchdog
+ timer is disabled.
+
+ @retval EFI_SUCCESS The watchdog timer has been programmed to fire in Time
+ 100 nS units.
+ @retval EFI_DEVICE_ERROR A watchdog timer could not be programmed due to a device
+ error.
+
+**/
+EFI_STATUS
+EFIAPI
+WatchdogSetTimerPeriod (
+ IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
+ IN UINT64 TimerPeriod // In 100ns units
+ )
+{
+ UINTN TimerVal;
+ EFI_STATUS Status;
+
+ // if TimerPerdiod is 0, this is a request to stop the watchdog.
+ if (TimerPeriod == 0) {
+ mNumTimerTicks = 0;
+ return WatchdogDisable ();
+ }
+
+ // Work out how many timer ticks will equate to TimerPeriod
+ mNumTimerTicks = (mTimerFrequencyHz * TimerPeriod) / TIME_UNITS_PER_SECOND;
+
+ //
+ // If the number of required ticks is greater than the max number the
+ // watchdog's offset register (WOR) can hold, we need to manually compute and
+ // set the compare register (WCV)
+ //
+ if (mNumTimerTicks > MAX_UINT32) {
+ //
+ // We need to enable the watchdog *before* writing to the compare register,
+ // because enabling the watchdog causes an "explicit refresh", which
+ // clobbers the compare register (WCV). In order to make sure this doesn't
+ // trigger an interrupt, set the offset to max.
+ //
+ Status = WatchdogWriteOffsetRegister (MAX_UINT32);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ WatchdogEnable ();
+ TimerVal = ArmArchTimerGetTimerVal ();
+ Status = WatchdogWriteCompareRegister (TimerVal + mNumTimerTicks);
+ } else {
+ Status = WatchdogWriteOffsetRegister ((UINT32)mNumTimerTicks);
+ WatchdogEnable ();
+ }
+
+ return Status;
+}
+
+/**
+ This function retrieves the period of timer interrupts in 100 ns units,
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
+ returned, then the timer is currently disabled.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod A pointer to the timer period to retrieve in 100
+ ns units. If 0 is returned, then the timer is
+ currently disabled.
+
+
+ @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
+ @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+WatchdogGetTimerPeriod (
+ IN CONST EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
+ OUT UINT64 *TimerPeriod
+ )
+{
+ if (TimerPeriod == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *TimerPeriod = ((TIME_UNITS_PER_SECOND / mTimerFrequencyHz) * mNumTimerTicks);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Interface structure for the Watchdog Architectural Protocol.
+
+ @par Protocol Description:
+ This protocol provides a service to set the amount of time to wait
+ before firing the watchdog timer, and it also provides a service to
+ register a handler that is invoked when the watchdog timer fires.
+
+ @par When the watchdog timer fires, control will be passed to a handler
+ if one has been registered. If no handler has been registered,
+ or the registered handler returns, then the system will be
+ reset by calling the Runtime Service ResetSystem().
+
+ @param RegisterHandler
+ Registers a handler that will be called each time the
+ watchdogtimer interrupt fires. TimerPeriod defines the minimum
+ time between timer interrupts, so TimerPeriod will also
+ be the minimum time between calls to the registered
+ handler.
+ NOTE: If the watchdog resets the system in hardware, then
+ this function will not have any chance of executing.
+
+ @param SetTimerPeriod
+ Sets the period of the timer interrupt in 100 nS units.
+ This function is optional, and may return EFI_UNSUPPORTED.
+ If this function is supported, then the timer period will
+ be rounded up to the nearest supported timer period.
+
+ @param GetTimerPeriod
+ Retrieves the period of the timer interrupt in 100 nS units.
+
+**/
+EFI_WATCHDOG_TIMER_ARCH_PROTOCOL gWatchdogTimer = {
+ (EFI_WATCHDOG_TIMER_REGISTER_HANDLER) WatchdogRegisterHandler,
+ (EFI_WATCHDOG_TIMER_SET_TIMER_PERIOD) WatchdogSetTimerPeriod,
+ (EFI_WATCHDOG_TIMER_GET_TIMER_PERIOD) WatchdogGetTimerPeriod
+};
+
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+
+EFI_STATUS
+EFIAPI
+GenericWatchdogEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ //
+ // Make sure the Watchdog Timer Architectural Protocol has not been installed
+ // in the system yet.
+ // This will avoid conflicts with the universal watchdog
+ //
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiWatchdogTimerArchProtocolGuid);
+
+ mTimerFrequencyHz = ArmArchTimerGetTimerFreq ();
+ ASSERT (mTimerFrequencyHz != 0);
+
+ // Register for an ExitBootServicesEvent
+ Status = gBS->CreateEvent (
+ EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY,
+ WatchdogExitBootServicesEvent, NULL, &EfiExitBootServicesEvent
+ );
+ if (!EFI_ERROR (Status)) {
+ // Install interrupt handler
+ Status = gBS->LocateProtocol (
+ &gHardwareInterruptProtocolGuid,
+ NULL,
+ (VOID **)&mInterruptProtocol
+ );
+ if (!EFI_ERROR (Status)) {
+ Status = mInterruptProtocol->RegisterInterruptSource (
+ mInterruptProtocol,
+ FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
+ WatchdogInterruptHandler
+ );
+ if (!EFI_ERROR (Status)) {
+ // Install the Timer Architectural Protocol onto a new handle
+ Handle = NULL;
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gEfiWatchdogTimerArchProtocolGuid, &gWatchdogTimer,
+ NULL
+ );
+ }
+ }
+ }
+
+ if (EFI_ERROR (Status)) {
+ // The watchdog failed to initialize
+ ASSERT (FALSE);
+ }
+
+ mNumTimerTicks = 0;
+ WatchdogDisable ();
+
+ return Status;
+}
diff --git a/ArmPlatformPkg/ArmJunoPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf b/ArmPlatformPkg/ArmJunoPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf new file mode 100755 index 000000000..6cc84a1ea --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf @@ -0,0 +1,54 @@ +#
+# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x00010016
+ BASE_NAME = GenericWatchdogDxe
+ FILE_GUID = 0619f5c2-4858-4caa-a86a-73a21a18df6b
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = GenericWatchdogEntry
+
+[Sources.common]
+ GenericWatchdogDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ IoLib
+ PcdLib
+ UefiLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+ ArmLib
+
+[FixedPcd]
+ gArmJunoTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmJunoTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+ gArmJunoTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
+
+[Protocols]
+ gEfiWatchdogTimerArchProtocolGuid
+ gHardwareInterruptProtocolGuid
+
+[Depex]
+ gHardwareInterruptProtocolGuid
diff --git a/ArmPlatformPkg/ArmJunoPkg/Include/ArmJunoSmc.h b/ArmPlatformPkg/ArmJunoPkg/Include/ArmJunoSmc.h new file mode 100755 index 000000000..ee6ae5eb0 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Include/ArmJunoSmc.h @@ -0,0 +1,25 @@ +/** @file
+*
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __ARM_JUNO_SMC_H__
+#define __ARM_JUNO_SMC_H__
+
+// System Management Trusted Interface
+#define ARM_JUNO_ARM_FAST_SMC_SET_SYSTEM_POWER_STATE 0x81000000
+
+// SMC System Power States
+#define ARM_JUNO_ARM_FAST_SMC_SYSTEM_POWER_STATE_REBOOT 0x0
+#define ARM_JUNO_ARM_FAST_SMC_SYSTEM_POWER_STATE_SHUTDOWN 0x1
+
+#endif
diff --git a/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h b/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h new file mode 100755 index 000000000..be9b07b7a --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Include/ArmPlatform.h @@ -0,0 +1,51 @@ +/** @file
+*
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __ARM_JUNO_H__
+#define __ARM_JUNO_H__
+
+#include <VExpressMotherBoard.h>
+
+/***********************************************************************************
+// Platform Memory Map
+************************************************************************************/
+
+// Motherboard Peripheral and On-chip peripheral
+#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000
+
+// NOR Flash 0
+#define ARM_VE_SMB_NOR0_BASE 0x08000000
+#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
+
+// Off-Chip peripherals (USB, Ethernet, VRAM)
+#define ARM_VE_SMB_PERIPH_BASE 0x18000000
+#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB + SIZE_2MB)
+
+// On-Chip non-secure ROM
+#define ARM_JUNO_NON_SECURE_ROM_BASE 0x1F000000
+#define ARM_JUNO_NON_SECURE_ROM_SZ SIZE_16MB
+
+// On-Chip Peripherals
+#define ARM_JUNO_PERIPHERALS_BASE 0x20000000
+#define ARM_JUNO_PERIPHERALS_SZ 0x0E000000
+
+// On-Chip non-secure SRAM
+#define ARM_JUNO_NON_SECURE_SRAM_BASE 0x2E000000
+#define ARM_JUNO_NON_SECURE_SRAM_SZ SIZE_16MB
+
+// SOC peripherals (HDLCD, UART, I2C, I2S, USB, SMC-PL354, etc)
+#define ARM_JUNO_SOC_PERIPHERALS_BASE 0x7FF50000
+#define ARM_JUNO_SOC_PERIPHERALS_SZ (SIZE_64KB * 9)
+
+#endif
diff --git a/ArmPlatformPkg/ArmJunoPkg/Include/Drivers/GenericWatchdog.h b/ArmPlatformPkg/ArmJunoPkg/Include/Drivers/GenericWatchdog.h new file mode 100755 index 000000000..578fd1e85 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Include/Drivers/GenericWatchdog.h @@ -0,0 +1,29 @@ +/** @file
+*
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD
+* License which accompanies this distribution. The full text of the license
+* may be found at http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+#ifndef __GENERIC_WATCHDOG_H__
+#define __GENERIC_WATCHDOG_H__
+
+// Refresh Frame:
+#define GENERIC_WDOG_REFRESH_REG ((UINT32)FixedPcdGet32 (PcdGenericWatchdogRefreshBase) + 0x000)
+
+// Control Frame:
+#define GENERIC_WDOG_CONTROL_STATUS_REG ((UINT32)FixedPcdGet32 (PcdGenericWatchdogControlBase) + 0x000)
+#define GENERIC_WDOG_OFFSET_REG ((UINT32)FixedPcdGet32 (PcdGenericWatchdogControlBase) + 0x008)
+#define GENERIC_WDOG_COMPARE_VALUE_REG ((UINT32)FixedPcdGet32 (PcdGenericWatchdogControlBase) + 0x010)
+
+// Values of bit 0 of the Control/Status Register
+#define GENERIC_WDOG_ENABLED 1
+#define GENERIC_WDOG_DISABLED 0
+
+#endif // __GENERIC_WATCHDOG_H__
diff --git a/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJuno.c b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJuno.c new file mode 100755 index 000000000..3be26d3ed --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJuno.c @@ -0,0 +1,163 @@ +/** @file
+*
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+#include <ArmPlatform.h>
+
+ARM_CORE_INFO mJunoInfoTable[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 0, Core 1
+ 0x0, 0x1,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 1, Core 0
+ 0x1, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 1, Core 1
+ 0x1, 0x1,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 1, Core 2
+ 0x1, 0x2,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 1, Core 3
+ 0x1, 0x3,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ }
+};
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+ @return Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Initialize controllers that must setup in the normal world
+
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+ in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ return RETURN_SUCCESS;
+}
+
+/**
+ Initialize the system (or sometimes called permanent) memory
+
+ This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+ VOID
+ )
+{
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ // Only support one cluster
+ *CoreCount = sizeof(mJunoInfoTable) / sizeof(ARM_CORE_INFO);
+ *ArmCoreTable = mJunoInfoTable;
+ return EFI_SUCCESS;
+}
+
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &mArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof(gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
diff --git a/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoHelper.S b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoHelper.S new file mode 100755 index 000000000..73b249ca5 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoHelper.S @@ -0,0 +1,75 @@ +/** @file
+*
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
+
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)
+
+
+PrimaryCoreMpid: .word 0x0
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 2) + CoreId
+ASM_PFX(ArmPlatformGetCorePosition):
+ and x1, x0, #ARM_CORE_MASK
+ and x0, x0, #ARM_CLUSTER_MASK
+ add x0, x1, x0, LSR #7
+ ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
+ ldr x0, =PrimaryCoreMpid
+ ldrh w0, [x0]
+ ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_PFX(ArmPlatformIsPrimaryCore):
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, x1)
+ ldrh w1, [x1]
+ and x0, x0, x1
+
+ ldr x1, =PrimaryCoreMpid
+ ldrh w1, [x1]
+
+ cmp w0, w1
+ mov x0, #1
+ mov x1, #0
+ csel x0, x0, x1, eq
+ ret
+
+ASM_PFX(ArmPlatformPeiBootAction):
+ // The trusted firmware passes the primary CPU MPID through x0 register.
+ // Save it in a variable.
+ ldr x1, =PrimaryCoreMpid
+ str w0, [x1]
+ ret
+
diff --git a/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf new file mode 100755 index 000000000..b05d65890 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf @@ -0,0 +1,48 @@ +#
+# Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmJunoLib
+ FILE_GUID = 87c525cd-e1a2-469e-994c-c28cd0c7bd0d
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec
+
+[LibraryClasses]
+ IoLib
+ ArmLib
+ MemoryAllocationLib
+ SerialPortLib
+
+[Sources.common]
+ ArmJuno.c
+ ArmJunoMem.c
+ ArmJunoHelper.S | GCC
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
diff --git a/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoMem.c b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoMem.c new file mode 100755 index 000000000..426bba682 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoMem.c @@ -0,0 +1,118 @@ +/** @file
+*
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <ArmPlatform.h>
+
+// The total number of descriptors, including the final "end-of-table" descriptor.
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 11
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+ )
+{
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
+ UINTN Index = 0;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ ASSERT (VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
+ CacheAttributes = DDR_ATTRIBUTES_CACHED;
+ } else {
+ CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
+ }
+
+ // SMB CS0 - NOR0 Flash
+ VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;
+ VirtualMemoryTable[Index].Length = SIZE_256KB * 255;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ // Environment Variables region
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255);
+ VirtualMemoryTable[Index].Length = SIZE_64KB * 4;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // SMB CS2 & CS3 - Off-chip (motherboard) peripherals
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // Juno OnChip non-secure ROM
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_NON_SECURE_ROM_BASE;
+ VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_NON_SECURE_ROM_BASE;
+ VirtualMemoryTable[Index].Length = ARM_JUNO_NON_SECURE_ROM_SZ;
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+
+ // Juno OnChip peripherals
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_PERIPHERALS_BASE;
+ VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_PERIPHERALS_BASE;
+ VirtualMemoryTable[Index].Length = ARM_JUNO_PERIPHERALS_SZ;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // Juno OnChip non-secure SRAM
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_NON_SECURE_SRAM_BASE;
+ VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_NON_SECURE_SRAM_BASE;
+ VirtualMemoryTable[Index].Length = ARM_JUNO_NON_SECURE_SRAM_SZ;
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+
+ // Juno SOC peripherals
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_JUNO_SOC_PERIPHERALS_BASE;
+ VirtualMemoryTable[Index].VirtualBase = ARM_JUNO_SOC_PERIPHERALS_BASE;
+ VirtualMemoryTable[Index].Length = ARM_JUNO_SOC_PERIPHERALS_SZ;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // DDR
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/NorFlashJuno.c b/ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/NorFlashJuno.c new file mode 100755 index 000000000..525adeea0 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/NorFlashJuno.c @@ -0,0 +1,68 @@ +/** @file
+
+ Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ **/
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/NorFlashPlatformLib.h>
+#include <ArmPlatform.h>
+
+NOR_FLASH_DESCRIPTION mNorFlashDevices[] = {
+ {
+ ARM_VE_SMB_NOR0_BASE,
+ ARM_VE_SMB_NOR0_BASE,
+ SIZE_256KB * 255,
+ SIZE_256KB,
+ {0xE7223039, 0x5836, 0x41E1, {0xB5, 0x42, 0xD7, 0xEC, 0x73, 0x6C, 0x5E, 0x59}}
+ },
+ {
+ ARM_VE_SMB_NOR0_BASE,
+ ARM_VE_SMB_NOR0_BASE + SIZE_256KB * 255,
+ SIZE_64KB * 4,
+ SIZE_64KB,
+ {0x02118005, 0x9DA7, 0x443A, {0x92, 0xD5, 0x78, 0x1F, 0x02, 0x2A, 0xED, 0xBB}}
+ },
+};
+
+EFI_STATUS
+NorFlashPlatformInitialization (
+ VOID
+ )
+{
+ // Everything seems ok so far, so now we need to disable the platform-specific
+ // flash write protection for Versatile Express
+ if ((MmioRead32 (ARM_VE_SYS_FLASH) & 0x1) == 0) {
+ // Writing to NOR FLASH is disabled, so enable it
+ MmioWrite32 (ARM_VE_SYS_FLASH, 1);
+ DEBUG((DEBUG_BLKIO, "NorFlashPlatformInitialization: informational - Had to enable HSYS_FLASH flag.\n" ));
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+NorFlashPlatformGetDevices (
+ OUT NOR_FLASH_DESCRIPTION **NorFlashDevices,
+ OUT UINT32 *Count
+ )
+{
+ if ((NorFlashDevices == NULL) || (Count == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *NorFlashDevices = mNorFlashDevices;
+ *Count = sizeof (mNorFlashDevices) / sizeof (NOR_FLASH_DESCRIPTION);
+
+ return EFI_SUCCESS;
+}
diff --git a/ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/NorFlashJunoLib.inf b/ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/NorFlashJunoLib.inf new file mode 100755 index 000000000..6b1363508 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/NorFlashJunoLib.inf @@ -0,0 +1,32 @@ +#/** @file
+#
+# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = NorFlashJunoLib
+ FILE_GUID = 3eb6cbc4-ce95-11e2-b1bd-00241d0c1ba8
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NorFlashPlatformLib
+
+[Sources.common]
+ NorFlashJuno.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
diff --git a/ArmPlatformPkg/ArmJunoPkg/Library/ResetSystemLib/ResetSystemLib.c b/ArmPlatformPkg/ArmJunoPkg/Library/ResetSystemLib/ResetSystemLib.c new file mode 100755 index 000000000..2297318b2 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Library/ResetSystemLib/ResetSystemLib.c @@ -0,0 +1,87 @@ +/** @file
+*
+* Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+
+#include <Library/DebugLib.h>
+#include <Library/EfiResetSystemLib.h>
+#include <Library/ArmSmcLib.h>
+#include <ArmJunoSmc.h>
+
+/**
+ Resets the entire platform.
+
+ @param ResetType The type of reset to perform.
+ @param ResetStatus The status code for the reset.
+ @param DataSize The size, in bytes, of WatchdogData.
+ @param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or
+ EfiResetShutdown the data buffer starts with a Null-terminated
+ Unicode string, optionally followed by additional binary data.
+
+**/
+EFI_STATUS
+EFIAPI
+LibResetSystem (
+ IN EFI_RESET_TYPE ResetType,
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN CHAR16 *ResetData OPTIONAL
+ )
+{
+ UINTN Rx;
+ UINTN SystemState;
+
+ switch (ResetType) {
+ case EfiResetWarm:
+ case EfiResetCold:
+ // Map a warm reset into a cold reset
+ Rx = ARM_JUNO_ARM_FAST_SMC_SET_SYSTEM_POWER_STATE;
+ SystemState = ARM_JUNO_ARM_FAST_SMC_SYSTEM_POWER_STATE_REBOOT;
+ break;
+ case EfiResetShutdown:
+ Rx = ARM_JUNO_ARM_FAST_SMC_SET_SYSTEM_POWER_STATE;
+ SystemState = ARM_JUNO_ARM_FAST_SMC_SYSTEM_POWER_STATE_SHUTDOWN;
+ break;
+ default:
+ Rx = 0;
+ ASSERT(FALSE);
+ }
+
+ if (Rx != 0) {
+ ArmCallSmcArg1 (&Rx, &SystemState);
+ // We should never be here
+ while(1);
+ }
+
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Initialize any infrastructure required for LibResetSystem () to function.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+LibInitializeResetSystem (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/ArmPlatformPkg/ArmJunoPkg/Library/ResetSystemLib/ResetSystemLib.inf b/ArmPlatformPkg/ArmJunoPkg/Library/ResetSystemLib/ResetSystemLib.inf new file mode 100755 index 000000000..1cf9654f8 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Library/ResetSystemLib/ResetSystemLib.inf @@ -0,0 +1,32 @@ +#
+# Copyright (c) 2014, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmJunoResetSystemLib
+ FILE_GUID = b5b8e984-c8a2-4df4-b5ac-026204124aa0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = EfiResetSystemLib
+
+[Sources.common]
+ ResetSystemLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmJunoPkg/ArmJuno.dec
+
+[LibraryClasses]
+ DebugLib
+ ArmSmcLib
diff --git a/ArmPlatformPkg/ArmJunoPkg/Makefile b/ArmPlatformPkg/ArmJunoPkg/Makefile new file mode 100755 index 000000000..9548629f1 --- /dev/null +++ b/ArmPlatformPkg/ArmJunoPkg/Makefile @@ -0,0 +1,89 @@ +# +# Copyright (c) 2013-2014, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +# Define the following variables to specify an alternative toolchain to the one located in your PATH: +# - RVCT_TOOLS_PATH: for RVCT and RVCTLINUX toolchains +# - ARMGCC_TOOLS_PATH: for ARMGCC toolchain +# - ARMLINUXGCC_TOOLS_PATH: for ARMLINUXGCC + +EDK2_TOOLCHAIN ?= GCC48 +GCC48_AARCH64_PREFIX ?= aarch64-linux-gnu- +EDK2_ARCH ?= AARCH64 +EDK2_BUILD ?= DEBUG +EDK2_DSC = ArmPlatformPkg/ArmJunoPkg/ArmJuno.dsc +DEST_BIN_ROOT ?= + +ifeq ($(EDK2_DSC),"") + $(error The Makefile macro 'EDK2_DSC' must be defined with an EDK2 DSC file.) +endif + +ifeq ("$(OS)","Windows_NT") +export WORKSPACE?=$(PWD) +export EDK_TOOLS_PATH ?= $(WORKSPACE)\BaseTools +else +export WORKSPACE?=$(PWD) +endif + +# Define the destination of the Firmware Image Package (FIP) if not defined +ifndef JUNO_FIP + ifdef DEST_BIN_ROOT + JUNO_FIP=$(DEST_BIN_ROOT)/fip.bin + else + JUNO_FIP=fip.bin + endif +endif + +SHELL := /bin/bash +SILENT ?= @ +ECHO ?= echo +MAKE ?= make -i -k +RM ?= rm -f +CP ?= cp + +.PHONY: all clean + +EDK2_CONF = Conf/BuildEnv.sh Conf/build_rule.txt Conf/target.txt Conf/tools_def.txt + +all: $(EDK2_CONF) +ifeq ("$(OS)","Windows_NT") + build -a $(EDK2_ARCH) -p $(EDK2_DSC) -t $(EDK2_TOOLCHAIN) -b $(EDK2_BUILD) $(EDK2_MACROS) +else + . ./edksetup.sh; GCC47_AARCH64_PREFIX=$(GCC47_AARCH64_PREFIX) build -a $(EDK2_ARCH) -p $(EDK2_DSC) -t $(EDK2_TOOLCHAIN) -b $(EDK2_BUILD) $(EDK2_MACROS) +endif +ifeq ("$(OS)","Windows_NT") + $(SILENT)$(ECHO) "Warning: The UEFI Firmware must be added to the Firmware Image Package (FIP)." +else + $(SILENT)which fip_create ; \ + if [ $$? -ne 0 ]; then \ + $(ECHO) "Warning: 'fip_create' tool is not in the PATH. The UEFI binary will not be added in the Firmware Image Package (FIP)."; \ + else \ + fip_create --bl33 $(WORKSPACE)/Build/ArmJuno/$(EDK2_BUILD)_$(EDK2_TOOLCHAIN)/FV/BL32_AP_UEFI.fd --dump $(JUNO_FIP); \ + fi +endif + +$(EDK2_CONF): +ifeq ("$(OS)","Windows_NT") + copy $(EDK_TOOLS_PATH)\Conf\build_rule.template Conf\build_rule.txt + copy $(EDK_TOOLS_PATH)\Conf\FrameworkDatabase.template Conf\FrameworkDatabase.txt + copy $(EDK_TOOLS_PATH)\Conf\target.template Conf\target.txt + copy $(EDK_TOOLS_PATH)\Conf\tools_def.template Conf\tools_def.txt +else + . ./edksetup.sh; $(MAKE) -C BaseTools +endif + +clean: +ifeq ("$(OS)","Windows_NT") + build -a $(EDK2_ARCH) -p $(EDK2_DSC) -t $(EDK2_TOOLCHAIN) -b $(EDK2_BUILD) $(EDK2_MACROS) cleanall +else + . ./edksetup.sh; build -a $(EDK2_ARCH) -p $(EDK2_DSC) -t $(EDK2_TOOLCHAIN) -b $(EDK2_BUILD) $(EDK2_MACROS) cleanall; \ + rm -Rf $(EDK2_CONF) Conf/.cache +endif diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index 26f841808..d4f62619a 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -157,4 +157,3 @@ # and PcdCPUCoreSecSecondaryStackSize
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008
-
diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf new file mode 100644 index 000000000..46dc925fd --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf @@ -0,0 +1,51 @@ +## +# Component description file for PlatformAcpiTables module. +# +# ACPI table data and ASL sources required to boot the platform. +# +# Copyright (c) 2013, Linaro Ltd. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformAcpiTables + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD + MODULE_TYPE = USER_DEFINED + VERSION_STRING = 1.0 + +[Sources] + facp.asl + dsdt.asl + ssdt0.asl + bert.asl + ecdt.asl + facs.asl + gtdt.asl + hest.asl + apic.asl + mcfg.asl + mpst.asl + oem0.asl + slit.asl + spmi.asl + srat.asl + uefi.asl + cpep.asl + einj.asl + erst.asl + fpdt.asl + mchi.asl + msct.asl + pmtt.asl + +[Packages] + MdePkg/MdePkg.dec diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/apic.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/apic.asl new file mode 100644 index 000000000..81351c3cc --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/apic.asl @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [APIC] Multiple APIC Description Table (MADT) + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "APIC" +[0004] Table Length : 000000F6 +[0001] Revision : 03 +[0001] Checksum : B0 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110623 + +[0004] Local Apic Address : 2C000000 +[0004] Flags (decoded below) : 00000001 + PC-AT Compatibility : 0 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000000 /* Should be equal to FDT provided or CPU hardware ID */ +[0004] Processor UID : 00000000 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C000000 /* armv8 FVP Base GIC address */ + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000001 +[0004] Processor UID : 00000001 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C000000 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000002 +[0004] Processor UID : 00000002 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C000000 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000003 +[0004] Processor UID : 00000003 +[0004] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C000000 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000004 +[0004] Processor UID : 00000004 +[0004] Flags (decoded below) : 00000000 + Processor Enabled : 0 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C000000 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000005 +[0004] Processor UID : 00000005 +[0004] Flags (decoded below) : 00000000 + Processor Enabled : 0 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C000000 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000006 +[0004] Processor UID : 00000006 +[0004] Flags (decoded below) : 00000000 + Processor Enabled : 0 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C000000 + +[0001] Subtable Type : 0B [Generic Interrupt Controller] +[0001] Length : 28 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000007 +[0004] Processor UID : 00000007 +[0004] Flags (decoded below) : 00000000 + Processor Enabled : 0 +[0004] Parking Protocol Version : 00000000 +[0004] Performance Interrupt : 00000000 +[0008] Parked Address : 0000000000000000 +[0008] Base Address : 000000002C000000 + +[0001] Subtable Type : 0C [Generic Interrupt Distributor] +[0001] Length : 18 +[0002] Reserved : 0000 +[0004] Local GIC Hardware ID : 00000000 +[0008] Base Address : 000000002F000000 /* armv8 FVP Base GIC distributor base addr */ +[0004] Interrupt Base : 00000000 +[0004] Reserved : 00000000 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/bert.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/bert.asl new file mode 100644 index 000000000..1b9f3d61c --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/bert.asl @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [BERT] Boot Error Record Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "BERT" +[0004] Table Length : 00000030 +[0001] Revision : 01 +[0001] Checksum : 15 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000002 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Boot Error Region Length : 0x9D +[0008] Boot Error Region Address : 0xFFFF0008 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/cpep.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/cpep.asl new file mode 100644 index 000000000..c84d07d4e --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/cpep.asl @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [CPEP] Corrected Platform Error Polling Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "CPEP" +[0004] Table Length : 00000034 +[0001] Revision : 01 +[0001] Checksum : 0F +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0008] Reserved : 0000000000000000 + +[0001] Subtable Type : 00 +[0001] Length : 08 +[0001] Processor ID : 00 +[0001] Processor EID : 00 +[0004] Polling Interval : 00000000 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/dsdt.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/dsdt.asl new file mode 100644 index 000000000..43ac1706c --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/dsdt.asl @@ -0,0 +1,758 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [DSDT] Description of the armv8 VE Model + * + */ + +DefinitionBlock ( + "dsdt.aml", // output filename + "DSDT", // table signature + 2, // DSDT compliance revision + "LINARO", // OEM ID + "RTSMVEV8", // table ID + 0x00000004) // OEM revision +{ + Scope (\_SB) + { + Method (_OSC, 4, NotSerialized) + { + /* Platform-Wide OSPM Capabilities */ + If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48"))) + { + /* APEI support unconditionally */ + Return (Arg3) + } Else { + CreateDWordField (Arg3, Zero, CDW1) + /* Set invalid UUID error bit */ + Or (CDW1, 0x04, CDW1) + Return (Arg3) + } + } + + Device (HED) + { + Name (_HID, EisaId ("PNP0C33")) + Name (_UID, 0x00) + } + + Device (SCK0) + { + Name (_HID, "ACPI0004") + Name (_UID, 0x00) + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Device (PRC0) + { + Name (_HID, "ACPI0007") + Name (_UID, 0x00) + + /* CPU0 will be always present */ + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (MAT0, Buffer (0x28) + { + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* type, len, reserved, gic_id */ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, /* uid, flags */ + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* parking_version, performance_interrupt */ + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* parked_address */ + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* base_address */ + }) + + Name (MAT1, Buffer (0x28) + { + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + + Method (_MAT, 0, NotSerialized) + { + If (_STA()) + { + Return (MAT0) + } + Else + { + Return (MAT1) + } + } + } + + Device (PRC1) + { + Name (_HID, "ACPI0007") + Name (_UID, 0x01) + + Name (STA1, 0x0F) + Method (_STA, 0, NotSerialized) + { + Return (STA1) + } + + Method (_EJ0, 1, NotSerialized) + { + If (LEqual (STA1, 0x0F)) + { + Store (0x00, STA1) + } + } + + Name (MAT0, Buffer (0x28) + { + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + /* 0008 */ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + + Name (MAT1, Buffer (0x28) + { + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + /* 0008 */ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + + Method (_MAT, 0, NotSerialized) + { + If (_STA()) + { + Return (MAT0) + } + Else + { + Return (MAT1) + } + } + } + + Device (PRC2) + { + Name (_HID, "ACPI0007") + Name (_UID, 0x02) + + Name (STA2, 0x0F) + Method (_STA, 0, NotSerialized) + { + Return (STA2) + } + + Method (_EJ0, 1, NotSerialized) + { + If (LEqual (STA2, 0x0F)) + { + Store (0x00, STA2) + } + } + + Name (MAT0, Buffer (0x28) + { + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, + /* 0008 */ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + + Name (MAT1, Buffer (0x28) + { + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, + /* 0008 */ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + + Method (_MAT, 0, NotSerialized) + { + If (_STA()) + { + Return (MAT0) + } + Else + { + Return (MAT1) + } + } + } + + Device (PRC3) + { + Name (_HID, "ACPI0007") + Name (_UID, 0x03) + + Name (STA3, 0x0F) + Method (_STA, 0, NotSerialized) + { + Return (STA3) + } + + Method (_EJ0, 1, NotSerialized) + { + If (LEqual (STA3, 0x0F)) + { + Store (0x00, STA3) + } + } + + Name (MAT0, Buffer (0x28) + { + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, + /* 0008 */ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + + Name (MAT1, Buffer (0x28) + { + /* 0000 */ 0x0B, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, + /* 0008 */ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, + /* 0010 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0018 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 0020 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + }) + + Method (_MAT, 0, NotSerialized) + { + If (_STA()) + { + Return (MAT0) + } + Else + { + Return (MAT1) + } + } + } + } + + Device (PMU0) { + Name (_HID, "LNRO0007") + Name (_UID, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {92, 93, 94, 95} + }) + Return (RBUF) + } + } + + Device (SMB) { + Name (_HID, "ACPI0004") + Name (_UID, 0) + + Name (_CRS, ResourceTemplate () { + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x08000000, // Address Range Minimum (base address in FDT) + 0x0BFFFFFF, // Address Range Maximum (base + (len-1)) + 0x00000000, // Address Translation Offset + 0x04000000, // Address Length (len in FDT) + ,, , AddressRangeMemory, TypeStatic) + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x14000000, // Address Range Minimum (base address in FDT) + 0x17FFFFFF, // Address Range Maximum (base + (len-1)) + 0x00000000, // Address Translation Offset + 0x04000000, // Address Length (len in FDT) + ,, , AddressRangeMemory, TypeStatic) + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x18000000, // Address Range Minimum (base address in FDT) + 0x1BFFFFFF, // Address Range Maximum (base + (len-1)) + 0x00000000, // Address Translation Offset + 0x04000000, // Address Length (len in FDT) + ,, , AddressRangeMemory, TypeStatic) + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x1C000000, // Address Range Minimum (base address in FDT) + 0x1FFFFFFF, // Address Range Maximum (base + (len -1)) + 0x00000000, // Address Translation Offset + 0x04000000, // Address Length (len in FDT) + ,, , AddressRangeMemory, TypeStatic) + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x0C000000, // Address Range Minimum (base address in FDT) + 0x0FFFFFFF, // Address Range Maximum (base + (len-1)) + 0x00000000, // Address Translation Offset + 0x04000000, // Address Length (len in FDT) + ,, , AddressRangeMemory, TypeStatic) + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x10000000, // Address Range Minimum (base address in FDT) + 0x13FFFFFF, // Address Range Maximum (base + (len-1)) + 0x00000000, // Address Translation Offset + 0x04000000, // Address Length (len in FDT) + ,, , AddressRangeMemory, TypeStatic) + + }) + + Device (NET0) { + Name (_HID, "LNRO0003") + Name (_UID, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x1a000000, 0x00010000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {0x2F} + }) + Return (RBUF) + } + } + + Device (CLK0) { + Name (_HID, "LNRO0008") + Name (_UID, 0) + + Method (FREQ, 0x0, NotSerialized) { + Return (24000000) + } + } + + Device (CLK1) { + Name (_HID, "LNRO0008") + Name (_UID, 1) + + Method (FREQ, 0x0, NotSerialized) { + Return (1000000) + } + } + + Device (CLK2) { + Name (_HID, "LNRO0008") + Name (_UID, 2) + + Method (FREQ, 0x0, NotSerialized) { + Return (32768) + } + } + + Device (FPGA) { + Name (_HID, "ACPI0004") + Name (_UID, 0) + + Name (_CRS, ResourceTemplate () { + + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Address Space Granularity + 0x1C000000, // Address Range Minimum (base address in FDT) + 0x1C1FFFFF, // Address Range Maximum (base + (len-1)) + 0x00000000, // Address Translation Offset + 0x00200000, // Address Length (len in FDT) + ,, , AddressRangeMemory, TypeStatic) + }) + + Device (SREG) { + Name (_HID, "LNRO0009") + Name (_UID, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0x1c010000, 0x1000) + }) + Return (RBUF) + } + } + + Device (VIRT) { + Name (_HID, "LNRO0005") + Name (_UID, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0x1c130000, 0x1000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {0x4A} + }) + Return (RBUF) + } + } + } // End of FPGA + } // End SMB + + Method (DTGP, 5, NotSerialized) + { + If (LEqual (Arg0, Buffer (0x10) + { + /* UUID: a706b112-bf0b-48d2-9fa3-95591a3c4c06 */ + /* 0000 */ 0xa7, 0x06, 0xb1, 0x12, 0xbf, 0x0b, 0x48, 0xd2, + /* 0008 */ 0x9f, 0xa3, 0x95, 0x59, 0x1a, 0x3c, 0x4c, 0x06 + })) + { + If (LEqual (Arg1, 0x01)) { + If (LEqual (Arg2, 0x00)) { + Store (Buffer (0x01) + { + 0x03 + }, Arg4) + Return (0x01) + } + + If (LEqual (Arg2, 0x01)) { + Return (0x01) + } + } + } + + Store (Buffer (0x01) + { + 0x00 + }, Arg4) + + Return (0x00) + } + + Device (REG0) { + Name (_HID, "LNRO0019") + Name (_UID, 0) + + Method(_DSM, 4, NotSerialized) { + Store (Package (8) + { + "regulator-name", "3V3", + "regulator-min-microvolt", "3300000", + "regulator-max-microvolt", "3300000", + "regulator-always-on", "1", + }, Local0) + + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + + Return (Local0) + } + } + + Device (FLH0) { + Name (_HID, "LNRO0015") + Name (_UID, 0) + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x08000000, 0x04000000) + Memory32Fixed (ReadWrite, 0x0C000000, 0x04000000) + }) + Return (RBUF) + } + + Method(_DSM, 4, NotSerialized) { + Store (Package () + { + "bank-width", "4", + }, Local0) + + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + + Return (Local0) + } + } + + Device (AMBA) { + Name (_HID, "AMBA0000") + Name (_UID, 0) + + /* Define 'apb_pclk' as a default clock source since it is + common with devices below */ + + Method(_DSM, 4, NotSerialized) { + Store (Package (2) + { + "clock-name", "apb_pclk \\_SB.SMB.CLK0", + }, Local0) + + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + + Return (Local0) + } + + Device (SCT0) { + Name (_HID, "LNRO000C") + Name (_UID, 0) + Name (_ADR, 0x1c020000) /* SYSCTL */ + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x1c020000, 0x00001000) + }) + Return (RBUF) + } + Method(_DSM, 4, Serialized) { + Store (Package (4) + { + "clock-name", "refclk \\_SB.SMB.CLK2", + "clock-name", "timclk \\_SB.SMB.CLK1", + }, Local0) + + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + + Return (Local0) + } + } + + Device (AAC0) { + Name (_HID, "LNRO000D") + Name (_UID, 0) + Name (_ADR, 0x1c040000) /* AACI */ + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x1c040000, 0x00001000) + Interrupt (ResourceConsumer, Edge, ActiveBoth, + Exclusive, , , ) {43} + }) + Return (RBUF) + } + } + + Device (MMC0) { + Name (_HID, "LNRO000E") + Name (_UID, 0) + Name (_ADR, 0x1c050000) /* MMCI */ + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x1c050000, 0x00001000) + Interrupt (ResourceConsumer, Edge, ActiveBoth, + Exclusive, , , ) {41, 42} + }) + Return (RBUF) + } + Method(_DSM, 4, Serialized) { + Store (Package (2) + { + "clock-name", "MCLK \\_SB.SMB.CLK0", + }, Local0) + + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + + Return (Local0) + } + } + + Device (KMI0) { + Name (_HID, "LNRO000F") + Name (_UID, 0) + Name (_ADR, 0x1c060000) + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x1c060000, 0x00001000) + Interrupt (ResourceConsumer, Edge, ActiveBoth, + Exclusive, , , ) {44} + }) + Return (RBUF) + } + Method(_DSM, 4, Serialized) { + Store (Package (2) + { + "clock-name", "KMIREFCLK \\_SB.SMB.CLK0", + }, Local0) + + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + + Return (Local0) + } + } + + Device (KMI1) { + Name (_HID, "LNRO000F") + Name (_UID, 1) + Name (_ADR, 0x1c070000) + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x1c070000, 0x00001000) + Interrupt (ResourceConsumer, Edge, ActiveBoth, + Exclusive, , , ) {45} + }) + Return (RBUF) + } + Method(_DSM, 4, NotSerialized) { + Store (Package (2) + { + "clock-name", "KMIREFCLK \\_SB.SMB.CLK0", + }, Local0) + + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + + Return (Local0) + } + } + + Device (SER0) { + Name (_HID, "LNRO000A") + Name (_ADR, 0x1c090000) + Name (_UID, 0) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0x1c090000, 0x1000) + Interrupt (ResourceConsumer, Edge, ActiveBoth, Exclusive, , , ) {0x25} + }) + Return (RBUF) + } + } + + Device (SER1) { + Name (_HID, "LNRO000A") + Name (_ADR, 0x1c0a0000) + Name (_UID, 1) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0x1c0a0000, 0x1000) + Interrupt (ResourceConsumer, Edge, ActiveBoth, Exclusive, , , ) {0x26} + }) + Return (RBUF) + } + } + + Device (SER2) { + Name (_HID, "LNRO000A") + Name (_ADR, 0x1c0b0000) + Name (_UID, 2) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0x1c0b0000, 0x1000) + Interrupt (ResourceConsumer, Edge, ActiveBoth, Exclusive, , , ) {0x27} + }) + Return (RBUF) + } + } + + Device (SER3) { + Name (_HID, "LNRO000A") + Name (_ADR, 0x1c0c0000) + Name (_UID, 3) + + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, 0x1c0c0000, 0x1000) + Interrupt (ResourceConsumer, Edge, ActiveBoth, Exclusive, , , ) {0x28} + }) + Return (RBUF) + } + } + + Device (WDT0) { + Name (_HID, "LNRO0011") + Name (_UID, 0) + Name (_ADR, 0x1c0f0000) /* WDT */ + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x1c0f0000, 0x00001000) + Interrupt (ResourceConsumer, Edge, ActiveBoth, + Exclusive, , , ) {32} + }) + Return (RBUF) + } + } + + Device (TIM0) { + Name (_HID, "LNRO0012") + Name (_UID, 0) + Name (_ADR, 0x1c110000) /* TIMER01 */ + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x1c110000, 0x00001000) + Interrupt (ResourceConsumer, Edge, ActiveBoth, + Exclusive, , , ) {34} + }) + Return (RBUF) + } + } + + Device (TIM2) { + Name (_HID, "LNRO0012") + Name (_UID, 1) + Name (_ADR, 0x1c120000) /* TIMER23 */ + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x1c120000, 0x00001000) + Interrupt (ResourceConsumer, Edge, ActiveBoth, + Exclusive, , , ) {35} + }) + Return (RBUF) + } + } + + Device (RTC0) { + Name (_HID, "LNRO0013") + Name (_UID, 0) + Name (_ADR, 0x1c170000) /* RTC */ + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x1c170000, 0x00001000) + Interrupt (ResourceConsumer, Edge, ActiveBoth, + Exclusive, , , ) {36} + }) + Return (RBUF) + } + } + + Device (CLCD) { + Name (_HID, "LNRO0014") + Name (_UID, 0) + Name (_ADR, 0x1c1f0000) /* CLCD */ + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate () { + Memory32Fixed (ReadWrite, 0x1c1f0000, 0x00001000) + Interrupt (ResourceConsumer, Edge, ActiveBoth, + Exclusive, , , ) {46} + }) + Return (RBUF) + } + Method(_DSM, 4, Serialized) { + Store (Package (2) + { + "clock-name", "CCLDCLK \\_SB.SMB.CLK0", + }, Local0) + + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + + Return (Local0) + } + } + + } // End of AMBA + } +} diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/ecdt.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/ecdt.asl new file mode 100644 index 000000000..2eb0acf92 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/ecdt.asl @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [ECDT] Embedded Controller Boot Resources Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "ECDT" +[0004] Table Length : 00000042 +[0001] Revision : 01 +[0001] Checksum : 2D +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + + +[0012] Command/Status Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000066 + +[0012] Data Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000062 + +[0004] UID : 00000000 +[0001] GPE Number : 09 +[0001] Namepath : "" diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/einj.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/einj.asl new file mode 100644 index 000000000..63044fc25 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/einj.asl @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [EINJ] Error Injection Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "EINJ" +[0004] Table Length : 00000130 +[0001] Revision : 01 +[0001] Checksum : 09 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000003 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Injection Header Length : 00000030 +[0001] Flags : 00 +[0003] Reserved : 000000 +[0004] Injection Entry Count : 00000008 + +[0001] Action : 00 [Begin Operation] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0200 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 01 [Get Trigger Table] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0208 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 02 [Set Error Type] +[0001] Instruction : 02 [Write Register] +[0001] Flags (decoded below) : 01 + Preserve Register Bits : 1 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0210 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 03 [Get Error Type] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0218 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 04 [End Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 01 + Preserve Register Bits : 1 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0220 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 05 [Execute Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 01 + Preserve Register Bits : 1 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 10 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 02 [Word Access:16] +[0008] Address : 0xFFFF0228 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 06 [Check Busy Status] +[0001] Instruction : 01 [Read Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0230 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 07 [Get Command Status] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 01 + Preserve Register Bits : 1 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0238 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/erst.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/erst.asl new file mode 100644 index 000000000..2bf2aff26 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/erst.asl @@ -0,0 +1,305 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [ERST] Error Record Serialization Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "ERST" +[0004] Table Length : 00000230 +[0001] Revision : 01 +[0001] Checksum : AB +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000002 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Serialization Header Length : 00000030 +[0004] Reserved : 00000000 +[0004] Instruction Entry Count : 00000010 + +[0001] Action : 00 [Begin Write Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0100 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 01 [Begin Read Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0108 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 02 [Begin Clear Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0110 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 03 [End Operation] +[0001] Instruction : 04 [Noop] +[0001] Flags (decoded below) : 01 + Preserve Register Bits : 1 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0118 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 04 [Set Record Offset] +[0001] Instruction : 02 [Write Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0120 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 05 [Execute Operation] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0xFFFF0128 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 06 [Check Busy Status] +[0001] Instruction : 01 [Read Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0130 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 07 [Get Command Status] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0138 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 08 [Get Record Identifier] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0140 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 09 [Set Record Identifier] +[0001] Instruction : 02 [Write Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0148 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0A [Get Record Count] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0150 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0B [Begin Dummy Write] +[0001] Instruction : 03 [Write Register Value] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0158 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0C [Unused/Unknown Action] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0160 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0D [Get Error Address Range] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0168 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0E [Get Error Address Length] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0170 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF + +[0001] Action : 0F [Get Error Attributes] +[0001] Instruction : 00 [Read Register] +[0001] Flags (decoded below) : 00 + Preserve Register Bits : 0 +[0001] Reserved : 00 + +[0012] Register Region : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0178 + +[0008] Value : 0000000000000000 +[0008] Mask : FFFFFFFFFFFFFFFF diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/facp.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/facp.asl new file mode 100644 index 000000000..8d742f7ce --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/facp.asl @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [FACP] ACPI Table + * + */ + +[0004] Signature : "FACP" +[0004] Table Length : 0000010C +[0001] Revision : 05 +[0001] Checksum : 18 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20111123 + +[0004] FACS Address : 00000000 +[0004] DSDT Address : 00000010 +[0001] Model : 00 +[0001] PM Profile : 04 /* Enterprise Server */ +[0002] SCI Interrupt : 0000 +[0004] SMI Command Port : 00000000 +[0001] ACPI Enable Value : 00 +[0001] ACPI Disable Value : 00 +[0001] S4BIOS Command : 00 +[0001] P-State Control : 00 +[0004] PM1A Event Block Address : 00000001 +[0004] PM1B Event Block Address : 00000000 +[0004] PM1A Control Block Address : 00000001 +[0004] PM1B Control Block Address : 00000000 +[0004] PM2 Control Block Address : 00000001 +[0004] PM Timer Block Address : 00000001 +[0004] GPE0 Block Address : 00000001 +[0004] GPE1 Block Address : 00000000 +[0001] PM1 Event Block Length : 04 +[0001] PM1 Control Block Length : 02 +[0001] PM2 Control Block Length : 01 +[0001] PM Timer Block Length : 04 +[0001] GPE0 Block Length : 08 +[0001] GPE1 Block Length : 00 +[0001] GPE1 Base Offset : 00 +[0001] _CST Support : 00 +[0002] C2 Latency : 0000 +[0002] C3 Latency : 0000 +[0002] CPU Cache Size : 0000 +[0002] Cache Flush Stride : 0000 +[0001] Duty Cycle Offset : 00 +[0001] Duty Cycle Width : 00 +[0001] RTC Day Alarm Index : 00 +[0001] RTC Month Alarm Index : 00 +[0001] RTC Century Index : 00 +[0002] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[0001] Reserved : 00 +[0004] Flags (decoded below) : 00000000 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 1 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 1 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 1 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 1 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 1 + +[0012] Reset Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000001 + +[0001] Value to cause reset : 00 +[0003] Reserved : 000000 +[0008] FACS Address : 0000000000000000 +[0008] DSDT Address : 0000000000000010 +[0012] PM1A Event Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 20 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 02 [Word Access:16] +[0008] Address : 0000000000000001 + +[0012] PM1B Event Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM1A Control Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 10 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 02 [Word Access:16] +[0008] Address : 0000000000000001 + +[0012] PM1B Control Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0012] PM2 Control Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000001 + +[0012] PM Timer Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 20 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 03 [DWord Access:32] +[0008] Address : 0000000000000001 + +[0012] GPE0 Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 80 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000001 + +[0012] GPE1 Block : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 00 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + + +[0012] Sleep Control Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000 + +[0012] Sleep Status Register : [Generic Address Structure] +[0001] Space ID : 01 [SystemIO] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000 + diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/facs.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/facs.asl new file mode 100644 index 000000000..8dbb38b38 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/facs.asl @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [FACS] ACPI Table + * + */ + +[0004] Signature : "FACS" +[0004] Length : 00000040 +[0004] Hardware Signature : 00000000 +[0004] 32 Firmware Waking Vector : 00000000 +[0004] Global Lock : 00000000 +[0004] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[0008] 64 Firmware Waking Vector : 0000000000000000 +[0001] Version : 02 +[0003] Reserved : 000000 +[0004] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/fpdt.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/fpdt.asl new file mode 100644 index 000000000..53afa6676 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/fpdt.asl @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [FPDT] Firmware Performance Data Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "FPDT" +[0004] Table Length : 00000064 +[0001] Revision : 01 +[0001] Checksum : BD +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110804 + + +[0002] Subtable Type : 0000 +[0001] Length : 30 +[0001] Revision : 01 +[0004] Reserved : 00000000 +[0008] Reset End : 0000000000000000 +[0008] Load Image Start : 0000000000000000 +[0008] Start Image Start : 0000000000000000 +[0008] Exit Services Entry : 0000000000000000 +[0008] Exit Services Exit : 0000000000000000 + +[0002] Subtable Type : 0001 +[0001] Length : 10 +[0001] Revision : 01 +[0004] Reserved : 00000000 +[0008] S3PT Address : 0000000000000000 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl new file mode 100644 index 000000000..afaf9f41b --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/gtdt.asl @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * Hanjun Guo <hanjun.guo@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [GTDT] Generic Timer Description Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "GTDT" +[0004] Table Length : 00000050 +[0001] Revision : 01 +[0001] Checksum : F1 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110623 + +[0008] Timer Address : 0000000000000000 +[0004] Flags (decoded below) : 00000001 + Memory Present : 1 + +/* In RTSM model's dts file, the last cell of interrupts + * is 0xff01, it means its cpu mask is FF, and trigger type + * and flag is 1 = low-to-high edge triggered. + * + * so in ACPI the Trigger Mode is 1 - Edge triggered, and + * Polarity is 0 - Active high as ACPI spec describled. + * + * using direct mapping for hwirqs, it means that we using + * ID [16, 31] for PPI, not [0, 15] used in FDT. + */ +[0004] Secure PL1 Interrupt : 0000001d +[0004] SPL1 Flags (decoded below) : 00000001 + Trigger Mode : 1 + Polarity : 0 + +[0004] Non-Secure PL1 Interrupt : 0000001e +[0004] NSPL1 Flags (decoded below) : 00000001 + Trigger Mode : 1 + Polarity : 0 + +[0004] Virtual Timer Interrupt : 0000001b +[0004] VT Flags (decoded below) : 00000001 + Trigger Mode : 1 + Polarity : 0 + +[0004] Non-Secure PL2 Interrupt : 0000001a +[0004] NSPL2 Flags (decoded below) : 00000001 + Trigger Mode : 1 + Polarity : 0 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/hest.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/hest.asl new file mode 100644 index 000000000..70ba8f2f1 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/hest.asl @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [HEST] Hardware Error Source Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "HEST" +[0004] Table Length : 000001D4 +[0001] Revision : 01 +[0001] Checksum : 20 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000002 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Error Source Count : 00000001 + +[0002] Subtable Type : 0009 [Generic Hardware Error Source] +[0002] Source Id : 0002 +[0002] Related Source Id : FFFF +[0001] Reserved : 00 +[0001] Enabled : 01 +[0004] Records To Preallocate : 00000001 +[0004] Max Sections Per Record : 00000001 +[0004] Max Raw Data Length : 00001000 + +[0012] Error Status Address : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 40 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 04 [QWord Access:64] +[0008] Address : 0xFFFF0000 + +[0028] Notify : [Hardware Error Notification Structure] +[0001] Notify Type : 03 [SCI] +[0001] Notify Length : 1C +[0002] Configuration Write Enable : 0000 +[0004] PollInterval : 00000000 +[0004] Vector : 00000000 +[0004] Polling Threshold Value : 00000000 +[0004] Polling Threshold Window : 00000000 +[0004] Error Threshold Value : 00000000 +[0004] Error Threshold Window : 00000000 + +[0004] Error Status Block Length : 00001000 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/mcfg.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/mcfg.asl new file mode 100644 index 000000000..470637e07 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/mcfg.asl @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [MCFG] PCIe Memory Mapped Configuration Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "MCFG" +[0004] Table Length : 0000003C +[0001] Revision : 01 +[0001] Checksum : 19 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0008] Reserved : 0000000000000000 + +[0008] Base Address : 0000000000000000 +[0002] Segment Group Number : 0000 +[0001] Start Bus Number : 00 +[0001] End Bus Number : 00 +[0004] Reserved : 00000000 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/mchi.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/mchi.asl new file mode 100644 index 000000000..759ff193c --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/mchi.asl @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [MCHI] Management Controller Host Interface Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "MCHI" +[0004] Table Length : 00000045 +[0001] Revision : 01 +[0001] Checksum : E4 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 02000715 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0001] Interface Type : 01 +[0001] Protocol : 00 +[0008] Protocol Data : 0000000000000000 +[0001] Interrupt Type : 00 +[0001] Gpe : 00 +[0001] Pci Device Flag : 00 +[0004] Global Interrupt : 00000000 + +[0012] Control Register : [Generic Address Structure] +[0001] Space ID : 02 [PCI_Config] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 00 [Undefined/Legacy] +[0008] Address : 0000000000000000 + +[0001] Pci Segment : 00 +[0001] Pci Bus : 00 +[0001] Pci Device : 00 +[0001] Pci Function : 00 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/mpst.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/mpst.asl new file mode 100644 index 000000000..d8b0d8cf5 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/mpst.asl @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [MPST] Memory Power State Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "MPST" +[0004] Table Length : 000000B6 +[0001] Revision : 01 +[0001] Checksum : 77 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20120913 + +[0001] Channel ID : 00 +[0003] Reserved : 000000 +[0002] Power Node Count : 0002 +[0002] Reserved : 0000 + +[0001] Flags (decoded below) : 00 + Node Enabled : 0 + Power Managed : 0 + Hot Plug Capable : 0 +[0001] Reserved : 00 +[0002] Node ID : 0000 +[0004] Length : 00000000 +[0008] Range Address : 0000000000000000 +[0008] Range Length : 0000000000000000 +[0004] Num Power States : 00000002 +[0004] Num Physical Components : 00000003 + +[0001] Power State : 00 +[0001] InfoIndex : 00 + +[0001] Power State : 00 +[0001] InfoIndex : 00 + +[0002] Component Id : 0000 +[0002] Component Id : 0001 +[0002] Component Id : 0002 + +[0001] Flags (decoded below) : 00 + Node Enabled : 0 + Power Managed : 0 + Hot Plug Capable : 0 +[0001] Reserved : 00 +[0002] Node ID : 0000 +[0004] Length : 00000000 +[0008] Range Address : 0000000000000000 +[0008] Range Length : 0000000000000000 +[0004] Num Power States : 00000001 +[0004] Num Physical Components : 00000001 + +[0001] Power State : 00 +[0001] InfoIndex : 00 + +[0002] Component Id : 0000 + +[0002] Characteristics Count : 0002 +[0002] Reserved : 0000 + +[0001] Structure ID : 01 +[0001] Flags (decoded below) : 00 + Memory Preserved : 0 + Auto Entry : 0 + Auto Exit : 0 +[0002] Reserved : 0000 +[0004] Average Power : 00000000 +[0004] Power Saving : 00000000 +[0008] Exit Latency : 0000000000000000 +[0008] Reserved : 0000000000000000 + +[0001] Structure ID : 01 +[0001] Flags (decoded below) : 00 + Memory Preserved : 0 + Auto Entry : 0 + Auto Exit : 0 +[0002] Reserved : 0000 +[0004] Average Power : 00000000 +[0004] Power Saving : 00000000 +[0008] Exit Latency : 0000000000000000 +[0008] Reserved : 0000000000000000 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/msct.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/msct.asl new file mode 100644 index 000000000..aecde848b --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/msct.asl @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [MSCT] Maximum System Characteristics Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "MSCT" +[0004] Table Length : 00000090 +[0001] Revision : 01 +[0001] Checksum : B7 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Proximity Offset : 00000038 +[0004] Max Proximity Domains : 00000003 +[0004] Max Clock Domains : 00000000 +[0008] Max Physical Address : 00000FFFFFFFFFFF + +[0001] Revision : 01 +[0001] Length : 16 +[0004] Domain Range Start : 00000000 +[0004] Domain Range End : 00000003 +[0004] Processor Capacity : 00000010 +[0008] Memory Capacity : 0000004000000000 + +[0001] Revision : 01 +[0001] Length : 16 +[0004] Domain Range Start : 00000000 +[0004] Domain Range End : 00000000 +[0004] Processor Capacity : 00000000 +[0008] Memory Capacity : 0000000000000000 + +[0001] Revision : 01 +[0001] Length : 16 +[0004] Domain Range Start : 00000000 +[0004] Domain Range End : 00000000 +[0004] Processor Capacity : 00000000 +[0008] Memory Capacity : 0000000000000000 + +[0001] Revision : 01 +[0001] Length : 16 +[0004] Domain Range Start : 00000000 +[0004] Domain Range End : 00000000 +[0004] Processor Capacity : 00000000 +[0008] Memory Capacity : 0000000000000000 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/oem0.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/oem0.asl new file mode 100644 index 000000000..ae4fa2805 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/oem0.asl @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [OEMx] OEM Specific Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "OEM0" +[0004] Table Length : 00000024 +[0001] Revision : 01 +[0001] Checksum : 8B +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 0000000A +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/pmtt.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/pmtt.asl new file mode 100644 index 000000000..019116f17 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/pmtt.asl @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [PMTT] Platform Memory Topology Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "PMTT" +[0004] Table Length : 000000B4 +[0001] Revision : 01 +[0001] Checksum : 3A +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110826 + +[0004] Reserved : 00000000 + +[0001] Subtable Type : 00 [Socket] +[0001] Reserved : 00 +[0002] Length : 0080 +[0002] Flags (decoded below) : 0001 + Top-level Device : 1 + Physical Element : 0 + Memory Type : 0 +[0002] Reserved : 0000 +[0002] Socket ID : 0000 +[0002] Reserved : 0000 + +[0001] Subtable Type : 01 [Memory Controller] +[0001] Reserved : 00 +[0002] Length : 0054 +[0002] Flags (decoded below) : 0005 + Top-level Device : 1 + Physical Element : 0 + Memory Type : 1 +[0002] Reserved : 0000 +[0004] Read Latency : 00000000 +[0004] Write Latency : 00000000 +[0004] Read Bandwidth : 00000000 +[0004] Write Bandwidth : 00000000 +[0002] Access Width : 0000 +[0002] Alignment : 0000 +[0002] Reserved : 0000 +[0002] Domain Count : 0003 +[0004] Proximity Domain : 00000000 +[0004] Proximity Domain : 00000000 +[0004] Proximity Domain : 00000000 + +[0001] Subtable Type : 02 [Physical Component (DIMM)] +[0001] Reserved : 00 +[0002] Length : 0014 +[0002] Flags (decoded below) : 0002 + Top-level Device : 0 + Physical Element : 1 + Memory Type : 0 +[0002] Reserved : 0000 +[0002] Component ID : 0000 +[0002] Reserved : 0000 +[0004] Memory Size : 00000000 +[0004] Bios Handle : 00000000 + +[0001] Subtable Type : 02 [Physical Component (DIMM)] +[0001] Reserved : 00 +[0002] Length : 0014 +[0002] Flags (decoded below) : 0002 + Top-level Device : 0 + Physical Element : 1 + Memory Type : 0 +[0002] Reserved : 0000 +[0002] Component ID : 0000 +[0002] Reserved : 0000 +[0004] Memory Size : 00000000 +[0004] Bios Handle : 00000000 + +[0001] Subtable Type : 01 [Memory Controller] +[0001] Reserved : 00 +[0002] Length : 0020 +[0002] Flags (decoded below) : 0001 + Top-level Device : 1 + Physical Element : 0 + Memory Type : 0 +[0002] Reserved : 0000 +[0004] Read Latency : 00000000 +[0004] Write Latency : 00000000 +[0004] Read Bandwidth : 00000000 +[0004] Write Bandwidth : 00000000 +[0002] Access Width : 0000 +[0002] Alignment : 0000 +[0002] Reserved : 0000 +[0002] Domain Count : 0000 + +[0001] Subtable Type : 00 [Socket] +[0001] Reserved : 00 +[0002] Length : 000C +[0002] Flags (decoded below) : 0001 + Top-level Device : 1 + Physical Element : 0 + Memory Type : 0 +[0002] Reserved : 0000 +[0002] Socket ID : 0000 +[0002] Reserved : 0000 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/rsdp.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/rsdp.asl new file mode 100644 index 000000000..0595647cc --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/rsdp.asl @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [RSDP] ACPI Table + * + */ + +[0008] Signature : "RSD PTR " +[0001] Checksum : 43 +[0006] Oem ID : "LINARO" +[0001] Revision : 02 +[0004] RSDT Address : 00000000 +[0004] Length : 00000024 +[0008] XSDT Address : 0000000000000000 +[0001] Extended Checksum : DC +[0003] Reserved : 000000 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/slit.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/slit.asl new file mode 100644 index 000000000..3d62f3210 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/slit.asl @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [SLIT] System Locality Information Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "SLIT" +[0004] Table Length : 000001BC +[0001] Revision : 01 +[0001] Checksum : 00 +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20110316 + +[0008] Localities : 0000000000000014 +[0020] Locality 0 : 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 \ + 24 25 26 27 +[0020] Locality 1 : 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 \ + 23 24 25 26 +[0020] Locality 2 : 16 15 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 \ + 22 23 24 25 +[0020] Locality 3 : 17 16 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 \ + 21 22 23 24 +[0020] Locality 4 : 18 17 16 15 0A 10 16 17 18 19 1A 1B 1C 1D 1E 1F \ + 20 21 22 23 +[0020] Locality 5 : 19 18 17 16 10 0A 15 16 17 18 19 1A 1B 1C 1D 1E \ + 1F 20 21 22 +[0020] Locality 6 : 1A 19 18 17 16 15 0A 10 16 17 18 19 1A 1B 1C 1D \ + 1E 1F 20 21 +[0020] Locality 7 : 1B 1A 19 18 17 16 10 0A 15 16 17 18 19 1A 1B 1C \ + 1D 1E 1F 20 +[0020] Locality 8 : 1C 1B 1A 19 18 17 16 15 0A 10 16 17 18 19 1A 1B \ + 1C 1D 1E 1F +[0020] Locality 9 : 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 17 18 19 1A \ + 1B 1C 1D 1E +[0020] Locality 10 : 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 16 17 18 19 \ + 1A 1B 1C 1D +[0020] Locality 11 : 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 17 18 \ + 19 1A 1B 1C +[0020] Locality 12 : 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 16 17 \ + 18 19 1A 1B +[0020] Locality 13 : 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A 15 16 \ + 17 18 19 1A +[0020] Locality 14 : 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 0A 10 \ + 16 17 18 19 +[0020] Locality 15 : 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 10 0A \ + 15 16 17 18 +[0020] Locality 16 : 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 \ + 0A 10 16 17 +[0020] Locality 17 : 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 \ + 10 0A 15 16 +[0020] Locality 18 : 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 \ + 16 15 0A 10 +[0020] Locality 19 : 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 \ + 17 16 10 0A diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/spmi.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/spmi.asl new file mode 100644 index 000000000..11b1c994d --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/spmi.asl @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [SPMI] Server Platform Management Interface Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "SPMI" +[0004] Table Length : 00000041 +[0001] Revision : 04 +[0001] Checksum : ED +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000000 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0001] Interface Type : 00 +[0001] Reserved : 00 +[0002] IPMI Spec Version : 0000 +[0001] Interrupt Type : 00 +[0001] GPE Number : 00 +[0001] Reserved : 00 +[0001] PCI Device Flag : 00 +[0004] Interrupt : 00000000 + +[0012] IPMI Register : [Generic Address Structure] +[0001] Space ID : 00 [SystemMemory] +[0001] Bit Width : 08 +[0001] Bit Offset : 00 +[0001] Encoded Access Width : 01 [Byte Access:8] +[0008] Address : 0000000000000000 + +[0001] PCI Segment : 00 +[0001] PCI Bus : 00 +[0001] PCI Device : 00 +[0001] PCI Function : 00 +[0001] Reserved : 00 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/srat.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/srat.asl new file mode 100644 index 000000000..670bdd3cb --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/srat.asl @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [SRAT] System Resource Affinity Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "SRAT" +[0004] Table Length : 00000080 +[0001] Revision : 03 +[0001] Checksum : 5A +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0004] Table Revision : 00000001 +[0008] Reserved : 0000000000000000 + +[0001] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[0001] Length : 10 + +[0001] Proximity Domain Low(8) : 00 +[0001] Apic ID : 00 +[0004] Flags (decoded below) : 00000001 + Enabled : 1 +[0001] Local Sapic EID : 00 +[0003] Proximity Domain High(24) : 000000 +[0004] Reserved : 00000000 + +[0001] Subtable Type : 01 [Memory Affinity] +[0001] Length : 28 + +[0004] Proximity Domain : 00000000 +[0002] Reserved1 : 0000 +[0008] Base Address : 0000000000000000 +[0008] Address Length : 000000000009FC00 +[0004] Reserved2 : 00000000 +[0004] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0008] Reserved3 : 0000000000000000 + +[0001] Subtable Type : 02 [Processor Local x2APIC Affinity] +[0001] Length : 18 + +[0002] Reserved1 : 0000 +[0004] Proximity Domain : 00000000 +[0004] Apic ID : 00000000 +[0004] Flags (decoded below) : 00000001 + Enabled : 1 +[0004] Clock Domain : 00000000 +[0004] Reserved2 : 00000000 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/ssdt0.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/ssdt0.asl new file mode 100644 index 000000000..a5515acbe --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/ssdt0.asl @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [SSDT] Description of the armv8 VE Model + * + */ + +DefinitionBlock ( + "ssdt0.aml", // output filename + "SSDT", // table signature + 2, // SSDT compliance revision + "LINARO", // OEM ID + "RTSMVEV8", // table ID + 0x00000001) // OEM revision +{ +} diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/tpm2.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/tpm2.asl new file mode 100644 index 000000000..c88eb2c4b --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/tpm2.asl @@ -0,0 +1,22 @@ +/* + * Intel ACPI Component Architecture + * iASL Compiler/Disassembler version 20130117-64 [Jan 31 2013] + * Copyright (c) 2000 - 2013 Intel Corporation + * + * Template for [TPM2] ACPI Table + * Format: [ByteLength] FieldName : HexFieldValue + */ + +[0004] Signature : "TPM2" [Trusted Platform Module hardware interface table] +[0004] Table Length : 00000034 +[0001] Revision : 03 +[0001] Checksum : 42 +[0006] Oem ID : "INTEL " +[0008] Oem Table ID : "TEMPLATE" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20121114 + +[0004] Flags : 00000000 +[0008] Control Address : 0011223344556677 +[0004] Start Method : 00000001 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/uefi.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/uefi.asl new file mode 100644 index 000000000..a39aa52f5 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/uefi.asl @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [UEFI] UEFI Boot Optimization Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "UEFI" +[0004] Table Length : 00000036 +[0001] Revision : 01 +[0001] Checksum : 9B +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000001 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0016] UUID Identifier : 03020100-0504-0706-0809-0A0B0C0D0E0F +[0002] Data Offset : 0000 diff --git a/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/xsdt.asl b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/xsdt.asl new file mode 100644 index 000000000..b33f82e21 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/xsdt.asl @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2013, Al Stone <al.stone@linaro.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * + * NB: This License is also known as the "BSD 2-Clause License". + * + * + * [XSDT] Extended System Description Table + * Format: [ByteLength] FieldName : HexFieldValue + * + */ + +[0004] Signature : "XSDT" +[0004] Table Length : 00000064 +[0001] Revision : 01 +[0001] Checksum : 8B +[0006] Oem ID : "LINARO" +[0008] Oem Table ID : "RTSMVEV8" +[0004] Oem Revision : 00000014 +[0004] Asl Compiler ID : "INTL" +[0004] Asl Compiler Revision : 20100528 + +[0008] ACPI Table Address 0 : 0000000000000010 +[0008] ACPI Table Address 0 : 0000000000000020 +[0008] ACPI Table Address 0 : 0000000000000030 +[0008] ACPI Table Address 0 : 0000000000000040 +[0008] ACPI Table Address 0 : 0000000000000050 +[0008] ACPI Table Address 0 : 0000000000000060 +[0008] ACPI Table Address 0 : 0000000000000070 +[0008] ACPI Table Address 0 : 0000000000000080 +[0008] ACPI Table Address 0 : 0000000000000090 +[0008] ACPI Table Address 0 : 00000000000000A0 +[0008] ACPI Table Address 0 : 00000000000000B0 +[0008] ACPI Table Address 0 : 00000000000000C0 +[0008] ACPI Table Address 0 : 00000000000000D0 +[0008] ACPI Table Address 0 : 00000000000000E0 +[0008] ACPI Table Address 0 : 00000000000000F0 +[0008] ACPI Table Address 0 : 0000000000000100 +[0008] ACPI Table Address 0 : 0000000000000110 +[0008] ACPI Table Address 0 : 0000000000000120 +[0008] ACPI Table Address 0 : 0000000000000130 +[0008] ACPI Table Address 0 : 0000000000000140 diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15-A7.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15-A7.dsc index 56ae26aea..f5b7aa10f 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15-A7.dsc +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15-A7.dsc @@ -21,7 +21,11 @@ PLATFORM_GUID = 0b511920-978d-4b34-acc0-3d9f8e6f9d81
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
+!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY = $(EDK2_OUT_DIR) +!else OUTPUT_DIRECTORY = Build/ArmVExpress-CTA15-A7
+!endif SUPPORTED_ARCHITECTURES = ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
@@ -179,11 +183,12 @@ #
# Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
gArmTokenSpaceGuid.PcdArmMachineType|2272
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from NorFlash"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(1F15DA3C-37FF-4070-B471-BB4AF12A724A)/MemoryMapped(0x0,0xE000000,0xE800000)"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400 earlyprintk debug verbose"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2
- gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(1F15DA3C-37FF-4070-B471-BB4AF12A724A)/MemoryMapped(0x0,0x0E800000,0x0E803000)"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linaro image on SD card" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uImage" + gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uInitrd" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400n8 rootwait root=/dev/mmcblk0p2" + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2 + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/v2p-ca15-tc2.dtb" # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
# PL111 - CLCD
@@ -260,6 +265,11 @@ #
ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmHwDxe.inf
+ # SMBIOS Support
+
+ ArmPlatformPkg/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
#
# Filesystems
#
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15-A7.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15-A7.fdf index 9ba0a951e..31b3ac791 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15-A7.fdf +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15-A7.fdf @@ -109,6 +109,12 @@ READ_LOCK_STATUS = TRUE #
INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+
+ #
+ # SMBIOS Support
+ #
+ INF ArmPlatformPkg/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
#
# Filesystems
@@ -171,6 +177,9 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF ArmPlatformPkg/Bds/Bds.inf
+ # FV Filesystem
+ INF MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemDxe.inf
+
[FV.FVMAIN_COMPACT]
FvBaseAddress = 0xB0000000
FvForceRebase = TRUE
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15x2.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15x2.dsc new file mode 100644 index 000000000..c91146839 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15x2.dsc @@ -0,0 +1,302 @@ +#
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = ArmVExpressPkg-CTA15x2
+ PLATFORM_GUID = eb2bd5ff-2379-4a06-9c12-db905cdee9ea
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+!ifdef $(EDK2_OUT_DIR)
+ OUTPUT_DIRECTORY = $(EDK2_OUT_DIR)
+!else
+ OUTPUT_DIRECTORY = Build/ArmVExpress-CTA15x2
+!endif
+ SUPPORTED_ARCHITECTURES = ARM
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15x2.fdf
+!ifndef $(EDK2_ARMVE_STANDALONE)
+ DEFINE EDK2_ARMVE_STANDALONE=1
+!endif
+
+!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc
+
+[LibraryClasses.common]
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
+ ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressLib.inf
+
+ # ARM PL310 L2 Cache Driver
+ L2X0CacheLib|ArmPlatformPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf
+ # ARM PL354 SMC Driver
+ PL35xSmcLib|ArmPlatformPkg/Drivers/PL35xSmc/PL35xSmc.inf
+ # ARM PL341 DMC Driver
+ PL341DmcLib|ArmPlatformPkg/Drivers/PL34xDmc/PL341Dmc.inf
+ # ARM PL301 Axi Driver
+ PL301AxiLib|ArmPlatformPkg/Drivers/PL301Axi/PL301Axi.inf
+
+ ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
+ NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
+ #LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
+
+[LibraryClasses.common.SEC]
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
+ ArmPlatformSecLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressSecLib.inf
+
+ # Uncomment to turn on GDB stub in SEC.
+ #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
+
+[BuildOptions]
+ RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15x2
+
+ GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a15 -mfpu=neon -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15x2
+
+ XCODE:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15x2
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+!ifdef $(EDK2_ARMVE_STANDALONE)
+ gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE
+!else
+ gArmPlatformTokenSpaceGuid.PcdStandalone|FALSE
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
+ gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
+!endif
+
+!ifdef $(EDK2_SKIP_PEICORE)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
+ gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
+!endif
+
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+ # It could be set FALSE to save size.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+
+[PcdsFixedAtBuild.common]
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmVExpress"
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|2
+
+ #
+ # NV Storage PCDs. Use base of 0x00000000 for NOR1
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
+
+ gArmTokenSpaceGuid.PcdVFPEnabled|1
+
+ # Stacks for MPCores in Secure World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x2E009000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000
+
+ # Stacks for MPCores in Monitor Mode
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x2E008000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
+
+ # Stacks for MPCores in Normal World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000
+
+ # System Memory (1GB)
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000
+
+ #
+ # ARM Pcds
+ #
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
+
+ #
+ # ARM PrimeCell
+ #
+
+ ## SP804 Timer
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|1000000
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|34
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x1c110000
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x1c110020
+ gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x1c120020
+
+ ## SP805 Watchdog - Motherboard Watchdog
+ gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1C0F0000
+
+ ## PL011 - Serial Terminal
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400
+
+ ## PL031 RealTimeClock
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000
+
+ ## PL111 Versatile Express Motherboard controller
+ #gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000
+
+ ## PL180 MMC/SD card controller
+ gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048
+ gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000
+
+ #
+ # ARM PL390 General Interrupt Controller
+ #
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000
+
+ #
+ # ARM OS Loader
+ #
+ # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
+ gArmTokenSpaceGuid.PcdArmMachineType|2272
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linaro image on SD card"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uImage"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uInitrd"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400n8 rootwait root=/dev/mmcblk0p2"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2
+ gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/v2p-ca15-tc1.dtb"
+
+ # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()"
+
+ #
+ # ARM L2x0 PCDs
+ #
+ gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x1E00A000
+
+ #
+ # ARM Architectual Timer Frequency
+ #
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|600000000
+
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+ #
+ # SEC
+ #
+ ArmPlatformPkg/Sec/Sec.inf {
+ <LibraryClasses>
+ # Use the implementation which set the Secure bits
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+ }
+
+ #
+ # PEI Phase modules
+ #
+!ifdef $(EDK2_SKIP_PEICORE)
+ ArmPlatformPkg/PrePi/PeiMPCore.inf {
+ <LibraryClasses>
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
+ ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressLib.inf
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf
+ }
+!else
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {
+ <LibraryClasses>
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf
+ }
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ Nt32Pkg/BootModePei/BootModePei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+!endif
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ EmbeddedPkg/SerialDxe/SerialDxe.inf
+
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
+ ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf
+ #ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
+ ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+
+ #
+ # Filesystems
+ #
+ ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ #
+ # Multimedia Card Interface
+ #
+ EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+ ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ ArmPlatformPkg/Bds/Bds.inf
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15x2.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15x2.fdf new file mode 100644 index 000000000..0a5973a04 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15x2.fdf @@ -0,0 +1,326 @@ +#
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.ArmVExpress_EFI]
+!if $(EDK2_ARMVE_STANDALONE) == 1
+BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+!else
+BaseAddress = 0xA0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in remapped DRAM.
+!endif
+Size = 0x00280000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0x280
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00080000
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
+FV = FVMAIN_SEC
+
+0x00080000|0x00200000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FVMAIN_SEC]
+FvBaseAddress = 0x0
+FvForceRebase = TRUE
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF ArmPlatformPkg/Sec/Sec.inf
+
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF EmbeddedPkg/SerialDxe/SerialDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf
+ INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
+ #INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
+ INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+
+ #
+
+!if $(EDK2_ARMVE_STANDALONE) != 1
+ #
+ # Semi-hosting filesystem (Required the Hardware Debugger to be connected)
+ #
+ INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+!endif
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatBinPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # Multimedia Card Interface
+ #
+ INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+ INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellBinPkg/UefiShell/UefiShell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF ArmPlatformPkg/Bds/Bds.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+!if $(EDK2_SKIP_PEICORE) == 1
+ INF ArmPlatformPkg/PrePi/PeiMPCore.inf
+!else
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+!endif
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA5s.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA5s.dsc new file mode 100644 index 000000000..b81c7c914 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA5s.dsc @@ -0,0 +1,296 @@ +# +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = ArmVExpressPkg-CTA5s + PLATFORM_GUID = eb2bd5ff-2379-4a06-9c12-db905cdee9ea + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 +!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY = $(EDK2_OUT_DIR) +!else + OUTPUT_DIRECTORY = Build/ArmVExpress-CTA5s +!endif + SUPPORTED_ARCHITECTURES = ARM + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA5s.fdf +!ifndef $(EDK2_ARMVE_STANDALONE) + DEFINE EDK2_ARMVE_STANDALONE=1 +!endif + +!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA5Lib/ArmCortexA5Lib.inf + ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressLib.inf + + # ARM PL310 L2 Cache Driver + L2X0CacheLib|ArmPlatformPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf + # ARM PL354 SMC Driver + PL35xSmcLib|ArmPlatformPkg/Drivers/PL35xSmc/PL35xSmc.inf + # ARM PL341 DMC Driver + PL341DmcLib|ArmPlatformPkg/Drivers/PL34xDmc/PL341Dmc.inf + # ARM PL301 Axi Driver + PL301AxiLib|ArmPlatformPkg/Drivers/PL301Axi/PL301Axi.inf + + ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf + NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf + #LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf + +[LibraryClasses.common.SEC] + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf + ArmPlatformSecLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressSecLib.inf + + # Uncomment to turn on GDB stub in SEC. + #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf + +[BuildOptions] + RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A5 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA5s + + GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a5 -mfpu=neon -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA5s + + XCODE:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a5 -mfpu=neon -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA5s + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] +!ifdef $(EDK2_ARMVE_STANDALONE) + gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE +!else + gArmPlatformTokenSpaceGuid.PcdStandalone|FALSE + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE +!endif + +!ifdef $(EDK2_SKIP_PEICORE) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE +!endif + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + +[PcdsFixedAtBuild.common] + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express" + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmVExpress" + gArmPlatformTokenSpaceGuid.PcdCoreCount|2 + + # + # NV Storage PCDs. Use base of 0x0C000000 for NOR1 + # + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000 + + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + # Stacks for MPCores in Secure World + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x2E009000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000 + + # Stacks for MPCores in Monitor Mode + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x2E008000 + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100 + + # Stacks for MPCores in Normal World + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000 + + # System Memory (1GB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 + + # + # ARM Pcds + # + gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000 + + # + # ARM PrimeCell + # + + ## SP804 Timer + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|1000000 + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 # expressed in 100ns units, 100,000 x 100 ns = 10,000,000 ns = 10 ms + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|34 + gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x1c110000 + gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x1c110020 + gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x1c120020 + + ## SP805 Watchdog - Motherboard Watchdog + gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1C0F0000 + + ## PL011 - Serial Terminal + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400 + + ## PL031 RealTimeClock + gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000 + + ## PL111 Versatile Express Motherboard controller + #gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000 + + ## PL180 MMC/SD card controller + gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048 + gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000 + + # + # ARM PL390 General Interrupt Controller + # + gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000100 + + # + # ARM OS Loader + # + # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux: + gArmTokenSpaceGuid.PcdArmMachineType|2272 + gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linaro image on SD card" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uImage" + gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uInitrd" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400n8 rootwait root=/dev/mmcblk0p2" + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2 + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/v2p-ca5s.dtb" + + # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut) + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()" + + # + # ARM L2x0 PCDs + # + gArmTokenSpaceGuid.PcdL2x0ControllerBase|0x1E00A000 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + + # + # SEC + # + ArmPlatformPkg/Sec/Sec.inf { + <LibraryClasses> + # Use the implementation which set the Secure bits + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf + } + + # + # PEI Phase modules + # +!ifdef $(EDK2_SKIP_PEICORE) + ArmPlatformPkg/PrePi/PeiMPCore.inf { + <LibraryClasses> + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressLib.inf + ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf + } +!else + ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf { + <LibraryClasses> + ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf + } + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + ArmPlatformPkg/PlatformPei/PlatformPeim.inf + ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + ArmPkg/Drivers/CpuPei/CpuPei.inf + IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + Nt32Pkg/BootModePei/BootModePei.inf + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + <LibraryClasses> + NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + } +!endif + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf + } + + # + # Architectural Protocols + # + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + EmbeddedPkg/SerialDxe/SerialDxe.inf + + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf + ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf + #ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf + ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + + # + # Filesystems + # + ArmPkg/Filesystem/SemihostFs/SemihostFs.inf + + # + # Multimedia Card Interface + # + EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf + ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + ArmPlatformPkg/Bds/Bds.inf diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA5s.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA5s.fdf new file mode 100644 index 000000000..0e36aa3c7 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA5s.fdf @@ -0,0 +1,326 @@ +# +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.ArmVExpress_EFI] +!if $(EDK2_ARMVE_STANDALONE) == 1 +BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +!else +BaseAddress = 0xA0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in remapped DRAM. +!endif +Size = 0x00280000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0x280 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################ + +0x00000000|0x00080000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize +FV = FVMAIN_SEC + +0x00080000|0x00200000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FVMAIN_SEC] +FvBaseAddress = 0x0 +FvForceRebase = TRUE +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPlatformPkg/Sec/Sec.inf + + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + # + # Multiple Console IO support + # + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF EmbeddedPkg/SerialDxe/SerialDxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPlatformPkg/Drivers/SP804TimerDxe/SP804TimerDxe.inf + INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf + #INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf + INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf + + # + +!if $(EDK2_ARMVE_STANDALONE) != 1 + # + # Semi-hosting filesystem (Required the Hardware Debugger to be connected) + # + INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf +!endif + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # Multimedia Card Interface + # + INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf + INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf + + # + # UEFI application + # + INF ShellBinPkg/UefiShell/UefiShell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF ArmPlatformPkg/Bds/Bds.inf + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +!if $(EDK2_SKIP_PEICORE) == 1 + INF ArmPlatformPkg/PrePi/PeiMPCore.inf +!else + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf + INF ArmPkg/Drivers/CpuPei/CpuPei.inf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +!endif + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) { + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + UI STRING ="$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc index df1073d14..a422060e1 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.dsc @@ -32,8 +32,11 @@ !ifndef EDK2_ARMVE_STANDALONE
DEFINE EDK2_ARMVE_STANDALONE=1
!endif
-!if $(EDK2_ARMVE_STANDALONE) == 1
- OUTPUT_DIRECTORY = Build/ArmVExpress-CTA9x4-Standalone
+!ifndef $(EDK2_ARMVE_SINGLE_BINARY) + DEFINE EDK2_ARMVE_SINGLE_BINARY=1 +!endif +!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY = $(EDK2_OUT_DIR) !else
OUTPUT_DIRECTORY = Build/ArmVExpress-CTA9x4
!endif
@@ -177,9 +180,12 @@ #
# Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
gArmTokenSpaceGuid.PcdArmMachineType|2272
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"NorFlash"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(1F15DA3C-37FF-4070-B471-BB4AF12A724A)/MemoryMapped(0x0,0x46000000,0x46400000)"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootType|1
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linaro image on SD card" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uImage" + gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uInitrd" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400n8 rootwait root=/dev/mmcblk0p2" + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2 + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/v2p-ca9.dtb" # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf index 6a3e93329..fa4a4242a 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf @@ -24,6 +24,7 @@ #
################################################################################
+!ifndef $(EDK2_ARMVE_SINGLE_BINARY) [FD.Sec_ArmVExpress_EFI]
BaseAddress = 0x44000000|gArmTokenSpaceGuid.PcdSecureFdBaseAddress #The base address of the Secure FLASH Device.
Size = 0x00080000|gArmTokenSpaceGuid.PcdSecureFdSize #The size in bytes of the Secure FLASH Device
@@ -50,20 +51,32 @@ NumBlocks = 0x80 0x00000000|0x00080000
gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
FV = FVMAIN_SEC
-
+!endif [FD.ArmVExpress_EFI]
!if $(EDK2_ARMVE_STANDALONE) == 1
+!if $(EDK2_ARMVE_SINGLE_BINARY) == 1 +BaseAddress = 0x44000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash. +!else BaseAddress = 0x45000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+!endif !else
BaseAddress = 0x80000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in remapped DRAM.
!endif
+!if $(EDK2_ARMVE_SINGLE_BINARY) == 1 +Size = 0x00280000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device +!else Size = 0x00200000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+!endif ErasePolarity = 1
# This one is tricky, it must be: BlockSize * NumBlocks = Size
BlockSize = 0x00001000
+!if $(EDK2_ARMVE_SINGLE_BINARY) == 1 +NumBlocks = 0x280 +!else NumBlocks = 0x200
+!endif ################################################################################
#
@@ -80,11 +93,19 @@ NumBlocks = 0x200 # RegionType <FV, DATA, or FILE>
#
################################################################################
-
+!if $(EDK2_ARMVE_SINGLE_BINARY) == 1 +0x00000000|0x00080000 +gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize +FV = FVMAIN_SEC + +0x00080000|0x00200000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT +!else 0x00000000|0x00200000
gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
FV = FVMAIN_COMPACT
-
+!endif ################################################################################
#
@@ -240,6 +261,8 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF ArmPlatformPkg/Bds/Bds.inf
+ # FV Filesystem
+ INF MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemDxe.inf
[FV.FVMAIN_COMPACT]
FvAlignment = 8
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc index eebb96bad..094bc2616 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc @@ -21,7 +21,11 @@ PLATFORM_GUID = 0de70077-9b3b-43bf-ba38-0ea37d77141b
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
+!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY = $(EDK2_OUT_DIR) +!else OUTPUT_DIRECTORY = Build/ArmVExpress-FVP-AArch64
+!endif SUPPORTED_ARCHITECTURES = AARCH64
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
@@ -168,12 +172,17 @@ # ARM OS Loader
#
# Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from SemiHosting"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/Image"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/filesystem.cpio.gz"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0 earlyprintk=pl011,0x1c090000 debug user_debug=31 loglevel=9"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2
- gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/fdt.dtb"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linaro disk image on virtio" +!ifdef $(EDK2_USE_ANDROID_CONFIG) + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/kernel" + gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/ramdisk.img" + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/fvp-base-gicv2-psci.dtb" +!else + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/Image" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0 earlyprintk=pl011,0x1c090000 debug user_debug=31 loglevel=9 root=/dev/vda2" + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/fdt.dtb" +!endif + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2 # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
@@ -266,6 +275,13 @@ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ #
+ # ACPI Support
+ #
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf
+
ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
ArmPkg/Drivers/TimerDxe/TimerDxe.inf
@@ -305,3 +321,5 @@ #
MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
ArmPlatformPkg/Bds/Bds.inf
+
+ MdeModulePkg/Universal/Fdt/FdtTableDxe/FdtTableDxe.inf
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf index 97a776648..d17d35281 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf @@ -142,6 +142,12 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ # ACPI Support
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF RuleOverride=ACPITABLE ArmPlatformPkg/ArmVExpressPkg/AcpiTables/rtsm_ve-aemv8a/AcpiTables.inf
+
#
# Multiple Console IO support
#
@@ -186,6 +192,11 @@ READ_LOCK_STATUS = TRUE INF ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.inf
INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf
+!ifdef EDK2_ENABLE_SMSC_91X
+!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-networking.fdf.inc
+ INF EmbeddedPkg/Drivers/LAN91xDxe/LAN91xDxe.inf
+!endif
+
#
# UEFI application (Shell Embedded Boot Loader)
#
@@ -197,6 +208,21 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF ArmPlatformPkg/Bds/Bds.inf
+ # FV Filesystem
+ INF MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemDxe.inf
+
+ #
+ # Embedded device tree image
+ #
+ INF MdeModulePkg/Universal/Fdt/FdtTableDxe/FdtTableDxe.inf
+
+ FILE FREEFORM = PCD(gEfiMdeModulePkgTokenSpaceGuid.PcdFdtImage) {
+!ifdef ARM_FOUNDATION_FVP
+ SECTION RAW = ArmPlatformPkg/ArmVExpressPkg/fvp-foundation-gicv2-psci.dtb
+!else
+ SECTION RAW = ArmPlatformPkg/ArmVExpressPkg/fvp-base-gicv2-psci.dtb
+!endif
+ }
[FV.FVMAIN_COMPACT]
FvAlignment = 16
@@ -339,3 +365,8 @@ READ_LOCK_STATUS = TRUE UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ASL |.aml
+ }
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15.dsc index a2aa986f4..827688a90 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15.dsc +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15.dsc @@ -21,7 +21,11 @@ PLATFORM_GUID = 1665b5b1-529d-4ba1-bd51-c3c9b29a2274
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
+!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY = $(EDK2_OUT_DIR) +!else OUTPUT_DIRECTORY = Build/ArmVExpress-RTSM-A15
+!endif SUPPORTED_ARCHITECTURES = ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
@@ -81,23 +85,13 @@ #
# NV Storage PCDs. Use base of 0x0C000000 for NOR1
#
-!if $(EDK2_ARMVE_SUPPORT_QEMU) == 1
- # QEMU only models a single flash block size, so use larger blocks
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FF00000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00040000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FF40000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00040000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FF80000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00040000
-!else
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
-!endif
-
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0c000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00040000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0c040000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00040000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0c080000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00040000 + gArmTokenSpaceGuid.PcdVFPEnabled|1
# Stacks for MPCores in Secure World
@@ -156,10 +150,12 @@ #
# Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
gArmTokenSpaceGuid.PcdArmMachineType|2272
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"SemiHosting"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/zImage"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2
- gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/rtsm_ve-cortex_a15x1.dtb"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linaro image on SD card" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uImage" + gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uInitrd" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400n8 rootwait root=/dev/mmcblk0p2" + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2 + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/rtsm\\rtsm_ve-ca15x1.dtb" # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15.fdf index 3b56d0d54..b21bcb16d 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15.fdf +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15.fdf @@ -198,6 +198,8 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF ArmPlatformPkg/Bds/Bds.inf
+ # FV Filesystem
+ INF MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemDxe.inf
[FV.FVMAIN_COMPACT]
FvAlignment = 8
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15_MPCore.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15_MPCore.dsc index 77751b4a5..9a67c0bc4 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15_MPCore.dsc +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15_MPCore.dsc @@ -21,7 +21,11 @@ PLATFORM_GUID = 3a91a0f8-3af4-409d-a71d-a199dc134357
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
+!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY = $(EDK2_OUT_DIR) +!else OUTPUT_DIRECTORY = Build/ArmVExpress-RTSM-A15_MPCore
+!endif SUPPORTED_ARCHITECTURES = ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
@@ -83,22 +87,12 @@ #
# NV Storage PCDs. Use base of 0x0C000000 for NOR1
#
-!if $(EDK2_ARMVE_SUPPORT_QEMU) == 1
- # QEMU only models a single flash block size, so use larger blocks
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FF00000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00040000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FF40000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00040000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FF80000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00040000
-!else
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
-!endif
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0c000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00040000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0c040000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00040000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0c080000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00040000 gArmTokenSpaceGuid.PcdVFPEnabled|1
@@ -158,10 +152,12 @@ #
# Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
gArmTokenSpaceGuid.PcdArmMachineType|2272
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"SemiHosting"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/zImage"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2
- gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/rtsm_ve-cortex_a15x4.dtb"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linaro image on SD card" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uImage" + gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uInitrd" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400n8 rootwait root=/dev/mmcblk0p2" + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2 + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/rtsm\\rtsm_ve-ca15x4.dtb" # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
@@ -257,6 +253,12 @@ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+
+ #
+ # SMBIOS Support
+ #
+ ArmPlatformPkg/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
#
# Semi-hosting filesystem
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15_MPCore.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15_MPCore.fdf index 8f84f91da..c05bc01a8 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15_MPCore.fdf +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15_MPCore.fdf @@ -160,6 +160,12 @@ READ_LOCK_STATUS = TRUE INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
#
+ # SMBIOS Support
+ #
+ INF ArmPlatformPkg/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
+ #
# Semi-hosting filesystem
#
INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
@@ -198,6 +204,8 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF ArmPlatformPkg/Bds/Bds.inf
+ # FV Filesystem
+ INF MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemDxe.inf
[FV.FVMAIN_COMPACT]
FvAlignment = 8
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.dsc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.dsc index 3e397880e..4abb76207 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.dsc +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.dsc @@ -21,7 +21,11 @@ PLATFORM_GUID = e46039e0-5bb3-11e0-a9d6-0002a5d5c51b
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
+!ifdef $(EDK2_OUT_DIR) + OUTPUT_DIRECTORY = $(EDK2_OUT_DIR) +!else OUTPUT_DIRECTORY = Build/ArmVExpress-RTSM-A9x4
+!endif SUPPORTED_ARCHITECTURES = ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
@@ -159,10 +163,12 @@ #
# Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
gArmTokenSpaceGuid.PcdArmMachineType|2272
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"SemiHosting"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/zImage"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2
- gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/rtsm_ve-cortex_a9x4.dtb"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linaro image on SD card" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uImage" + gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uInitrd" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyAMA0,38400n8 rootwait root=/dev/mmcblk0p2" + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2 + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(09831032-6FA3-4484-AF4F-0A000A8D3A82)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/rtsm\\rtsm_ve-ca9x4.dtb" # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.fdf index 67aa6af1f..1dc3c8202 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.fdf +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.fdf @@ -184,6 +184,8 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF ArmPlatformPkg/Bds/Bds.inf
+ # FV Filesystem
+ INF MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemDxe.inf
[FV.FVMAIN_COMPACT]
FvAlignment = 8
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4-foundation.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4-foundation.fdf index 4e1c5a2ae..22a3a3089 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4-foundation.fdf +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4-foundation.fdf @@ -160,6 +160,11 @@ READ_LOCK_STATUS = TRUE INF ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.inf INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf +!ifdef EDK2_ENABLE_SMSC_91X
+!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-networking.fdf.inc
+ INF EmbeddedPkg/Drivers/LAN91xDxe/LAN91xDxe.inf
+!endif
+
# # UEFI application (Shell Embedded Boot Loader)
#
@@ -171,6 +176,8 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF ArmPlatformPkg/Bds/Bds.inf
+ # FV Filesystem
+ INF MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemDxe.inf
[FV.FVMAIN_COMPACT]
FvAlignment = 16
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4.fdf b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4.fdf index 83ceec4f6..845e8469e 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4.fdf +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-AEMv8Ax4.fdf @@ -181,6 +181,8 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
INF ArmPlatformPkg/Bds/Bds.inf
+ # FV Filesystem
+ INF MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemDxe.inf
[FV.FVMAIN_COMPACT]
FvAlignment = 16
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-networking.fdf.inc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-networking.fdf.inc new file mode 100644 index 000000000..f88392a3e --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-networking.fdf.inc @@ -0,0 +1,28 @@ +#
+# Copyright (c) 2012-2014, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions
+# of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+ #
+ # Networking stack
+ #
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
diff --git a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc index c61429e8d..5dddb56aa 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc +++ b/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc @@ -92,6 +92,7 @@ EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf
+ PathLib|MdeModulePkg/Library/BasePathLib/BasePathLib.inf
#
# Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
@@ -358,6 +359,11 @@ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()"
gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|10
+!ifdef EDK2_ENABLE_SMSC_91X
+ # Ethernet (SMSC 91C111)
+ gEmbeddedTokenSpaceGuid.PcdLan91xDxeBaseAddress|0x1A000000
+!endif
+
[Components.common]
# Versatile Express FileSystem
ArmPlatformPkg/FileSystem/BootMonFs/BootMonFs.inf
@@ -377,6 +383,10 @@ MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+!ifdef EDK2_ENABLE_SMSC_91X
+ # SMSC LAN 91C111
+ EmbeddedPkg/Drivers/LAN91xDxe/LAN91xDxe.inf
+!endif
# ISP1761 USB OTG Controller
EmbeddedPkg/Drivers/Isp1761UsbDxe/Isp1761UsbDxe.inf
@@ -387,3 +397,6 @@ EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf
EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf
ArmPlatformPkg/ArmVExpressPkg/ArmVExpressFastBootDxe/ArmVExpressFastBootDxe.inf
+
+ # FV Filesystem
+ MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemDxe.inf diff --git a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15x2/ArmPlatform.h b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15x2/ArmPlatform.h new file mode 100644 index 000000000..58e53fa3c --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15x2/ArmPlatform.h @@ -0,0 +1,96 @@ +/** @file
+* Header defining Versatile Express constants (Base addresses, sizes, flags)
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __ARM_VEXPRESS_H__
+#define __ARM_VEXPRESS_H__
+
+#include <Base.h>
+#include <VExpressMotherBoard.h>
+
+/***********************************************************************************
+// Platform Memory Map
+************************************************************************************/
+
+// Can be NOR0, NOR1, DRAM
+#define ARM_VE_REMAP_BASE 0x00000000
+#define ARM_VE_REMAP_SZ SIZE_64MB
+
+// Motherboard Peripheral and On-chip peripheral
+#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE 0x1C000000
+#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ SIZE_256MB
+#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000
+#define ARM_VE_CHIP_PERIPH_BASE 0x2A000000
+
+// SMC
+#define ARM_VE_SMC_BASE 0x08000000
+#define ARM_VE_SMC_SZ 0x1C000000
+
+// NOR Flash 1
+// There is typo in the reference manual for the Base address of NOR Flash 1
+#define ARM_VE_SMB_NOR0_BASE 0x08000000
+#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
+// NOR Flash 2
+#define ARM_VE_SMB_NOR1_BASE 0x0C000000
+#define ARM_VE_SMB_NOR1_SZ SIZE_64MB
+// SRAM
+#define ARM_VE_SMB_SRAM_BASE 0x2E000000
+#define ARM_VE_SMB_SRAM_SZ SIZE_64KB
+// USB, Ethernet, VRAM
+#define ARM_VE_SMB_PERIPH_BASE 0x18000000
+#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE
+#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB
+
+// DRAM
+#define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase)
+#define ARM_VE_DRAM_SZ PcdGet64 (PcdSystemMemorySize)
+
+// This can be any value since we only support motherboard PL111
+#define LCD_VRAM_CORE_TILE_BASE 0x84000000
+
+// On-chip peripherals (Snoop Control Unit etc...)
+#define ARM_VE_ON_CHIP_PERIPH_BASE 0x2C000000
+// Note: The TRM says not all the peripherals are implemented
+#define ARM_VE_ON_CHIP_PERIPH_SZ SIZE_256MB
+
+
+// External AXI between daughterboards (Logic Tile)
+#define ARM_VE_EXT_AXI_BASE 0x2E010000 // Not modelled
+#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */
+
+
+/***********************************************************************************
+ Core Tile memory-mapped Peripherals
+************************************************************************************/
+
+// SP810 Controller
+#undef SP810_CTRL_BASE
+#define SP810_CTRL_BASE 0x1C020000
+
+// PL111 Colour LCD Controller
+#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE
+#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
+// PL341 Dynamic Memory Controller Base
+#define ARM_VE_DMC_BASE (0x2B0A0000)
+
+// PL354 Static Memory Controller Base
+#define ARM_VE_SMC_CTRL_BASE (0x7FFD0000)
+
+// SCC Base
+#define ARM_VE_SCC_BASE (0x7FFF0000)
+
+// VRAM offset for the PL111 Colour LCD Controller on the motherboard
+#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)
+
+#endif
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA5s/ArmPlatform.h b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA5s/ArmPlatform.h new file mode 100644 index 000000000..990e407a8 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA5s/ArmPlatform.h @@ -0,0 +1,93 @@ +/** @file +* Header defining Versatile Express constants (Base addresses, sizes, flags) +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __ARM_VEXPRESS_H__ +#define __ARM_VEXPRESS_H__ + +#include <Base.h> +#include <VExpressMotherBoard.h> + +/*********************************************************************************** +// Platform Memory Map +************************************************************************************/ + +// Can be NOR0, NOR1, DRAM +#define ARM_VE_REMAP_BASE 0x00000000 +#define ARM_VE_REMAP_SZ SIZE_64MB + +// Motherboard Peripheral and On-chip peripheral +#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE 0x1C000000 +#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ SIZE_256MB +#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000 +#define ARM_VE_CHIP_PERIPH_BASE 0x2A000000 + +// SMC +#define ARM_VE_SMC_BASE 0x08000000 +#define ARM_VE_SMC_SZ 0x1C000000 + +// NOR Flash 1 +// There is typo in the reference manual for the Base address of NOR Flash 1 +#define ARM_VE_SMB_NOR0_BASE 0x08000000 +#define ARM_VE_SMB_NOR0_SZ SIZE_64MB +// NOR Flash 2 +#define ARM_VE_SMB_NOR1_BASE 0x0C000000 +#define ARM_VE_SMB_NOR1_SZ SIZE_64MB +// SRAM +#define ARM_VE_SMB_SRAM_BASE 0x2E000000 +#define ARM_VE_SMB_SRAM_SZ SIZE_64KB +// USB, Ethernet, VRAM +#define ARM_VE_SMB_PERIPH_BASE 0x18000000 +#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE +#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB + +// DRAM +#define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase) +#define ARM_VE_DRAM_SZ PcdGet64 (PcdSystemMemorySize) + +// This can be any value since we only support motherboard PL111 +#define LCD_VRAM_CORE_TILE_BASE 0x84000000 + +// On-chip peripherals (Snoop Control Unit etc...) +#define ARM_VE_ON_CHIP_PERIPH_BASE 0x2C000000 +// Note: The TRM says not all the peripherals are implemented +#define ARM_VE_ON_CHIP_PERIPH_SZ SIZE_256MB + + +// External AXI between daughterboards (Logic Tile) +#define ARM_VE_EXT_AXI_BASE 0x2E010000 // Not modelled +#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */ + + +/*********************************************************************************** + Core Tile memory-mapped Peripherals +************************************************************************************/ + +// SP810 Controller +#undef SP810_CTRL_BASE +#define SP810_CTRL_BASE 0x1C020000 + +// PL111 Colour LCD Controller +#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE +#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1 +// PL341 Dynamic Memory Controller Base +#define ARM_VE_DMC_BASE (0x2A150000) + +// PL354 Static Memory Controller Base +#define ARM_VE_SMC_CTRL_BASE (0x2A190000) + +// VRAM offset for the PL111 Colour LCD Controller on the motherboard +#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000) + +#endif diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressLib.inf new file mode 100644 index 000000000..017449e08 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressLib.inf @@ -0,0 +1,54 @@ +#/* @file
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = CTA15x2ArmVExpressLib
+ FILE_GUID = b16c63a0-f417-11df-b3af-0002a5d5c51b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+ IoLib
+ ArmLib
+ PL341DmcLib
+ PL301AxiLib
+ L2X0CacheLib
+ SerialPortLib
+
+[Sources.common]
+ CTA15x2.c
+ CTA15x2Mem.c
+ CTA15x2Helper.asm | RVCT
+ CTA15x2Helper.S | GCC
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable
+ gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressSecLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressSecLib.inf new file mode 100644 index 000000000..1b111a1a4 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/ArmVExpressSecLib.inf @@ -0,0 +1,53 @@ +#/* @file
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = CTA15x2ArmVExpressLib
+ FILE_GUID = b16c63a0-f417-11df-b3af-0002a5d5c51b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+ ArmLib
+ ArmPlatformSysConfigLib
+ IoLib
+ L2X0CacheLib
+ PL301AxiLib
+ PL341DmcLib
+ PL35xSmcLib
+ SerialPortLib
+
+[Sources.common]
+ CTA15x2Sec.c
+ CTA15x2.c
+ CTA15x2Boot.asm | RVCT
+ CTA15x2Boot.S | GCC
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable
+ gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2.c new file mode 100644 index 000000000..72881eeba --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2.c @@ -0,0 +1,161 @@ +#/* @file
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+
+#include <Drivers/PL341Dmc.h>
+#include <Drivers/PL301Axi.h>
+#include <Drivers/SP804Timer.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+#include <ArmPlatform.h>
+
+#define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1);
+
+ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA15x2[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 0, Core 1
+ 0x0, 0x1,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+};
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+ @return Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ if (MmioRead32(ARM_VE_SYS_FLAGS_NV_REG) == 0) {
+ return BOOT_WITH_FULL_CONFIGURATION;
+ } else {
+ return BOOT_ON_S2_RESUME;
+ }
+}
+
+/**
+ Initialize controllers that must setup in the normal world
+
+ This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
+ in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ if (!ArmPlatformIsPrimaryCore (MpId)) {
+ return RETURN_SUCCESS;
+ }
+
+ // Configure periodic timer (TIMER0) for 1MHz operation
+ MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
+ // Configure 1MHz clock
+ MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
+ // configure SP810 to use 1MHz clock and disable
+ MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
+ // Configure SP810 to use 1MHz clock and disable
+ MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Initialize the system (or sometimes called permanent) memory
+
+ This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+ VOID
+ )
+{
+ // Memory is initialised in CTA15x2Boot.S
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ *CoreCount = sizeof(mVersatileExpressMpCoreInfoCTA15x2) / sizeof(ARM_CORE_INFO);
+ *ArmCoreTable = mVersatileExpressMpCoreInfoCTA15x2;
+
+ return EFI_SUCCESS;
+}
+
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &mArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof(gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
+
+/**
+ Initialize the Secure peripherals and memory regions
+
+ If Trustzone is supported by your platform then this function makes the required initialization
+ of the secure peripherals and memory regions.
+
+**/
+VOID
+ArmPlatformSecTrustzoneInit (
+ IN UINTN MpId
+ )
+{
+}
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S new file mode 100644 index 000000000..c8a78a7bf --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.S @@ -0,0 +1,503 @@ +//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <Library/ArmPlatformLib.h>
+#include <Drivers/PL35xSmc.h>
+#include <Drivers/PL341Dmc.h>
+#include <ArmPlatform.h>
+#include <AutoGen.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(ArmPlatformSecBootAction)
+GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)
+GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)
+
+/**
+ Call at the beginning of the platform boot up
+
+ This function allows the firmware platform to do extra actions at the early
+ stage of the platform power up.
+
+ Note: This function must be implemented in assembler as there is no stack set up yet
+
+**/
+ASM_PFX(ArmPlatformSecBootAction):
+ bx lr
+
+/**
+ Initialize the memory where the initial stacks will reside
+
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).
+ In some platform, this region is already initialized and the implementation of this function can
+ do nothing. This memory can also represent the Secure RAM.
+ This function is called before the satck has been set up. Its implementation must ensure the stack
+ pointer is not used (probably required to use assembly language)
+
+**/
+ASM_PFX(ArmPlatformInitializeBootMemory):
+ bx lr
+
+
+/**
+ Initialize the memory where the initial stacks will reside
+
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).
+ In some platform, this region is already initialized and the implementation of this function can
+ do nothing. This memory can also represent the Secure RAM.
+ This function is called before the satck has been set up. Its implementation must ensure the stack
+ pointer is not used (probably required to use assembly language)
+
+**/
+ASM_PFX(ArmPlatformSecBootMemoryInit):
+ mov r8, lr
+ bl smc_init
+ bl dmc_init
+ bx r8
+
+
+/**
+ Initialise the Static Memory Controller
+**/
+smc_init:
+
+ //
+ // Disable loop buffer for A15
+ //
+ MRC p15, 0, r2, c0, c0, 0
+ MOV r1, r2, lsr #4
+ LDR r0, =0xFFF
+ AND r1, r1, r0
+ LDR r0, =0xC0F // See if A15
+ CMP r1, r0
+ BNE smc_init2 // Go if not
+
+ MRC p15, 0, r1, c1, c0, 1 // Read Aux Ctrl Reg
+ ORR r1, r1, #(1 << 1) // Set Bit 1
+ MCR p15, 0, r1, c1, c0, 1 // and write it back
+
+smc_init2:
+
+ LDR r0, = ARM_VE_SMC_CTRL_BASE
+ LDR r2, = ARM_VE_SMB_PERIPH_BASE
+
+ // CS0 - NOR0
+ LDR r1, = 0x0002393A
+ STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET]
+ LDR r1, = 0x00000AAA
+ STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET]
+ LDR r1, = 0x00400000
+ STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET]
+
+ // CS1 - PSRAM
+ LDR r1, = 0x00027158
+ STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET]
+ LDR r1, = 0x00000802
+ STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET]
+ LDR r1, = 0x00C00000
+ STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET]
+
+ // CS2 - usb, ethernet and vram
+ LDR r1, = 0x000CD2AA
+ STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET]
+ LDR r1, = 0x00000046
+ STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET]
+ LDR r1, = 0x01400000
+ STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET]
+
+ // CS3 - IOFPGA peripherals
+ LDR r1, = 0x00025156
+ STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET]
+ LDR r1, = 0x00000046
+ STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET]
+ LDR r1, = 0x01C00000
+ STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET]
+
+ // CS4 - NOR1
+ LDR r1, = 0x0002393A
+ STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET]
+ LDR r1, = 0x00000AAA
+ STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET]
+ LDR r1, = 0x02400000
+ STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET]
+
+ // CS5 - unused
+ LDR r1, = 0x0002393A
+ STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET]
+ LDR r1, = 0x00000AAA
+ STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET]
+ LDR r1, = 0x02C00000
+ STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET]
+
+ // CS6 - unused
+ LDR r1, = 0x0002393A
+ STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET]
+ LDR r1, = 0x00000AAA
+ STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET]
+ LDR r1, = 0x03400000
+ STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET]
+
+ // CS7 - unused
+ LDR r1, = 0x0002393A
+ STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET]
+ LDR r1, = 0x00000AAA
+ STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET]
+ LDR r1, = 0x03C00000
+ STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET]
+
+ // Set refresh period
+ LDR r1, = 0x1
+ STR r1, [r0, #0x20]
+
+ LDR r1, = 0x1
+ STR r1, [r0, #0x24]
+
+ // page mode setup for VRAM
+ LDR r0, = 0x00FFFFFC
+ ADD r0, r0, r2
+
+ // read current state
+ LDR r1, [r0, #0]
+ LDR r1, [r0, #0]
+ LDR r1, = 0x00000000
+ STR r1, [r0, #0]
+ LDR r1, [r0, #0]
+
+ // enable page mode
+ LDR r1, [r0, #0]
+ LDR r1, [r0, #0]
+ LDR r1, = 0x00000000
+ STR r1, [r0, #0]
+ LDR r1, = 0x00900090
+ STR r1, [r0, #0]
+
+ // confirm page mode enabled
+ LDR r1, [r0, #0]
+ LDR r1, [r0, #0]
+ LDR r1, = 0x00000000
+ STR r1, [r0, #0]
+ LDR r1, [r0, #0]
+
+ BX lr
+ // end of smc_init
+
+
+/**
+ Initialise the PL341 Dynamic Memory Controller (DMC)
+
+ On A15, the PHY needs to be locked before configuring the DMC.
+ After DMC config, the PHY needs to be trained
+**/
+#define SCC_PHY_RESET_REG_OFFSET 0x04
+
+dmc_init:
+
+ LDR r0, = ARM_VE_DMC_BASE
+ LDR r1, = 0x00000400 // SCC reset bit for DDR PHY
+ LDR r2, = 0x7FEF0000 // PHY addr
+
+ LDR r3, =0x3
+ STR r3, [r2, #PHY_PTM_DFI_CLK_RANGE]
+ LDR r3, =0x0
+ STR r3, [r2, #PHY_PTM_PLL_RANGE]
+ LDR r3, =0x0
+ STR r3, [r2, #PHY_PTM_FEEBACK_DIV]
+ LDR r3, =0x0
+ STR r3, [r2, #PHY_PTM_RCLK_DIV]
+ LDR r3, =0x1
+ STR r3, [r2, #PHY_PTM_PLL_EN]
+
+ // Wait for PHY to lock
+waitloop_01:
+ LDR r3, [r2, #PHY_PTM_LOCK_STATUS]
+ AND r3, #0xff
+ CMP r3, #0x1
+ BNE waitloop_01
+
+ LDR r3, =0x5
+ STR r3, [r2, #PHY_PTM_IOTERM]
+ LDR r0, =ARM_VE_SCC_BASE
+ LDR r3, [r0, #SCC_PHY_RESET_REG_OFFSET]
+ ORR r3, r3, r1
+ STR r3, [r0, #SCC_PHY_RESET_REG_OFFSET]
+
+ // wait for PHY ready
+waitloop_03:
+ LDR r3, [r2, #PHY_PTM_INIT_DONE]
+ AND r3, #0x1
+ TST r3, #0x1
+ BEQ waitloop_03
+
+ // Init PL341
+ LDR r0, = ARM_VE_DMC_BASE
+
+ LDR r1, =0x4 // enter config mode
+ STR r1, [r0, #DMC_COMMAND_REG]
+ LDR r1, =0xc30
+ STR r1, [r0, #DMC_REFRESH_PRD_REG]
+ LDR r1, =0xc
+ STR r1, [r0, #DMC_CAS_LATENCY_REG]
+ LDR r1, =0x5
+ STR r1, [r0, #DMC_WRITE_LATENCY_REG]
+ LDR r1, =0x2
+ STR r1, [r0, #DMC_T_MRD_REG]
+ LDR r1, =0x12
+ STR r1, [r0, #DMC_T_RAS_REG]
+ LDR r1, =0x18
+ STR r1, [r0, #DMC_T_RC_REG]
+ LDR r1, =0x0306
+ STR r1, [r0,#DMC_T_RCD_REG]
+ LDR r1, =0x00004c4f
+ STR r1, [r0, #DMC_T_RFC_REG]
+ LDR r1, =0x00000306
+ STR r1, [r0, #DMC_T_RP_REG]
+ LDR r1, =0x4
+ STR r1, [r0, #DMC_T_RRD_REG]
+ LDR r1, =0x6
+ STR r1, [r0, #DMC_T_WR_REG]
+ LDR r1, =0x3
+ STR r1, [r0, #DMC_T_WTR_REG]
+ LDR r1, =0x2
+ STR r1, [r0, #DMC_T_XP_REG]
+ LDR r1, =0x52
+ STR r1, [r0, #DMC_T_XSR_REG]
+ LDR r1, =0xc8
+ STR r1, [r0, #DMC_T_ESR_REG]
+ LDR r1, =0x0b0e
+ STR r1, [r0, #DMC_T_FAW_REG]
+ LDR r1, =0x3
+ STR r1, [r0, #DMC_T_RDATA_EN]
+ LDR r1, =0x1
+ STR r1, [r0, #DMC_T_WRLAT_DIFF]
+ LDR r1, =0x00210022
+ STR r1, [r0, #DMC_MEMORY_CONFIG_REG]
+ LDR r1, =0x0000007C
+ STR r1, [r0, #DMC_MEMORY_CFG2_REG]
+ LDR r1, =0x00000001
+ STR r1, [r0, #DMC_MEMORY_CFG3_REG]
+ LDR r1, =0x000000c0
+ STR r1, [r0, #DMC_CHIP_0_CFG_REG]
+ LDR r1, =0x00040c0
+ STR r1, [r0, #DMC_CHIP_1_CFG_REG]
+
+ // Configure DDR2 Devices on Chip Select 0
+ // nop
+ LDR r1, =0x000C0000
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // pre-charge all
+ LDR r1, =0x0
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // wait loop
+ LDR r1, =0x0
+waitloop_04:
+ LDR r3, [r0, #DMC_STATUS_REG]
+ ADD r1, r1, #1
+ CMP r1, #10
+ BLT waitloop_04
+
+ // extended mode register 2 (EMR2)
+ LDR r1, =0x000A0000
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // extended mode register 3 (EMR3)
+ LDR r1, =0x000B0000
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // extended mode register (EMR), OCD default state
+ LDR r1, =0x00090000
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // set mode register (MR) with DLL reset
+ LDR r1,=0x00080B62
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // pre-charge all
+ LDR r1, =0x0
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // auto-refresh
+ LDR r1, =0x00040000
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // auto-refresh
+ LDR r1, =0x00040000
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // set mode register (MR) without DLL reset
+ LDR r1,=0x00080A62
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // wait loop
+ LDR r1, =0x0
+waitloop_05:
+ LDR r3, [r0, #DMC_STATUS_REG]
+ ADD r1, r1, #1
+ CMP r1, #10
+ BLT waitloop_05
+
+ // extended mode register (EMR) enable OCD defaults
+ LDR r1, =0x00094384
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // wait loop
+ LDR r1, =0x0
+waitloop_06:
+ LDR r3, [r0, #DMC_STATUS_REG]
+ ADD r1, r1, #1
+ CMP r1, #10
+ BLT waitloop_06
+
+ // extended mode register (EMR) OCD Exit
+ LDR r1, =0x00094004
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // wait loop
+ LDR r1, =0x0
+waitloop_07:
+ LDR r3, [r0, #DMC_STATUS_REG]
+ ADD r1, r1, #1
+ CMP r1, #10
+ BLT waitloop_07
+
+ // Configure DDR2 Devices on Chip Select 1
+ // send nop
+ // nop
+ LDR r1, =0x001C0000
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // pre-charge all
+ LDR r1, =0x00100000
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // wait loop
+ LDR r1, =0x0
+waitloop_08:
+ LDR r3, [r0, #DMC_STATUS_REG]
+ ADD r1, r1, #1
+ CMP r1, #10
+ BLT waitloop_08
+
+ // set extended mode register 2
+ LDR r1, =0x001A0000
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // set extended mode register 3
+ LDR r1, =0x001B0000
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // extended mode register (EMR) OCD default state
+ LDR r1, =0x00190000
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // mode register (MR) with DLL reset
+ LDR r1,=0x00180B62
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // pre-charge all
+ LDR r1, =0x00100000
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // auto-refresh
+ LDR r1, =0x00140000
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // auto-refresh
+ LDR r1, =0x00140000
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+
+ // mode register (MR) without DLL reset
+ LDR r1,=0x00180A62
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // wait loop
+ LDR r1, =0x0
+waitloop_09:
+ LDR r3, [r0, #DMC_STATUS_REG]
+ ADD r1, r1, #1
+ CMP r1, #10
+ BLT waitloop_09
+
+ // extended mode register (EMR) enable OCD defaults
+ LDR r1, =0x00194384
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // wait loop
+ LDR r1, =0x0
+waitloop_10:
+ LDR r3, [r0, #DMC_STATUS_REG]
+ ADD r1, r1, #1
+ CMP r1, #10
+ BLT waitloop_10
+
+ // extended mode register (EMR) OCD Exit
+ LDR r1, =0x00194004
+ STR r1, [r0, #DMC_DIRECT_CMD_REG]
+
+ // wait loop
+ LDR r1, =0x0
+waitloop_11:
+ LDR r3, [r0, #DMC_STATUS_REG]
+ ADD r1, r1, #1
+ CMP r1, #10
+ BLT waitloop_11
+
+ // go command
+ LDR r1, =DMC_COMMAND_GO
+ STR r1, [r0, #DMC_COMMAND_REG]
+
+ // wait for ready
+waitloop_12:
+ LDR r1, [r0,#DMC_STATUS_REG]
+ AND r1, #0x3 // Mask of all but memc_status bits
+ TST r1,#1
+ BEQ waitloop_12
+
+ // PHY Squelch Training
+ LDR r3, =0x1
+ STR r3, [r2, #PHY_PTM_SQU_TRAINING]
+
+ LDR r5, =0x80000000
+waitloop_13:
+ LDR r4, =0
+waitloop_14:
+ LDR r3, [r5, #0]
+ ADD r4, #1
+ CMP r4, #200
+ BNE waitloop_14
+
+ // wait for ready
+ LDR r3, [r2,#PHY_PTM_SQU_STAT]
+ TST r3,#1
+ BEQ waitloop_13
+
+ LDR r3, =0
+ STR r3, [r2, #PHY_PTM_SQU_TRAINING]
+
+ // For Test Chip Change Program architected timer frequency
+ MRC p15, 0, r0, c0, c1, 1 // CPUID_EXT_PFR1
+ LSR r0, r0, #16
+ ANDS r0, r0, #1 // Check generic timer support
+ BEQ exit
+ LDR r0, = 600000000 // 600MHz timer frequency
+ MCR p15, 0, r0, c14, c0, 0 // CNTFRQ
+
+exit:
+ bx lr
+ // end of dmc_init
+
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.asm b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.asm new file mode 100644 index 000000000..a81db9d62 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Boot.asm @@ -0,0 +1,127 @@ +//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <Library/ArmPlatformLib.h>
+#include <Drivers/PL35xSmc.h>
+#include <ArmPlatform.h>
+#include <AutoGen.h>
+
+ INCLUDE AsmMacroIoLib.inc
+
+ EXPORT ArmPlatformSecBootAction
+ EXPORT ArmPlatformInitializeBootMemory
+ IMPORT PL35xSmcInitialize
+
+ PRESERVE8
+ AREA CTA15x2BootMode, CODE, READONLY
+
+//
+// For each Chip Select: ChipSelect / SetCycle / SetOpMode
+//
+VersatileExpressSmcConfiguration
+ // NOR Flash 0
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(0)
+ DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV
+
+ // NOR Flash 1
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(4)
+ DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV
+
+ // SRAM
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(2)
+ DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_ADV
+
+ // Usb/Eth/VRAM
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(3)
+ DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6)
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
+
+ // Memory Mapped Peripherals
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(7)
+ DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
+
+ // VRAM
+ DCD PL350_SMC_DIRECT_CMD_ADDR_CS(1)
+ DCD 0x00049249
+ DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC
+VersatileExpressSmcConfigurationEnd
+
+/**
+ Call at the beginning of the platform boot up
+
+ This function allows the firmware platform to do extra actions at the early
+ stage of the platform power up.
+
+ Note: This function must be implemented in assembler as there is no stack set up yet
+
+**/
+ArmPlatformSecBootAction
+ bx lr
+
+/**
+ Initialize the memory where the initial stacks will reside
+
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).
+ In some platform, this region is already initialized and the implementation of this function can
+ do nothing. This memory can also represent the Secure RAM.
+ This function is called before the satck has been set up. Its implementation must ensure the stack
+ pointer is not used (probably required to use assembly language)
+
+**/
+ArmPlatformInitializeBootMemory
+ mov r5, lr
+
+ //
+ // Initialize PL354 SMC
+ //
+ LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)
+ ldr r2, =VersatileExpressSmcConfiguration
+ ldr r3, =VersatileExpressSmcConfigurationEnd
+ blx PL35xSmcInitialize
+
+ //
+ // Page mode setup for VRAM
+ //
+ LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)
+
+ // Read current state
+ ldr r0, [r2, #0]
+ ldr r0, [r2, #0]
+ ldr r0, = 0x00000000
+ str r0, [r2, #0]
+ ldr r0, [r2, #0]
+
+ // Enable page mode
+ ldr r0, [r2, #0]
+ ldr r0, [r2, #0]
+ ldr r0, = 0x00000000
+ str r0, [r2, #0]
+ ldr r0, = 0x00900090
+ str r0, [r2, #0]
+
+ // Confirm page mode enabled
+ ldr r0, [r2, #0]
+ ldr r0, [r2, #0]
+ ldr r0, = 0x00000000
+ str r0, [r2, #0]
+ ldr r0, [r2, #0]
+
+ryan doesn't want this to happen
+
+ bx r5
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Helper.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Helper.S new file mode 100644 index 000000000..d01cd379c --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Helper.S @@ -0,0 +1,60 @@ +# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+#include <AsmMacroIoLib.h>
+#include <Library/ArmLib.h>
+
+.text
+.align 2
+
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
+
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0)
+ ldr r0, [r0]
+ bx lr
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_PFX(ArmPlatformIsPrimaryCore):
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)
+ ldr r1, [r1]
+ and r0, r0, r1
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)
+ ldr r1, [r1]
+ cmp r0, r1
+ moveq r0, #1
+ movne r0, #0
+ bx lr
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+ASM_PFX(ArmPlatformGetCorePosition):
+ and r0, r0, #ARM_CORE_MASK
+ bx lr
+
+ASM_PFX(ArmPlatformPeiBootAction):
+ bx lr
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Helper.asm b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Helper.asm new file mode 100644 index 000000000..a938be681 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Helper.asm @@ -0,0 +1,69 @@ +// Copyright (c) 2013, ARM Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AsmMacroIoLib.h>
+#include <Library/ArmLib.h>
+
+#include <AutoGen.h>
+
+ INCLUDE AsmMacroIoLib.inc
+
+ EXPORT ArmPlatformPeiBootAction
+ EXPORT ArmPlatformIsPrimaryCore
+ EXPORT ArmPlatformGetPrimaryCoreMpId
+ EXPORT ArmPlatformGetCorePosition
+
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask
+
+ AREA CTA9x4Helper, CODE, READONLY
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ArmPlatformGetPrimaryCoreMpId FUNCTION
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0)
+ ldr r0, [r0]
+ bx lr
+ ENDFUNC
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ArmPlatformIsPrimaryCore FUNCTION
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)
+ ldr r1, [r1]
+ and r0, r0, r1
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)
+ ldr r1, [r1]
+ cmp r0, r1
+ moveq r0, #1
+ movne r0, #0
+ bx lr
+ ENDFUNC
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+ArmPlatformGetCorePosition FUNCTION
+ and r0, r0, #ARM_CORE_MASK
+ bx lr
+ ENDFUNC
+
+ArmPlatformPeiBootAction FUNCTION
+ bx lr
+ ENDFUNC
+
+ END
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Mem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Mem.c new file mode 100644 index 000000000..1f6530295 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Mem.c @@ -0,0 +1,127 @@ +#/* @file
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <ArmPlatform.h>
+
+// Number of Virtual Memory Map Descriptors without a Logic Tile
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+ )
+{
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
+ UINTN Index = 0;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ ASSERT(VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
+ CacheAttributes = DDR_ATTRIBUTES_CACHED;
+ } else {
+ CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
+ }
+
+ // ReMap (Either NOR Flash or DRAM)
+ VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE;
+ VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ;
+
+ if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) {
+ // Map the NOR Flash as Secure Memory
+ if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
+ VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
+ } else {
+ VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_UNCACHED;
+ }
+ } else {
+ // DRAM mapping
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+ }
+
+ // DDR
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;
+ VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+
+ // SMC CS7
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE;
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE;
+ VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // SMB CS0-CS1 - NOR Flash 1 & 2
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // SMB CS2 - SRAM
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;
+ VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;
+ VirtualMemoryTable[Index].Attributes = CacheAttributes;
+
+ // SMB CS3-CS6 - Motherboard Peripherals
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;
+ VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // If a Logic Tile is connected to The ARM Versatile Express Motherboard
+ if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {
+ VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;
+ VirtualMemoryTable[Index].VirtualBase = ARM_VE_EXT_AXI_BASE;
+ VirtualMemoryTable[Index].Length = ARM_VE_EXT_AXI_SZ;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1));
+ } else {
+ ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+ }
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Sec.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Sec.c new file mode 100644 index 000000000..d91149d95 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15x2/CTA15x2Sec.c @@ -0,0 +1,73 @@ +#/* @file
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Drivers/PL310L2Cache.h>
+#include <Drivers/SP804Timer.h>
+#include <ArmPlatform.h>
+
+/**
+ Initialize the Secure peripherals and memory regions
+
+ If Trustzone is supported by your platform then this function makes the required initialization
+ of the secure peripherals and memory regions.
+
+**/
+VOID
+ArmPlatformTrustzoneInit (
+ VOID
+ )
+{
+ // No TZPC or TZASC on RTSM to initialize
+}
+
+/**
+ Initialize controllers that must setup at the early stage
+
+ Some peripherals must be initialized in Secure World.
+ For example, some L2x0 requires to be initialized in Secure World
+
+**/
+VOID
+ArmPlatformSecInitialize (
+ VOID
+ )
+{
+ // Configure periodic timer (TIMER0) for 1MHz operation
+ MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
+ // Configure 1MHz clock
+ MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
+ // Configure SP810 to use 1MHz clock and disable
+ MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
+ // Configure SP810 to use 1MHz clock and disable
+ MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
+}
+
+/**
+ Call before jumping to Normal World
+
+ This function allows the firmware platform to do extra actions before
+ jumping to the Normal World
+
+**/
+VOID
+ArmPlatformSecExtraAction (
+ IN UINTN MpId,
+ OUT UINTN* JumpAddress
+ )
+{
+ *JumpAddress = PcdGet32(PcdFvBaseAddress);
+}
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressLib.inf new file mode 100644 index 000000000..de141a86b --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressLib.inf @@ -0,0 +1,54 @@ +#/* @file +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = CTA5sArmVExpressLib + FILE_GUID = b16c63a0-f417-11df-b3af-0002a5d5c51b + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + IoLib + ArmLib + PL341DmcLib + PL301AxiLib + L2X0CacheLib + SerialPortLib + +[Sources.common] + CTA5s.c + CTA5sMem.c + CTA5Helper.asm | RVCT + CTA5Helper.S | GCC + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdCoreCount + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize + gArmTokenSpaceGuid.PcdFvBaseAddress + + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressSecLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressSecLib.inf new file mode 100644 index 000000000..147f3e8e6 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/ArmVExpressSecLib.inf @@ -0,0 +1,53 @@ +#/* @file +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = CTA5sArmVExpressLib + FILE_GUID = b16c63a0-f417-11df-b3af-0002a5d5c51b + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + ArmLib + ArmPlatformSysConfigLib + IoLib + L2X0CacheLib + PL301AxiLib + PL341DmcLib + PL35xSmcLib + SerialPortLib + +[Sources.common] + CTA5sSec.c + CTA5s.c + CTA5sBoot.asm | RVCT + CTA5sBoot.S | GCC + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvBaseAddress + + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask + gArmTokenSpaceGuid.PcdArmPrimaryCore diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5Helper.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5Helper.S new file mode 100644 index 000000000..f18aeef89 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5Helper.S @@ -0,0 +1,62 @@ +# +# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# + +#include <AsmMacroIoLib.h> +#include <Library/ArmLib.h> + +.text +.align 2 + +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) + +GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore) +GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask) + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0) + ldr r0, [r0] + bx lr + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformIsPrimaryCore): + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1) + ldr r1, [r1] + and r0, r0, r1 + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1) + ldr r1, [r1] + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + bx lr + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformGetCorePosition): + and r0, r0, #ARM_CORE_MASK + bx lr + +ASM_PFX(ArmPlatformPeiBootAction): + bx lr + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5Helper.asm b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5Helper.asm new file mode 100644 index 000000000..a112b9e26 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5Helper.asm @@ -0,0 +1,70 @@ +// +// Copyright (c) 2013, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include <AsmMacroIoLib.h> +#include <Library/ArmLib.h> + +#include <AutoGen.h> + + INCLUDE AsmMacroIoLib.inc + + EXPORT ArmPlatformPeiBootAction + EXPORT ArmPlatformIsPrimaryCore + EXPORT ArmPlatformGetPrimaryCoreMpId + EXPORT ArmPlatformGetCorePosition + + IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore + IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask + + AREA CTA9x4Helper, CODE, READONLY + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ArmPlatformGetPrimaryCoreMpId FUNCTION + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r0) + ldr r0, [r0] + bx lr + ENDFUNC + +//UINTN +//ArmPlatformIsPrimaryCore ( +// IN UINTN MpId +// ); +ArmPlatformIsPrimaryCore FUNCTION + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1) + ldr r1, [r1] + and r0, r0, r1 + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1) + ldr r1, [r1] + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + bx lr + ENDFUNC + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ArmPlatformGetCorePosition FUNCTION + and r0, r0, #ARM_CORE_MASK + bx lr + ENDFUNC + +ArmPlatformPeiBootAction FUNCTION + bx lr + ENDFUNC + + END diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5s.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5s.c new file mode 100644 index 000000000..ccf6fe0a6 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5s.c @@ -0,0 +1,162 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/IoLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/SerialPortLib.h> + +#include <Drivers/PL341Dmc.h> +#include <Drivers/PL301Axi.h> +#include <Drivers/SP804Timer.h> + +#include <Ppi/ArmMpCoreInfo.h> + +#include <ArmPlatform.h> + +#define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1); + +ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA5s[] = { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, + { + // Cluster 0, Core 1 + 0x0, 0x1, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG, + (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG, + (UINT64)0xFFFFFFFF + }, +}; + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + + @return Return the current Boot Mode of the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + if (MmioRead32(ARM_VE_SYS_FLAGS_NV_REG) == 0) { + return BOOT_WITH_FULL_CONFIGURATION; + } else { + return BOOT_ON_S2_RESUME; + } +} + +/** + Initialize controllers that must setup in the normal world + + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei + in the PEI phase. + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + if (!ArmPlatformIsPrimaryCore (MpId)) { + return RETURN_SUCCESS; + } + + // Configure periodic timer (TIMER0) for 1MHz operation + MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK); + // Configure 1MHz clock + MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK); + // configure SP810 to use 1MHz clock and disable + MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK); + // Configure SP810 to use 1MHz clock and disable + MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK); + + return RETURN_SUCCESS; +} + +/** + Initialize the system (or sometimes called permanent) memory + + This memory is generally represented by the DRAM. + +**/ +VOID +ArmPlatformInitializeSystemMemory ( + VOID + ) +{ + // Memory is initialised in CTA5sBoot.S +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount = sizeof(mVersatileExpressMpCoreInfoCTA5s) / sizeof(ARM_CORE_INFO); + *ArmCoreTable = mVersatileExpressMpCoreInfoCTA5s; + + return EFI_SUCCESS; +} + +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &mArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof(gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} + +/** + Initialize the Secure peripherals and memory regions + + If Trustzone is supported by your platform then this function makes the required initialization + of the secure peripherals and memory regions. + +**/ +VOID +ArmPlatformSecTrustzoneInit ( + IN UINTN MpId + ) +{ +} diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sBoot.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sBoot.S new file mode 100644 index 000000000..51f1db05a --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sBoot.S @@ -0,0 +1,386 @@ +// +// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include <AsmMacroIoLib.h> +#include <Base.h> +#include <Library/ArmPlatformLib.h> +#include <Drivers/PL35xSmc.h> +#include <Drivers/PL341Dmc.h> +#include <ArmPlatform.h> +#include <AutoGen.h> + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformSecBootAction) +GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory) +GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit) + +/** + Call at the beginning of the platform boot up + + This function allows the firmware platform to do extra actions at the early + stage of the platform power up. + + Note: This function must be implemented in assembler as there is no stack set up yet + +**/ +ASM_PFX(ArmPlatformSecBootAction): + bx lr + +/** + Initialize the memory where the initial stacks will reside + + This memory can contain the initial stacks (Secure and Secure Monitor stacks). + In some platform, this region is already initialized and the implementation of this function can + do nothing. This memory can also represent the Secure RAM. + This function is called before the satck has been set up. Its implementation must ensure the stack + pointer is not used (probably required to use assembly language) + +**/ +ASM_PFX(ArmPlatformInitializeBootMemory): + bx lr + + +/** + Initialize the memory where the initial stacks will reside + + This memory can contain the initial stacks (Secure and Secure Monitor stacks). + In some platform, this region is already initialized and the implementation of this function can + do nothing. This memory can also represent the Secure RAM. + This function is called before the satck has been set up. Its implementation must ensure the stack + pointer is not used (probably required to use assembly language) + +**/ +ASM_PFX(ArmPlatformSecBootMemoryInit): + mov r8, lr + bl smc_init + bl dmc_init + bx r8 + + +/** + Initialise the Static Memory Controller +**/ +smc_init: + + // + // Disable loop buffer for A15 + // + MRC p15, 0, r2, c0, c0, 0 + MOV r1, r2, lsr #4 + LDR r0, =0xFFF + AND r1, r1, r0 + LDR r0, =0xC0F // See if A15 + CMP r1, r0 + BNE smc_init2 // Go if not + + MRC p15, 0, r1, c1, c0, 1 // Read Aux Ctrl Reg + ORR r1, r1, #(1 << 1) // Set Bit 1 + MCR p15, 0, r1, c1, c0, 1 // and write it back + +smc_init2: + + LDR r0, = ARM_VE_SMC_CTRL_BASE + LDR r2, = ARM_VE_SMB_PERIPH_BASE + + // CS0 - NOR0 + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x00400000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS1 - PSRAM + LDR r1, = 0x00027158 + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000802 + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x00C00000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS2 - usb, ethernet and vram + LDR r1, = 0x000CD2AA + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000046 + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x01400000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS3 - IOFPGA peripherals + LDR r1, = 0x00025156 + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000046 + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x01C00000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS4 - NOR1 + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x02400000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS5 - unused + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x02C00000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS6 - unused + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x03400000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // CS7 - unused + LDR r1, = 0x0002393A + STR r1, [r0, #PL350_SMC_SET_CYCLES_OFFSET] + LDR r1, = 0x00000AAA + STR r1, [r0, #PL350_SMC_SET_OPMODE_OFFSET] + LDR r1, = 0x03C00000 + STR r1, [r0, #PL350_SMC_DIRECT_CMD_OFFSET] + + // Set refresh period + LDR r1, = 0x1 + STR r1, [r0, #0x20] + + LDR r1, = 0x1 + STR r1, [r0, #0x24] + + // page mode setup for VRAM + LDR r0, = 0x00FFFFFC + ADD r0, r0, r2 + + // read current state + LDR r1, [r0, #0] + LDR r1, [r0, #0] + LDR r1, = 0x00000000 + STR r1, [r0, #0] + LDR r1, [r0, #0] + + // enable page mode + LDR r1, [r0, #0] + LDR r1, [r0, #0] + LDR r1, = 0x00000000 + STR r1, [r0, #0] + LDR r1, = 0x00900090 + STR r1, [r0, #0] + + // confirm page mode enabled + LDR r1, [r0, #0] + LDR r1, [r0, #0] + LDR r1, = 0x00000000 + STR r1, [r0, #0] + LDR r1, [r0, #0] + + BX lr + // end of smc_init + + +/** + Initialise the PL341 Dynamic Memory Controller (DMC) + + On A15, the PHY needs to be locked before configuring the DMC. + After DMC config, the PHY needs to be trained +**/ +#define SCC_PHY_RESET_REG_OFFSET 0x04 + +dmc_init: + + LDR r0, = ARM_VE_DMC_BASE + LDR r1, = ARM_VE_BOARD_PERIPH_BASE + + // On entry:- + // r0 = base address of ssmc controller + // r1 = address of system registers + + // Initializes V2P_CA5 dynamic memory controller + + MOV r2, r1 + + // set config mode + MOV r1, #0x4 + STR r1, [r0, #DMC_COMMAND_REG] + + // initialise memory controlller + + // refresh period + LDR r1, =0x3D0 + STR r1, [r0, #DMC_REFRESH_PRD_REG] + + // cas latency + MOV r1, #0xA + STR r1, [r0, #DMC_CAS_LATENCY_REG] + + // write latency + MOV r1, #0x3 + STR r1, [r0, #DMC_WRITE_LATENCY_REG] + + // t_mrd + MOV r1, #0x2 + STR r1, [r0, #DMC_T_MRD_REG] + + // t_ras + MOV r1, #0x0C + STR r1, [r0, #DMC_T_RAS_REG] + + // t_rc + MOV r1, #0x0F + STR r1, [r0, #DMC_T_RC_REG] + + // t_rcd + LDR r1, =0x00000104 + STR r1, [r0,#DMC_T_RCD_REG] + + // t_rfc + LDR r1, =0x00001022 + STR r1, [r0, #DMC_T_RFC_REG] + + // t_rp + LDR r1, =0x00000104 + STR r1, [r0, #DMC_T_RP_REG] + + // t_rrd + MOV r1, #0x2 + STR r1, [r0, #DMC_T_RRD_REG] + + // t_wr + MOV r1, #0x4 + STR r1, [r0, #DMC_T_WR_REG] + + // t_wtr + MOV r1, #0x2 + STR r1, [r0, #DMC_T_WTR_REG] + + // t_xp + MOV r1, #0x2 + STR r1, [r0, #DMC_T_XP_REG] + + // t_xsr + MOV r1, #0xC8 + STR r1, [r0, #DMC_T_XSR_REG] + + // t_esr + MOV r1, #0x04 + STR r1, [r0, #DMC_T_ESR_REG] + + // t_faw + LDR r1, =0x00000407 + STR r1, [r0, #DMC_T_FAW_REG] + + // set memory config + LDR r1, =0x0001001A + STR r1, [r0, #DMC_MEMORY_CONFIG_REG] + + // set memory config 2 + LDR r1, =0x000000B0 + STR r1, [r0, #DMC_MEMORY_CFG2_REG] + + // initialise external memory chips + // set chip select for chip configuration + LDR r1, =0x000180C0 + STR r1, [r0, #DMC_CHIP_0_CFG_REG] + + // config memories + + // send nop + LDR r1, =0x000C0000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // delay + MOV r1, #0 +B1: LDR r3, [r0, #DMC_STATUS_REG] // read status register + ADD r1, r1, #1 + CMP r1, #10 + BLT B1 + + // pre-charge all + MOV r1, #0x0 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // delay + MOV r1, #0 +B2: LDR r3, [r0, #DMC_STATUS_REG] // read status register + ADD r1, r1, #1 + CMP r1, #10 + BLT B2 + + // set extended mode register 2 + LDR r1, =0x000A8000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set extended mode register 3 + MOV r1, #0x000B0000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set extended mode register + LDR r1, =0x00094005 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set mode register -DLL reset + LDR r1, =0x00080552 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // delay + MOV r1, #0 +B3: LDR r3, [r0, #DMC_STATUS_REG] // read status register + ADD r1, r1, #1 + CMP r1, #10 + BLT B3 + + // pre-charge all + MOV r1, #0x0 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // auto-refresh + MOV r1, #0x00040000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // auto-refresh + MOV r1, #0x00040000 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set mode register + LDR r1, =0x00080452 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set extended mode register - Enable OCD defaults + LDR r1, =0x000943C5 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + // set extended mode register - OCD Exit + LDR r1, =0x00094047 + STR r1, [r0, #DMC_DIRECT_CMD_REG] + + //---------------------------------------- + // go command + MOV r1, #0x0 + STR r1, [r0, #DMC_COMMAND_REG] + + // wait for ready +B4: LDR r1, [r0,#DMC_STATUS_REG] + TST r1,#1 + BEQ B4 + +exit: + bx lr + // end of dmc_init + diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sBoot.asm b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sBoot.asm new file mode 100644 index 000000000..39d903378 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sBoot.asm @@ -0,0 +1,127 @@ +// +// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include <AsmMacroIoLib.h> +#include <Base.h> +#include <Library/ArmPlatformLib.h> +#include <Drivers/PL35xSmc.h> +#include <ArmPlatform.h> +#include <AutoGen.h> + + INCLUDE AsmMacroIoLib.inc + + EXPORT ArmPlatformSecBootAction + EXPORT ArmPlatformInitializeBootMemory + IMPORT PL35xSmcInitialize + + PRESERVE8 + AREA CTA5sBootMode, CODE, READONLY + +// +// For each Chip Select: ChipSelect / SetCycle / SetOpMode +// +VersatileExpressSmcConfiguration + // NOR Flash 0 + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(0) + DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1) + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV + + // NOR Flash 1 + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(4) + DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1) + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV + + // SRAM + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(2) + DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1) + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_ADV + + // Usb/Eth/VRAM + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(3) + DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6) + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC + + // Memory Mapped Peripherals + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(7) + DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1) + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC + + // VRAM + DCD PL350_SMC_DIRECT_CMD_ADDR_CS(1) + DCD 0x00049249 + DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC +VersatileExpressSmcConfigurationEnd + +/** + Call at the beginning of the platform boot up + + This function allows the firmware platform to do extra actions at the early + stage of the platform power up. + + Note: This function must be implemented in assembler as there is no stack set up yet + +**/ +ArmPlatformSecBootAction + bx lr + +/** + Initialize the memory where the initial stacks will reside + + This memory can contain the initial stacks (Secure and Secure Monitor stacks). + In some platform, this region is already initialized and the implementation of this function can + do nothing. This memory can also represent the Secure RAM. + This function is called before the satck has been set up. Its implementation must ensure the stack + pointer is not used (probably required to use assembly language) + +**/ +ArmPlatformInitializeBootMemory + mov r5, lr + + // + // Initialize PL354 SMC + // + LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1) + ldr r2, =VersatileExpressSmcConfiguration + ldr r3, =VersatileExpressSmcConfigurationEnd + blx PL35xSmcInitialize + + // + // Page mode setup for VRAM + // + LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2) + + // Read current state + ldr r0, [r2, #0] + ldr r0, [r2, #0] + ldr r0, = 0x00000000 + str r0, [r2, #0] + ldr r0, [r2, #0] + + // Enable page mode + ldr r0, [r2, #0] + ldr r0, [r2, #0] + ldr r0, = 0x00000000 + str r0, [r2, #0] + ldr r0, = 0x00900090 + str r0, [r2, #0] + + // Confirm page mode enabled + ldr r0, [r2, #0] + ldr r0, [r2, #0] + ldr r0, = 0x00000000 + str r0, [r2, #0] + ldr r0, [r2, #0] + +ryan doesn't want this to happen + + bx r5 diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sMem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sMem.c new file mode 100644 index 000000000..eee3c3c9f --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sMem.c @@ -0,0 +1,128 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> + +#include <ArmPlatform.h> + +// Number of Virtual Memory Map Descriptors without a Logic Tile +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 6 + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- + Virtual Memory mapping. This array must be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + UINTN Index = 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + ASSERT(VirtualMemoryMap != NULL); + + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable == NULL) { + return; + } + + if (FeaturePcdGet(PcdCacheEnable) == TRUE) { + CacheAttributes = DDR_ATTRIBUTES_CACHED; + } else { + CacheAttributes = DDR_ATTRIBUTES_UNCACHED; + } + + // ReMap (Either NOR Flash or DRAM) + VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ; + + if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) { + // Map the NOR Flash as Secure Memory + if (FeaturePcdGet(PcdCacheEnable) == TRUE) { + VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED; + } else { + VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_UNCACHED; + } + } else { + // DRAM mapping + VirtualMemoryTable[Index].Attributes = CacheAttributes; + } + + // DDR + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // SMC CS7 + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // SMB CS0-CS1 - NOR Flash 1 & 2 + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // SMB CS2 - SRAM + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ; + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // SMB CS3-CS6 - Motherboard Peripherals + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE; + VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + // If a Logic Tile is connected to The ARM Versatile Express Motherboard + if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) { + VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE; + VirtualMemoryTable[Index].VirtualBase = ARM_VE_EXT_AXI_BASE; + VirtualMemoryTable[Index].Length = ARM_VE_EXT_AXI_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + + ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1)); + } else { + ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + } + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + *VirtualMemoryMap = VirtualMemoryTable; +} diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sSec.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sSec.c new file mode 100644 index 000000000..d9d3ff731 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA5s/CTA5sSec.c @@ -0,0 +1,74 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/IoLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Drivers/PL310L2Cache.h> +#include <Drivers/SP804Timer.h> +#include <ArmPlatform.h> + +/** + Initialize the Secure peripherals and memory regions + + If Trustzone is supported by your platform then this function makes the required initialization + of the secure peripherals and memory regions. + +**/ +VOID +ArmPlatformTrustzoneInit ( + VOID + ) +{ + // No TZPC or TZASC on RTSM to initialize +} + +/** + Initialize controllers that must setup at the early stage + + Some peripherals must be initialized in Secure World. + For example, some L2x0 requires to be initialized in Secure World + +**/ +VOID +ArmPlatformSecInitialize ( + VOID + ) +{ + // Configure periodic timer (TIMER0) for 1MHz operation + MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK); + // Configure 1MHz clock + MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK); + // Configure SP810 to use 1MHz clock and disable + MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK); + // Configure SP810 to use 1MHz clock and disable + MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK); +} + +/** + Call before jumping to Normal World + + This function allows the firmware platform to do extra actions before + jumping to the Normal World + +**/ +VOID +ArmPlatformSecExtraAction ( + IN UINTN MpId, + OUT UINTN* JumpAddress + ) +{ + *JumpAddress = PcdGet32(PcdFvBaseAddress); +} diff --git a/ArmPlatformPkg/ArmVExpressPkg/fvp-base-gicv2-psci.dtb b/ArmPlatformPkg/ArmVExpressPkg/fvp-base-gicv2-psci.dtb Binary files differnew file mode 100644 index 000000000..5bfdcf1da --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/fvp-base-gicv2-psci.dtb diff --git a/ArmPlatformPkg/ArmVExpressPkg/fvp-foundation-gicv2-psci.dtb b/ArmPlatformPkg/ArmVExpressPkg/fvp-foundation-gicv2-psci.dtb Binary files differnew file mode 100644 index 000000000..70175e892 --- /dev/null +++ b/ArmPlatformPkg/ArmVExpressPkg/fvp-foundation-gicv2-psci.dtb diff --git a/ArmPlatformPkg/PlatformSmbiosDxe/PlatformSmbiosDxe.c b/ArmPlatformPkg/PlatformSmbiosDxe/PlatformSmbiosDxe.c new file mode 100644 index 000000000..68ce8df66 --- /dev/null +++ b/ArmPlatformPkg/PlatformSmbiosDxe/PlatformSmbiosDxe.c @@ -0,0 +1,730 @@ +/** @file + Static SMBIOS Table for ARM platform + Derived from EmulatorPkg package + + Note SMBIOS 2.7.1 Required structures: + BIOS Information (Type 0) + System Information (Type 1) + Board Information (Type 2) + System Enclosure (Type 3) + Processor Information (Type 4) - CPU Driver + Cache Information (Type 7) - For cache that is external to processor + System Slots (Type 9) - If system has slots + Physical Memory Array (Type 16) + Memory Device (Type 17) - For each socketed system-memory Device + Memory Array Mapped Address (Type 19) - One per contiguous block per Physical Memroy Array + System Boot Information (Type 32) + + Copyright (c) 2012, Apple Inc. All rights reserved.<BR> + Copyright (c) 2013 Linaro.org + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +//#include <PiDxe.h> +#include <Protocol/Smbios.h> +#include <IndustryStandard/SmBios.h> +#include <Guid/SmBios.h> +#include <Library/DebugLib.h> +#include <Library/UefiDriverEntryPoint.h> +#include <Library/UefiLib.h> +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/UefiBootServicesTableLib.h> +/*********************************************************************** + SMBIOS data definition TYPE0 BIOS Information +************************************************************************/ +SMBIOS_TABLE_TYPE0 mBIOSInfoType0 = { + { EFI_SMBIOS_TYPE_BIOS_INFORMATION, sizeof (SMBIOS_TABLE_TYPE0), 0 }, + 1, // Vendor String + 2, // BiosVersion String + 0xE000, // BiosSegment + 3, // BiosReleaseDate String + 0x7F, // BiosSize + { // BiosCharacteristics + 0, // Reserved :2; ///< Bits 0-1. + 0, // Unknown :1; + 0, // BiosCharacteristicsNotSupported :1; + 0, // IsaIsSupported :1; + 0, // McaIsSupported :1; + 0, // EisaIsSupported :1; + 0, // PciIsSupported :1; + 0, // PcmciaIsSupported :1; + 0, // PlugAndPlayIsSupported :1; + 0, // ApmIsSupported :1; + 1, // BiosIsUpgradable :1; + 1, // BiosShadowingAllowed :1; + 0, // VlVesaIsSupported :1; + 0, // EscdSupportIsAvailable :1; + 0, // BootFromCdIsSupported :1; + 1, // SelectableBootIsSupported :1; + 0, // RomBiosIsSocketed :1; + 0, // BootFromPcmciaIsSupported :1; + 0, // EDDSpecificationIsSupported :1; + 0, // JapaneseNecFloppyIsSupported :1; + 0, // JapaneseToshibaFloppyIsSupported :1; + 0, // Floppy525_360IsSupported :1; + 0, // Floppy525_12IsSupported :1; + 0, // Floppy35_720IsSupported :1; + 0, // Floppy35_288IsSupported :1; + 0, // PrintScreenIsSupported :1; + 0, // Keyboard8042IsSupported :1; + 0, // SerialIsSupported :1; + 0, // PrinterIsSupported :1; + 0, // CgaMonoIsSupported :1; + 0, // NecPc98 :1; + 0 // ReservedForVendor :32; ///< Bits 32-63. Bits 32-47 reserved for BIOS vendor + ///< and bits 48-63 reserved for System Vendor. + }, + { // BIOSCharacteristicsExtensionBytes[] + 0x81, // AcpiIsSupported :1; + // UsbLegacyIsSupported :1; + // AgpIsSupported :1; + // I2OBootIsSupported :1; + // Ls120BootIsSupported :1; + // AtapiZipDriveBootIsSupported :1; + // Boot1394IsSupported :1; + // SmartBatteryIsSupported :1; + // BIOSCharacteristicsExtensionBytes[1] + 0x0a, // BiosBootSpecIsSupported :1; + // FunctionKeyNetworkBootIsSupported :1; + // TargetContentDistributionEnabled :1; + // UefiSpecificationSupported :1; + // VirtualMachineSupported :1; + // ExtensionByte2Reserved :3; + }, + 0x00, // SystemBiosMajorRelease + 0x01, // SystemBiosMinorRelease + 0xFF, // EmbeddedControllerFirmwareMajorRelease + 0xFF, // EmbeddedControllerFirmwareMinorRelease +}; + +CHAR8 *mBIOSInfoType0Strings[] = { + "edk2.sourceforge.net", // Vendor String + __TIME__, // BiosVersion String + __DATE__, // BiosReleaseDate String + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE1 System Information +************************************************************************/ +SMBIOS_TABLE_TYPE1 mSysInfoType1 = { + { EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, sizeof (SMBIOS_TABLE_TYPE1), 0 }, + 1, // Manufacturer String + 2, // ProductName String + 3, // Version String + 4, // SerialNumber String + { 0x25EF0280, 0xEC82, 0x42B0, { 0x8F, 0xB6, 0x10, 0xAD, 0xCC, 0xC6, 0x7C, 0x02 } }, + SystemWakeupTypePowerSwitch, + 5, // SKUNumber String + 6, // Family String +}; +CHAR8 *mSysInfoType1Strings[] = { + "ARM", + "Arm Versatile Express", + "1.0", + "System Serial#", + "System SKU#", + "edk2", + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE2 Board Information +************************************************************************/ +SMBIOS_TABLE_TYPE2 mBoardInfoType2 = { + { EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, sizeof (SMBIOS_TABLE_TYPE2), 0 }, + 1, // Manufacturer String + 2, // ProductName String + 3, // Version String + 4, // SerialNumber String + 5, // AssetTag String + { // FeatureFlag + 1, // Motherboard :1; + 0, // RequiresDaughterCard :1; + 0, // Removable :1; + 0, // Replaceable :1; + 0, // HotSwappable :1; + 0, // Reserved :3; + }, + 6, // LocationInChassis String + 0, // ChassisHandle; + BaseBoardTypeMotherBoard, // BoardType; + 0, // NumberOfContainedObjectHandles; + { 0 } // ContainedObjectHandles[1]; +}; +CHAR8 *mBoardInfoType2Strings[] = { + "ARM", + "Arm Versatile Express", + "1.0", + "Base Board Serial#", + "Base Board Asset Tag#", + "Part Component", + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE3 Enclosure Information +************************************************************************/ +SMBIOS_TABLE_TYPE3 mEnclosureInfoType3 = { + { EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, sizeof (SMBIOS_TABLE_TYPE3), 0 }, + 1, // Manufacturer String + MiscChassisTypeLapTop, // Type; + 2, // Version String + 3, // SerialNumber String + 4, // AssetTag String + ChassisStateSafe, // BootupState; + ChassisStateSafe, // PowerSupplyState; + ChassisStateSafe, // ThermalState; + ChassisSecurityStatusNone,// SecurityStatus; + { 0, 0, 0, 0 }, // OemDefined[4]; + 0, // Height; + 0, // NumberofPowerCords; + 0, // ContainedElementCount; + 0, // ContainedElementRecordLength; + { { 0 } }, // ContainedElements[1]; +}; +CHAR8 *mEnclosureInfoType3Strings[] = { + "ARM", + "1.0", + "Chassis Board Serial#", + "Chassis Board Asset Tag#", + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE4 Processor Information +************************************************************************/ +SMBIOS_TABLE_TYPE4 mProcessorInfoType4 = { + { EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, sizeof (SMBIOS_TABLE_TYPE4), 0}, + 1, // Socket String + ProcessorOther, // ProcessorType; ///< The enumeration value from PROCESSOR_TYPE_DATA. + ProcessorFamilyIndicatorFamily2, // ProcessorFamily; ///< The enumeration value from PROCESSOR_FAMILY2_DATA. + 2, // ProcessorManufacture String; + { // ProcessorId; + { // PROCESSOR_SIGNATURE + 0, // ProcessorSteppingId:4; + 0, // ProcessorModel: 4; + 0, // ProcessorFamily: 4; + 0, // ProcessorType: 2; + 0, // ProcessorReserved1: 2; + 0, // ProcessorXModel: 4; + 0, // ProcessorXFamily: 8; + 0, // ProcessorReserved2: 4; + }, + + { // PROCESSOR_FEATURE_FLAGS + 0, // ProcessorFpu :1; + 0, // ProcessorVme :1; + 0, // ProcessorDe :1; + 0, // ProcessorPse :1; + 0, // ProcessorTsc :1; + 0, // ProcessorMsr :1; + 0, // ProcessorPae :1; + 0, // ProcessorMce :1; + 0, // ProcessorCx8 :1; + 0, // ProcessorApic :1; + 0, // ProcessorReserved1 :1; + 0, // ProcessorSep :1; + 0, // ProcessorMtrr :1; + 0, // ProcessorPge :1; + 0, // ProcessorMca :1; + 0, // ProcessorCmov :1; + 0, // ProcessorPat :1; + 0, // ProcessorPse36 :1; + 0, // ProcessorPsn :1; + 0, // ProcessorClfsh :1; + 0, // ProcessorReserved2 :1; + 0, // ProcessorDs :1; + 0, // ProcessorAcpi :1; + 0, // ProcessorMmx :1; + 0, // ProcessorFxsr :1; + 0, // ProcessorSse :1; + 0, // ProcessorSse2 :1; + 0, // ProcessorSs :1; + 0, // ProcessorReserved3 :1; + 0, // ProcessorTm :1; + 0, // ProcessorReserved4 :2; + } + }, + 3, // ProcessorVersion String; + { // Voltage; + 1, // ProcessorVoltageCapability5V :1; + 1, // ProcessorVoltageCapability3_3V :1; + 1, // ProcessorVoltageCapability2_9V :1; + 0, // ProcessorVoltageCapabilityReserved :1; ///< Bit 3, must be zero. + 0, // ProcessorVoltageReserved :3; ///< Bits 4-6, must be zero. + 0 // ProcessorVoltageIndicateLegacy :1; + }, + 0, // ExternalClock; + 0, // MaxSpeed; + 0, // CurrentSpeed; + 0x41, // Status; + ProcessorUpgradeOther, // ProcessorUpgrade; ///< The enumeration value from PROCESSOR_UPGRADE. + 0, // L1CacheHandle; + 0, // L2CacheHandle; + 0, // L3CacheHandle; + 4, // SerialNumber; + 5, // AssetTag; + 6, // PartNumber; + 0, // CoreCount; + 0, // EnabledCoreCount; + 0, // ThreadCount; + 0, // ProcessorCharacteristics; + ProcessorFamilyARM, // ARM Processor Family; +}; + +CHAR8 *mProcessorInfoType4Strings[] = { + "Socket", + "ARM", + "v7", + "1.0", + "1.0", + "1.0", + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE7 Cache Information +************************************************************************/ +SMBIOS_TABLE_TYPE7 mCacheInfoType7 = { + { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE7), 0 }, + 1, // SocketDesignation String + 0x018A, // Cache Configuration + 0x00FF, // Maximum Size 256k + 0x00FF, // Install Size 256k + { // Supported SRAM Type + 0, //Other :1 + 0, //Unknown :1 + 0, //NonBurst :1 + 1, //Burst :1 + 0, //PiplelineBurst :1 + 1, //Synchronous :1 + 0, //Asynchronous :1 + 0 //Reserved :9 + }, + { // Current SRAM Type + 0, //Other :1 + 0, //Unknown :1 + 0, //NonBurst :1 + 1, //Burst :1 + 0, //PiplelineBurst :1 + 1, //Synchronous :1 + 0, //Asynchronous :1 + 0 //Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorMultiBit, // Error Correction Multi + CacheTypeUnknown, // System Cache Type + CacheAssociativity2Way // Associativity +}; +CHAR8 *mCacheInfoType7Strings[] = { + "Cache1", + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE9 System Slot Information +************************************************************************/ +SMBIOS_TABLE_TYPE9 mSysSlotInfoType9 = { + { EFI_SMBIOS_TYPE_SYSTEM_SLOTS, sizeof (SMBIOS_TABLE_TYPE9), 0 }, + 1, // SlotDesignation String + SlotTypeOther, // SlotType; ///< The enumeration value from MISC_SLOT_TYPE. + SlotDataBusWidthOther, // SlotDataBusWidth; ///< The enumeration value from MISC_SLOT_DATA_BUS_WIDTH. + SlotUsageAvailable, // CurrentUsage; ///< The enumeration value from MISC_SLOT_USAGE. + SlotLengthOther, // SlotLength; ///< The enumeration value from MISC_SLOT_LENGTH. + 0, // SlotID; + { // SlotCharacteristics1; + 1, // CharacteristicsUnknown :1; + 0, // Provides50Volts :1; + 0, // Provides33Volts :1; + 0, // SharedSlot :1; + 0, // PcCard16Supported :1; + 0, // CardBusSupported :1; + 0, // ZoomVideoSupported :1; + 0, // ModemRingResumeSupported:1; + }, + { // SlotCharacteristics2; + 0, // PmeSignalSupported :1; + 0, // HotPlugDevicesSupported :1; + 0, // SmbusSignalSupported :1; + 0, // Reserved :5; ///< Set to 0. + }, + 0, // SegmentGroupNum; + 0, // BusNum; + 0, // DevFuncNum; +}; +CHAR8 *mSysSlotInfoType9Strings[] = { + "SD Card", + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE16 Physical Memory ArrayInformation +************************************************************************/ +SMBIOS_TABLE_TYPE16 mPhyMemArrayInfoType16 = { + { EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, sizeof (SMBIOS_TABLE_TYPE16), 0 }, + MemoryArrayLocationSystemBoard, // Location; ///< The enumeration value from MEMORY_ARRAY_LOCATION. + MemoryArrayUseSystemMemory, // Use; ///< The enumeration value from MEMORY_ARRAY_USE. + MemoryErrorCorrectionUnknown, // MemoryErrorCorrection; ///< The enumeration value from MEMORY_ERROR_CORRECTION. + 0x80000000, // MaximumCapacity; + 0xFFFE, // MemoryErrorInformationHandle; + 1, // NumberOfMemoryDevices; + 0x3fffffffffffffffULL, // ExtendedMaximumCapacity; +}; +CHAR8 *mPhyMemArrayInfoType16Strings[] = { + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE17 Memory Device Information +************************************************************************/ +SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = { + { EFI_SMBIOS_TYPE_MEMORY_DEVICE, sizeof (SMBIOS_TABLE_TYPE17), 0 }, + 0, // MemoryArrayHandle; + 0xFFFE, // MemoryErrorInformationHandle; + 0xFFFF, // TotalWidth; + 0xFFFF, // DataWidth; + 0xFFFF, // Size; + MemoryFormFactorUnknown, // FormFactor; ///< The enumeration value from MEMORY_FORM_FACTOR. + 0xff, // DeviceSet; + 1, // DeviceLocator String + 2, // BankLocator String + MemoryTypeDram, // MemoryType; ///< The enumeration value from MEMORY_DEVICE_TYPE. + { // TypeDetail; + 0, // Reserved :1; + 0, // Other :1; + 1, // Unknown :1; + 0, // FastPaged :1; + 0, // StaticColumn :1; + 0, // PseudoStatic :1; + 0, // Rambus :1; + 0, // Synchronous :1; + 0, // Cmos :1; + 0, // Edo :1; + 0, // WindowDram :1; + 0, // CacheDram :1; + 0, // Nonvolatile :1; + 0, // Registered :1; + 0, // Unbuffered :1; + 0, // Reserved1 :1; + }, + 0, // Speed; + 3, // Manufacturer String + 0, // SerialNumber String + 0, // AssetTag String + 0, // PartNumber String + 0, // Attributes; + 0, // ExtendedSize; + 0, // ConfiguredMemoryClockSpeed; +}; +CHAR8 *mMemDevInfoType17Strings[] = { + "OS Virtual Memory", + "malloc", + "OSV", + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE19 Memory Array Mapped Address Information +************************************************************************/ +SMBIOS_TABLE_TYPE19 mMemArrMapInfoType19 = { + { EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, sizeof (SMBIOS_TABLE_TYPE19), 0 }, + 0x80000000, // StartingAddress; + 0xbfffffff, // EndingAddress; + 0, // MemoryArrayHandle; + 1, // PartitionWidth; + 0, // ExtendedStartingAddress; + 0, // ExtendedEndingAddress; +}; +CHAR8 *mMemArrMapInfoType19Strings[] = { + NULL +}; + +/*********************************************************************** + SMBIOS data definition TYPE32 Boot Information +************************************************************************/ +SMBIOS_TABLE_TYPE32 mBootInfoType32 = { + { EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, sizeof (SMBIOS_TABLE_TYPE32), 0 }, + { 0, 0, 0, 0, 0, 0 }, // Reserved[6]; + BootInformationStatusNoError // BootStatus +}; + +CHAR8 *mBootInfoType32Strings[] = { + NULL +}; + + +/** + + Create SMBIOS record. + + Converts a fixed SMBIOS structure and an array of pointers to strings into + an SMBIOS record where the strings are cat'ed on the end of the fixed record + and terminated via a double NULL and add to SMBIOS table. + + SMBIOS_TABLE_TYPE32 gSmbiosType12 = { + { EFI_SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS, sizeof (SMBIOS_TABLE_TYPE12), 0 }, + 1 // StringCount + }; + + CHAR8 *gSmbiosType12Strings[] = { + "Not Found", + NULL + }; + + ... + + LogSmbiosData ( + (EFI_SMBIOS_TABLE_HEADER*)&gSmbiosType12, + gSmbiosType12Strings + ); + + @param Template Fixed SMBIOS structure, required. + @param StringArray Array of strings to convert to an SMBIOS string pack. + NULL is OK. +**/ + +EFI_STATUS +EFIAPI +LogSmbiosData ( + IN EFI_SMBIOS_TABLE_HEADER *Template, + IN CHAR8 **StringPack + ) +{ + EFI_STATUS Status; + EFI_SMBIOS_PROTOCOL *Smbios; + EFI_SMBIOS_HANDLE SmbiosHandle; + EFI_SMBIOS_TABLE_HEADER *Record; + UINTN Index; + UINTN StringSize; + UINTN Size; + CHAR8 *Str; + + // + // Locate Smbios protocol. + // + Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID **)&Smbios); + + if (EFI_ERROR (Status)) { + return Status; + } + + // Calculate the size of the fixed record and optional string pack + + Size = Template->Length; + if (StringPack == NULL) { + // At least a double null is required + Size += 2; + } else { + for (Index = 0; StringPack[Index] != NULL; Index++) { + StringSize = AsciiStrSize (StringPack[Index]); + Size += StringSize; + } + if (StringPack[0] == NULL) { + // At least a double null is required + Size += 1; + } + + // Don't forget the terminating double null + Size += 1; + } + + // Copy over Template + Record = (EFI_SMBIOS_TABLE_HEADER *)AllocateZeroPool (Size); + if (Record == NULL) { + return EFI_OUT_OF_RESOURCES; + } + CopyMem (Record, Template, Template->Length); + + // Append string pack + Str = ((CHAR8 *)Record) + Record->Length; + + for (Index = 0; StringPack[Index] != NULL; Index++) { + StringSize = AsciiStrSize (StringPack[Index]); + CopyMem (Str, StringPack[Index], StringSize); + Str += StringSize; + } + + *Str = 0; + SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; + Status = Smbios->Add ( + Smbios, + gImageHandle, + &SmbiosHandle, + Record + ); + + ASSERT_EFI_ERROR (Status); + FreePool (Record); + return Status; +} + +/*********************************************************************** + SMBIOS data update TYPE0 BIOS Information +************************************************************************/ +VOID +BIOSInfoUpdateSmbiosType0 ( + VOID + ) +{ + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mBIOSInfoType0, mBIOSInfoType0Strings); +} + +/*********************************************************************** + SMBIOS data update TYPE1 System Information +************************************************************************/ +VOID +SysInfoUpdateSmbiosType1 ( + VOID + ) +{ + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mSysInfoType1, mSysInfoType1Strings); +} + +/*********************************************************************** + SMBIOS data update TYPE2 Board Information +************************************************************************/ +VOID +BoardInfoUpdateSmbiosType2 ( + VOID + ) +{ + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mBoardInfoType2, mBoardInfoType2Strings); +} + +/*********************************************************************** + SMBIOS data update TYPE3 Enclosure Information +************************************************************************/ +VOID +EnclosureInfoUpdateSmbiosType3 ( + VOID + ) +{ + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mEnclosureInfoType3, mEnclosureInfoType3Strings); +} + +/*********************************************************************** + SMBIOS data update TYPE4 Processor Information +************************************************************************/ +VOID +ProcessorInfoUpdateSmbiosType4 ( + IN UINTN MaxCpus + ) +{ + mProcessorInfoType4.CoreCount = (UINT8) MaxCpus; + mProcessorInfoType4.EnabledCoreCount = (UINT8) MaxCpus; + mProcessorInfoType4.ThreadCount = (UINT8) MaxCpus; + + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mProcessorInfoType4, mProcessorInfoType4Strings); +} + +/*********************************************************************** + SMBIOS data update TYPE7 Cache Information +************************************************************************/ +VOID +CacheInfoUpdateSmbiosType7 ( + VOID + ) +{ + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7, mCacheInfoType7Strings); +} + +/*********************************************************************** + SMBIOS data update TYPE9 System Slot Information +************************************************************************/ +VOID +SysSlotInfoUpdateSmbiosType9 ( + VOID + ) +{ + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mSysSlotInfoType9, mSysSlotInfoType9Strings); +} + +/*********************************************************************** + SMBIOS data update TYPE16 Physical Memory Array Information +************************************************************************/ +VOID +PhyMemArrayInfoUpdateSmbiosType16 ( + VOID + ) +{ + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mPhyMemArrayInfoType16, mPhyMemArrayInfoType16Strings); +} + +/*********************************************************************** + SMBIOS data update TYPE17 Memory Device Information +************************************************************************/ +VOID +MemDevInfoUpdateSmbiosType17 ( + VOID + ) +{ + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mMemDevInfoType17, mMemDevInfoType17Strings); +} + +/*********************************************************************** + SMBIOS data update TYPE19 Memory Array Map Information +************************************************************************/ +VOID +MemArrMapInfoUpdateSmbiosType19 ( + VOID + ) +{ + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mMemArrMapInfoType19, mMemArrMapInfoType19Strings); +} + + +/*********************************************************************** + SMBIOS data update TYPE32 Boot Information +************************************************************************/ +VOID +BootInfoUpdateSmbiosType32 ( + VOID + ) +{ + LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mBootInfoType32, mBootInfoType32Strings); +} + +/*********************************************************************** + Driver Entry +************************************************************************/ +EFI_STATUS +EFIAPI +PlatfomrSmbiosDriverEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + BIOSInfoUpdateSmbiosType0(); + + SysInfoUpdateSmbiosType1(); + + BoardInfoUpdateSmbiosType2(); + + EnclosureInfoUpdateSmbiosType3(); + + ProcessorInfoUpdateSmbiosType4 (4); //One example for creating and updating + + CacheInfoUpdateSmbiosType7(); + + SysSlotInfoUpdateSmbiosType9(); + + PhyMemArrayInfoUpdateSmbiosType16(); + + MemDevInfoUpdateSmbiosType17(); + + MemArrMapInfoUpdateSmbiosType19(); + + BootInfoUpdateSmbiosType32(); + + return EFI_SUCCESS; +} diff --git a/ArmPlatformPkg/PlatformSmbiosDxe/PlatformSmbiosDxe.inf b/ArmPlatformPkg/PlatformSmbiosDxe/PlatformSmbiosDxe.inf new file mode 100644 index 000000000..502aa2ea3 --- /dev/null +++ b/ArmPlatformPkg/PlatformSmbiosDxe/PlatformSmbiosDxe.inf @@ -0,0 +1,46 @@ +#/** @file +# SMBIOS Table for ARM platform +# +# Copyright (c) 2013 Linaro.org +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformSmbiosDxe + FILE_GUID = 3847D23F-1D95-4772-B60C-4BBFBC4D532F + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PlatfomrSmbiosDriverEntryPoint + +[Sources] + PlatformSmbiosDxe.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + MemoryAllocationLib + BaseMemoryLib + BaseLib + UefiLib + UefiDriverEntryPoint + DebugLib + +[Protocols] + gEfiSmbiosProtocolGuid # PROTOCOL SOMETIMES_CONSUMED + +[Guids] + +[Depex] + gEfiSmbiosProtocolGuid diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template index f99ddf60e..28493ad1e 100644 --- a/BaseTools/Conf/tools_def.template +++ b/BaseTools/Conf/tools_def.template @@ -5819,16 +5819,16 @@ RELEASE_ARMLINUXGCC_ARM_CC_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_ARM ######################
# AARCH64 64bit ARM GNU/Linux GCC (ARM Architecture 64)
-*_ARMLINUXGCC_AARCH64_ASLCC_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-gcc
-*_ARMLINUXGCC_AARCH64_ASLDLINK_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-ld
-*_ARMLINUXGCC_AARCH64_ASLPP_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-gcc
-
-*_ARMLINUXGCC_AARCH64_CC_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-gcc
-*_ARMLINUXGCC_AARCH64_SLINK_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-ar
-*_ARMLINUXGCC_AARCH64_DLINK_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-ld
-*_ARMLINUXGCC_AARCH64_ASM_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-as
-*_ARMLINUXGCC_AARCH64_PP_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-gcc
-*_ARMLINUXGCC_AARCH64_VFRPP_PATH = ENV(AARCH64LINUXGCC_TOOLS_PATH)aarch64-linux-gnu-gcc
+*_ARMLINUXGCC_AARCH64_ASLCC_PATH = ENV(CROSS_COMPILE)gcc +*_ARMLINUXGCC_AARCH64_ASLDLINK_PATH = ENV(CROSS_COMPILE)ld +*_ARMLINUXGCC_AARCH64_ASLPP_PATH = ENV(CROSS_COMPILE)gcc + +*_ARMLINUXGCC_AARCH64_CC_PATH = ENV(CROSS_COMPILE)gcc +*_ARMLINUXGCC_AARCH64_SLINK_PATH = ENV(CROSS_COMPILE)ar +*_ARMLINUXGCC_AARCH64_DLINK_PATH = ENV(CROSS_COMPILE)ld +*_ARMLINUXGCC_AARCH64_ASM_PATH = ENV(CROSS_COMPILE)as +*_ARMLINUXGCC_AARCH64_PP_PATH = ENV(CROSS_COMPILE)gcc +*_ARMLINUXGCC_AARCH64_VFRPP_PATH = ENV(CROSS_COMPILE)gcc #
# Use default values, or override in DSC file
diff --git a/EmbeddedPkg/Drivers/LAN91xDxe/LAN91xDxe.c b/EmbeddedPkg/Drivers/LAN91xDxe/LAN91xDxe.c new file mode 100644 index 000000000..d0def7277 --- /dev/null +++ b/EmbeddedPkg/Drivers/LAN91xDxe/LAN91xDxe.c @@ -0,0 +1,2233 @@ +/** @file +* SMSC LAN91x series Network Controller Driver. +* +* Copyright (c) 2013 Linaro.org +* +* Derived from the LAN9118 driver. Original sources +* Copyright (c) 2012-2013, ARM Limited. All rights reserved. +* +* This program and the accompanying materials are licensed and +* made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license +* may be found at: http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Uefi.h> +#include <Uefi/UefiSpec.h> +#include <Base.h> + +// Protocols used by this driver +#include <Protocol/SimpleNetwork.h> +#include <Protocol/ComponentName2.h> +#include <Protocol/PxeBaseCode.h> +#include <Protocol/DevicePath.h> + +// Libraries used by this driver +#include <Library/UefiLib.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/IoLib.h> +#include <Library/PcdLib.h> +#include <Library/NetLib.h> +#include <Library/DevicePathLib.h> + +// Hardware register definitions +#include "LAN91xDxeHw.h" + +// Debugging output options +//#define LAN91X_PRINT_REGISTERS 1 +//#define LAN91X_PRINT_PACKET_HEADERS 1 +//#define LAN91X_PRINT_RECEIVE_FILTERS 1 + +// Chip power-down option -- UNTESTED +//#define LAN91X_POWER_DOWN 1 + +/*--------------------------------------------------------------------------------------------------------------------- + + LAN91x Information Structure + +---------------------------------------------------------------------------------------------------------------------*/ +typedef struct _LAN91X_DRIVER { + // Driver signature + UINT32 Signature; + EFI_HANDLE ControllerHandle; + + // EFI SNP protocol instances + EFI_SIMPLE_NETWORK_PROTOCOL Snp; + EFI_SIMPLE_NETWORK_MODE SnpMode; + + // EFI Snp statistics instance + EFI_NETWORK_STATISTICS Stats; + + // Transmit Buffer recycle queue +#define TX_QUEUE_DEPTH 16 + VOID *TxQueue[TX_QUEUE_DEPTH]; + UINTN TxQueHead; + UINTN TxQueTail; + + // Register access variables + UINTN IoBase; // I/O Base Address + UINT8 Revision; // Chip Revision Number + INT8 PhyAd; // Phy Address + UINT8 BankSel; // Currently selected register bank + +} LAN91X_DRIVER; + +#define LAN91X_NO_PHY (-1) // PhyAd value if PHY not detected + +#define LAN91X_SIGNATURE SIGNATURE_32('S', 'M', '9', '1') +#define INSTANCE_FROM_SNP_THIS(a) CR(a, LAN91X_DRIVER, Snp, LAN91X_SIGNATURE) + +#define LAN91X_STALL 2 +#define LAN91X_MEMORY_ALLOC_POLLS 100 // Max times to poll for memory allocation +#define LAN91X_PKT_OVERHEAD 6 // Overhead bytes in packet buffer + +// Synchronization TPLs +#define LAN91X_TPL TPL_CALLBACK + +// Most common CRC32 Polynomial for little endian machines +#define CRC_POLYNOMIAL 0xEDB88320 + + +typedef struct { + MAC_ADDR_DEVICE_PATH Lan91x; + EFI_DEVICE_PATH_PROTOCOL End; +} LAN91X_DEVICE_PATH; + +LAN91X_DEVICE_PATH Lan91xPathTemplate = { + { + { + MESSAGING_DEVICE_PATH, MSG_MAC_ADDR_DP, + { (UINT8) (sizeof(MAC_ADDR_DEVICE_PATH)), (UINT8) ((sizeof(MAC_ADDR_DEVICE_PATH)) >> 8) } + }, + { { 0 } }, + 0 + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { sizeof(EFI_DEVICE_PATH_PROTOCOL), 0 } + } +}; + +// Chip ID numbers and name strings +#define CHIP_9192 3 +#define CHIP_9194 4 +#define CHIP_9195 5 +#define CHIP_9196 6 +#define CHIP_91100 7 +#define CHIP_91100FD 8 +#define CHIP_91111FD 9 + +STATIC CHAR16 CONST * CONST ChipIds[ 16 ] = { + NULL, NULL, NULL, + /* 3 */ L"SMC91C90/91C92", + /* 4 */ L"SMC91C94", + /* 5 */ L"SMC91C95", + /* 6 */ L"SMC91C96", + /* 7 */ L"SMC91C100", + /* 8 */ L"SMC91C100FD", + /* 9 */ L"SMC91C11xFD", + NULL, NULL, NULL, + NULL, NULL, NULL +}; + + +/* ------------------ TxBuffer Queue functions ------------------- */ + +#define TxQueNext(off) ((((off) + 1) >= TX_QUEUE_DEPTH) ? 0 : ((off) + 1)) + +STATIC +BOOLEAN +TxQueInsert ( + IN LAN91X_DRIVER *LanDriver, + IN VOID *Buffer + ) +{ + + if (TxQueNext (LanDriver->TxQueTail) == LanDriver->TxQueHead) { + return FALSE; + } + + LanDriver->TxQueue[LanDriver->TxQueTail] = Buffer; + LanDriver->TxQueTail = TxQueNext (LanDriver->TxQueTail); + + return TRUE; +} + +STATIC +VOID +*TxQueRemove ( + IN LAN91X_DRIVER *LanDriver + ) +{ + VOID *Buffer; + + if (LanDriver->TxQueTail == LanDriver->TxQueHead) { + return NULL; + } + + Buffer = LanDriver->TxQueue[LanDriver->TxQueHead]; + LanDriver->TxQueue[LanDriver->TxQueHead] = NULL; + LanDriver->TxQueHead = TxQueNext (LanDriver->TxQueHead); + + return Buffer; +} + +/* ------------------ MAC Address Hash Calculations ------------------- */ + +/* +** Generate a hash value from a multicast address +** +** This uses the Ethernet standard CRC32 algorithm +** +** INFO USED: +** 1: http://en.wikipedia.org/wiki/Cyclic_redundancy_check +** +** 2: http://www.erg.abdn.ac.uk/~gorry/eg3567/dl-pages/crc.html +** +** 3: http://en.wikipedia.org/wiki/Computation_of_CRC +*/ +STATIC +UINT32 +MulticastHash ( + IN EFI_MAC_ADDRESS *Mac, + IN UINT32 AddrLen + ) +{ + UINT32 Iter; + UINT32 Remainder; + UINT32 Crc32; + UINT8 *Addr; + + // 0xFFFFFFFF is standard seed for Ethernet + Remainder = 0xFFFFFFFF; + + // Generate the remainder byte-by-byte (LSB first) + Addr = &Mac->Addr[0]; + while (AddrLen-- > 0) { + Remainder ^= *Addr++; + for (Iter = 0; Iter < 8; ++Iter) { + // Check if exponent is set + if ((Remainder & 1) != 0) { + Remainder = (Remainder >> 1) ^ CRC_POLYNOMIAL; + } else { + Remainder = (Remainder >> 1) ^ 0; + } + } + } + + // Reverse the bits of the remainder + Crc32 = 0; + for (Iter = 0; Iter < 32; ++Iter) { + Crc32 <<= 1; + Crc32 |= Remainder & 1; + Remainder >>= 1; + } + return Crc32; +} + + +/* ---------------- Banked Register Operations ------------------ */ + +// Select the proper I/O bank +STATIC +VOID +SelectIoBank ( + LAN91X_DRIVER *LanDriver, + UINTN Register + ) +{ + UINT8 Bank; + + Bank = RegisterToBank (Register); + + // Select the proper I/O bank + if (LanDriver->BankSel != Bank) { + MmioWrite16 (LanDriver->IoBase + LAN91X_BANK_OFFSET, Bank); + LanDriver->BankSel = Bank; + } +} + +// Read a 16-bit I/O-space register +STATIC +UINT16 +ReadIoReg16 ( + LAN91X_DRIVER *LanDriver, + UINTN Register + ) +{ + UINT8 Offset; + + // Select the proper I/O bank + SelectIoBank (LanDriver, Register); + + // Read the requested register + Offset = RegisterToOffset (Register); + return MmioRead16 (LanDriver->IoBase + Offset); +} + +// Write a 16-bit I/O-space register +STATIC +UINT16 +WriteIoReg16 ( + LAN91X_DRIVER *LanDriver, + UINTN Register, + UINT16 Value + ) +{ + UINT8 Offset; + + // Select the proper I/O bank + SelectIoBank (LanDriver, Register); + + // Write the requested register + Offset = RegisterToOffset (Register); + return MmioWrite16 (LanDriver->IoBase + Offset, Value); +} + +// Read an 8-bit I/O-space register +STATIC +UINT8 +ReadIoReg8 ( + LAN91X_DRIVER *LanDriver, + UINTN Register + ) +{ + UINT8 Offset; + + // Select the proper I/O bank + SelectIoBank (LanDriver, Register); + + // Read the requested register + Offset = RegisterToOffset (Register); + return MmioRead8 (LanDriver->IoBase + Offset); +} + +// Write an 8-bit I/O-space register +STATIC +UINT8 +WriteIoReg8 ( + LAN91X_DRIVER *LanDriver, + UINTN Register, + UINT8 Value + ) +{ + UINT8 Offset; + + // Select the proper I/O bank + SelectIoBank (LanDriver, Register); + + // Write the requested register + Offset = RegisterToOffset (Register); + return MmioWrite8 (LanDriver->IoBase + Offset, Value); +} + + +/* ---------------- MII/PHY Access Operations ------------------ */ + +#define LAN91X_MDIO_STALL 1 + +STATIC +VOID +MdioOutput ( + LAN91X_DRIVER *LanDriver, + UINTN Bits, + UINT32 Value + ) +{ + UINT16 MgmtReg; + UINT32 Mask; + + MgmtReg = ReadIoReg16 (LanDriver, LAN91X_MGMT); + MgmtReg &= ~MGMT_MCLK; + MgmtReg |= MGMT_MDOE; + + for (Mask = (1 << (Bits - 1)); Mask != 0; Mask >>= 1) { + if ((Value & Mask) != 0) { + MgmtReg |= MGMT_MDO; + } else { + MgmtReg &= ~MGMT_MDO; + } + + WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg); + gBS->Stall (LAN91X_MDIO_STALL); + WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg | MGMT_MCLK); + gBS->Stall (LAN91X_MDIO_STALL); + } +} +#define PHY_OUTPUT_TIME (2 * LAN91X_MDIO_STALL) + +STATIC +UINT32 +MdioInput ( + LAN91X_DRIVER *LanDriver, + UINTN Bits + ) +{ + UINT16 MgmtReg; + UINT32 Mask; + UINT32 Value; + + MgmtReg = ReadIoReg16 (LanDriver, LAN91X_MGMT); + MgmtReg &= ~(MGMT_MDOE | MGMT_MCLK | MGMT_MDO); + WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg); + + Value = 0; + for (Mask = (1 << (Bits - 1)); Mask != 0; Mask >>= 1) { + if ((ReadIoReg16 (LanDriver, LAN91X_MGMT) & MGMT_MDI) != 0) { + Value |= Mask; + } + + WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg); + gBS->Stall (LAN91X_MDIO_STALL); + WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg | MGMT_MCLK); + gBS->Stall (LAN91X_MDIO_STALL); + } + + return Value; +} +#define PHY_INPUT_TIME (2 * LAN91X_MDIO_STALL) + +STATIC +VOID +MdioIdle ( + LAN91X_DRIVER *LanDriver + ) +{ + UINT16 MgmtReg; + + MgmtReg = ReadIoReg16 (LanDriver, LAN91X_MGMT); + MgmtReg &= ~(MGMT_MDOE | MGMT_MCLK | MGMT_MDO); + WriteIoReg16 (LanDriver, LAN91X_MGMT, MgmtReg); +} + +// Write to a PHY register +STATIC +VOID +WritePhyReg16 ( + LAN91X_DRIVER *LanDriver, + UINTN RegAd, + UINT16 Value + ) +{ + // Bit-bang the MII Serial Frame write operation + MdioOutput (LanDriver, 32, 0xffffffff); // Send 32 Ones as a preamble + MdioOutput (LanDriver, 2, 0x01); // Send Start (01) + MdioOutput (LanDriver, 2, 0x01); // Send Write (01) + MdioOutput (LanDriver, 5, LanDriver->PhyAd); // Send PHYAD[4:0] + MdioOutput (LanDriver, 5, RegAd); // Send REGAD[4:0] + MdioOutput (LanDriver, 2, 0x02); // Send TurnAround (10) + MdioOutput (LanDriver, 16, Value); // Write 16 data bits + + // Idle the MDIO bus + MdioIdle (LanDriver); +} +// Calculate approximate time to write a PHY register in microseconds +#define PHY_WRITE_TIME ((32 + 2 + 2 + 5 + 5 + 2 + 16) * PHY_OUTPUT_TIME) + +// Read from a PHY register +STATIC +UINT16 +ReadPhyReg16 ( + LAN91X_DRIVER *LanDriver, + UINTN RegAd + ) +{ + UINT32 Value; + + // Bit-bang the MII Serial Frame read operation + MdioOutput (LanDriver, 32, 0xffffffff); // Send 32 Ones as a preamble + MdioOutput (LanDriver, 2, 0x01); // Send Start (01) + MdioOutput (LanDriver, 2, 0x02); // Send Read (10) + MdioOutput (LanDriver, 5, LanDriver->PhyAd); // Send PHYAD[4:0] + MdioOutput (LanDriver, 5, RegAd); // Send REGAD[4:0] + + (VOID) MdioInput (LanDriver, 2); // Discard TurnAround bits + Value = MdioInput (LanDriver, 16); // Read 16 data bits + + // Idle the MDIO bus + MdioIdle (LanDriver); + + return (Value & 0xffff); +} +// Calculate approximate time to read a PHY register in microseconds +#define PHY_READ_TIME (((32 + 2 + 2 + 5 + 5) * PHY_OUTPUT_TIME) + \ + ((2 + 16) * PHY_INPUT_TIME)) + + +/* ---------------- Debug Functions ------------------ */ + +#ifdef LAN91X_PRINT_REGISTERS +STATIC +VOID +PrintIoRegisters ( + IN LAN91X_DRIVER *LanDriver + ) +{ + UINTN Bank; + UINTN Offset; + UINT16 Value; + + DEBUG((EFI_D_ERROR, "\nLAN91x I/O Register Dump:\n")); + + // Print currrent bank select register + Value = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET); + DEBUG((EFI_D_ERROR, " BankSel: %d Bank Register %04x (%d)\n", + LanDriver->BankSel, Value, Value & 0x0007)); + + // Print all I/O registers + for (Offset = 0; Offset < 0x0e; Offset += 2) { + DEBUG((EFI_D_ERROR, " %02x:", Offset)); + for (Bank = 0; Bank <= 3; ++Bank) { + DEBUG((EFI_D_ERROR, " %04x", ReadIoReg16 (LanDriver, MakeRegister (Bank, Offset)))); + } + DEBUG((EFI_D_ERROR, "\n")); + } +} + +STATIC +VOID +PrintPhyRegisters ( + IN LAN91X_DRIVER *LanDriver + ) +{ + UINTN RegNum; + + DEBUG((EFI_D_ERROR, "\nLAN91x Phy %d Register Dump:\n", LanDriver->PhyAd)); + + // Print all Phy registers + for (RegNum = 0; RegNum <= 5; ++RegNum) { + DEBUG((EFI_D_ERROR, " %2d: %04x\n", + RegNum, + ReadPhyReg16 (LanDriver, RegNum) + )); + } + for (RegNum = 16; RegNum <= 20; ++RegNum) { + DEBUG((EFI_D_ERROR, " %2d: %04x\n", + RegNum, + ReadPhyReg16 (LanDriver, RegNum) + )); + } +} +#endif + +#if LAN91X_PRINT_PACKET_HEADERS +STATIC +VOID +PrintIpDgram ( + IN CONST VOID *DstMac, + IN CONST VOID *SrcMac, + IN CONST VOID *Proto, + IN CONST VOID *IpDgram + ) +{ + CONST UINT8 *Ptr; + UINT16 SrcPort; + UINT16 DstPort; + + Ptr = DstMac; + DEBUG((EFI_D_ERROR, " Dst: %02x-%02x-%02x", + Ptr[0], Ptr[1], Ptr[2])); + DEBUG((EFI_D_ERROR, "-%02x-%02x-%02x", + Ptr[3], Ptr[4], Ptr[5])); + + Ptr = SrcMac; + DEBUG((EFI_D_ERROR, " Src: %02x-%02x-%02x", + Ptr[0], Ptr[1], Ptr[2])); + DEBUG((EFI_D_ERROR, "-%02x-%02x-%02x", + Ptr[3], Ptr[4], Ptr[5])); + + Ptr = Proto; + DEBUG((EFI_D_ERROR, " Proto: %02x%02x\n", + Ptr[0], Ptr[1])); + + Ptr = IpDgram; + switch (Ptr[9]) { + case EFI_IP_PROTO_ICMP: + DEBUG((EFI_D_ERROR, " ICMP")); + break; + case EFI_IP_PROTO_TCP: + DEBUG((EFI_D_ERROR, " TCP")); + break; + case EFI_IP_PROTO_UDP: + DEBUG((EFI_D_ERROR, " UDP")); + break; + default: + DEBUG((EFI_D_ERROR, " IpProto %d\n", Ptr[9])); + return; + } + + DEBUG((EFI_D_ERROR, " SrcIp: %d.%d.%d.%d", + Ptr[12], Ptr[13], Ptr[14], Ptr[15])); + DEBUG((EFI_D_ERROR, " DstIp: %d.%d.%d.%d", + Ptr[16], Ptr[17], Ptr[18], Ptr[19])); + + SrcPort = (Ptr[20] << 8) | Ptr[21]; + DstPort = (Ptr[22] << 8) | Ptr[23]; + DEBUG((EFI_D_ERROR, " SrcPort: %d DstPort: %d\n", SrcPort, DstPort)); +} +#endif + + +/* ---------------- PHY Management Operations ----------------- */ + +STATIC +EFI_STATUS +PhyDetect ( + IN LAN91X_DRIVER *LanDriver + ) +{ + UINT16 PhyId1; + UINT16 PhyId2; + + for (LanDriver->PhyAd = 0x1f; LanDriver->PhyAd >= 0 ; --LanDriver->PhyAd) { + PhyId1 = ReadPhyReg16 (LanDriver, PHY_INDEX_ID1); + PhyId2 = ReadPhyReg16 (LanDriver, PHY_INDEX_ID2); + + if ((PhyId1 != 0x0000) && (PhyId1 != 0xffff) && + (PhyId2 != 0x0000) && (PhyId2 != 0xffff)) { + if ((PhyId1 == 0x0016) && ((PhyId2 & 0xfff0) == 0xf840)) { + DEBUG((EFI_D_ERROR, "LAN91x: PHY type LAN83C183 (LAN91C111 Internal)\n")); + } else if ((PhyId1 == 0x0282) && ((PhyId2 & 0xfff0) == 0x1c50)) { + DEBUG((EFI_D_ERROR, "LAN91x: PHY type LAN83C180\n")); + } else { + DEBUG((EFI_D_ERROR, "LAN91x: PHY id %04x:%04x\n", PhyId1, PhyId2)); + } + return EFI_SUCCESS; + } + } + + DEBUG((EFI_D_ERROR, "LAN91x: PHY detection failed\n")); + return EFI_NO_MEDIA; +} + + +// Check the Link Status and take appropriate action +STATIC +BOOLEAN +CheckLinkStatus ( + IN LAN91X_DRIVER *LanDriver + ) +{ + UINT16 PhyStatus; + + // Get the PHY Status + PhyStatus = ReadPhyReg16 (LanDriver, PHY_INDEX_BASIC_STATUS); + + return (PhyStatus & PHYSTS_LINK_STS) != 0; +} + + +// Do auto-negotiation +STATIC +EFI_STATUS +PhyAutoNegotiate ( + IN LAN91X_DRIVER *LanDriver + ) +{ + UINTN Retries; + UINT16 PhyControl; + UINT16 PhyStatus; + UINT16 PhyAdvert; + + // If there isn't a PHY, don't try to reset it + if (LanDriver->PhyAd == LAN91X_NO_PHY) { + return EFI_SUCCESS; + } + + // Next check that auto-negotiation is supported + PhyStatus = ReadPhyReg16 (LanDriver, PHY_INDEX_BASIC_STATUS); + if ((PhyStatus & PHYSTS_AUTO_CAP) == 0) { + return EFI_SUCCESS; + } + + // Translate capabilities to advertise + PhyAdvert = PHYANA_CSMA; + + if ((PhyStatus & PHYSTS_10BASET_HDPLX) != 0) { + PhyAdvert |= PHYANA_10BASET; + } + if ((PhyStatus & PHYSTS_10BASET_FDPLX) != 0) { + PhyAdvert |= PHYANA_10BASETFD; + } + if ((PhyStatus & PHYSTS_100BASETX_HDPLX) != 0) { + PhyAdvert |= PHYANA_100BASETX; + } + if ((PhyStatus & PHYSTS_100BASETX_FDPLX) != 0) { + PhyAdvert |= PHYANA_100BASETXFD; + } + if ((PhyStatus & PHYSTS_100BASE_T4) != 0) { + PhyAdvert |= PHYANA_100BASET4; + } + + // Set the capabilities to advertise + WritePhyReg16 (LanDriver, PHY_INDEX_AUTO_NEG_ADVERT, PhyAdvert); + (VOID) ReadPhyReg16 (LanDriver, PHY_INDEX_AUTO_NEG_ADVERT); + + // Restart Auto-Negotiation + PhyControl = ReadPhyReg16 (LanDriver, PHY_INDEX_BASIC_CTRL); + PhyControl &= ~(PHYCR_SPEED_SEL | PHYCR_DUPLEX_MODE); + PhyControl |= PHYCR_AUTO_EN | PHYCR_RST_AUTO; + WritePhyReg16 (LanDriver, PHY_INDEX_BASIC_CTRL, PhyControl); + + // Wait up to 2 seconds for the process to complete + Retries = 2000000 / (PHY_READ_TIME + 100); + while ((ReadPhyReg16 (LanDriver, PHY_INDEX_BASIC_STATUS) & PHYSTS_AUTO_COMP) == 0) { + if (--Retries == 0) { + DEBUG((EFI_D_ERROR, "LAN91x: PHY auto-negotiation timed-out\n")); + return EFI_TIMEOUT; + } + gBS->Stall (100); + } + + return EFI_SUCCESS; +} + + +// Perform PHY software reset +STATIC +EFI_STATUS +PhySoftReset ( + IN LAN91X_DRIVER *LanDriver + ) +{ + UINTN Retries; + + // If there isn't a PHY, don't try to reset it + if (LanDriver->PhyAd == LAN91X_NO_PHY) { + return EFI_SUCCESS; + } + + // Request a PHY reset + WritePhyReg16 (LanDriver, PHY_INDEX_BASIC_CTRL, PHYCR_RESET); + + // The internal PHY will reset within 50ms. Allow 100ms. + Retries = 100000 / (PHY_READ_TIME + 100); + while (ReadPhyReg16 (LanDriver, PHY_INDEX_BASIC_CTRL) & PHYCR_RESET) { + if (--Retries == 0) { + DEBUG((EFI_D_ERROR, "LAN91x: PHY reset timed-out\n")); + return EFI_TIMEOUT; + } + gBS->Stall (100); + } + + return EFI_SUCCESS; +} + + +/* ---------------- General Operations ----------------- */ + +STATIC +EFI_MAC_ADDRESS +GetCurrentMacAddress ( + IN LAN91X_DRIVER *LanDriver + ) +{ + UINTN RegNum; + UINT8 *Addr; + EFI_MAC_ADDRESS MacAddress; + + SetMem (&MacAddress, sizeof(MacAddress), 0); + + Addr = &MacAddress.Addr[0]; + for (RegNum = LAN91X_IAR0; RegNum <= LAN91X_IAR5; ++RegNum) { + *Addr = ReadIoReg8 (LanDriver, RegNum); + ++Addr; + } + + return MacAddress; +} + +STATIC +EFI_STATUS +SetCurrentMacAddress ( + IN LAN91X_DRIVER *LanDriver, + IN EFI_MAC_ADDRESS *MacAddress + ) +{ + UINTN RegNum; + UINT8 *Addr; + + Addr = &MacAddress->Addr[0]; + for (RegNum = LAN91X_IAR0; RegNum <= LAN91X_IAR5; ++RegNum) { + WriteIoReg8 (LanDriver, RegNum, *Addr); + ++Addr; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +MmuOperation ( + IN LAN91X_DRIVER *LanDriver, + IN UINTN MmuOp + ) +{ + UINTN Polls; + + WriteIoReg16 (LanDriver, LAN91X_MMUCR, MmuOp); + Polls = 100; + while ((ReadIoReg16 (LanDriver, LAN91X_MMUCR) & MMUCR_BUSY) != 0) { + if (--Polls == 0) { + DEBUG((EFI_D_ERROR, "LAN91x: MMU operation %04x timed-out\n", MmuOp)); + return EFI_TIMEOUT; + } + gBS->Stall (LAN91X_STALL); + } + + return EFI_SUCCESS; +} + +// Read bytes from the DATA register +STATIC +EFI_STATUS +ReadIoData ( + IN LAN91X_DRIVER *LanDriver, + IN VOID *Buffer, + IN UINTN BufLen + ) +{ + UINT8 *Ptr; + + Ptr = Buffer; + for (; BufLen > 0; --BufLen) { + *Ptr = ReadIoReg8 (LanDriver, LAN91X_DATA0); + ++Ptr; + } + + return EFI_SUCCESS; +} + +// Write bytes to the DATA register +STATIC +EFI_STATUS +WriteIoData ( + IN LAN91X_DRIVER *LanDriver, + IN VOID *Buffer, + IN UINTN BufLen + ) +{ + UINT8 *Ptr; + + Ptr = Buffer; + for (; BufLen > 0; --BufLen) { + WriteIoReg8 (LanDriver, LAN91X_DATA0, *Ptr); + ++Ptr; + } + + return EFI_SUCCESS; +} + +// Disable the interface +STATIC +EFI_STATUS +ChipDisable ( + IN LAN91X_DRIVER *LanDriver + ) +{ +#ifdef LAN91X_POWER_DOWN + UINT16 Val16; +#endif + + // Stop Rx and Tx operations + WriteIoReg16 (LanDriver, LAN91X_RCR, RCR_CLEAR); + WriteIoReg16 (LanDriver, LAN91X_TCR, TCR_CLEAR); + +#ifdef LAN91X_POWER_DOWN + // Power-down the chip + Val16 = ReadIoReg16 (LanDriver, LAN91X_CR); + Val16 &= ~CR_EPH_POWER_EN; + WriteIoReg16 (LanDriver, LAN91X_CR, Val16); +#endif + + return EFI_SUCCESS; +} + +// Enable the interface +STATIC +EFI_STATUS +ChipEnable ( + IN LAN91X_DRIVER *LanDriver + ) +{ +#ifdef LAN91X_POWER_DOWN + UINT16 Val16; + + // Power-up the chip + Val16 = ReadIoReg16 (LanDriver, LAN91X_CR); + Val16 |= CR_EPH_POWER_EN; + WriteIoReg16 (LanDriver, LAN91X_CR, Val16); + gBS->Stall (LAN91X_STALL); +#endif + + // Start Rx and Tx operations + WriteIoReg16 (LanDriver, LAN91X_TCR, TCR_DEFAULT); + WriteIoReg16 (LanDriver, LAN91X_RCR, RCR_DEFAULT); + + return EFI_SUCCESS; +} + + +// Perform software reset on the LAN91x +STATIC +EFI_STATUS +SoftReset ( + IN LAN91X_DRIVER *LanDriver + ) +{ + UINT16 Val16; + + // Issue the reset + WriteIoReg16 (LanDriver, LAN91X_RCR, RCR_SOFT_RST); + gBS->Stall (LAN91X_STALL); + WriteIoReg16 (LanDriver, LAN91X_RCR, RCR_CLEAR); + + // Set the configuration register + WriteIoReg16 (LanDriver, LAN91X_CR, CR_DEFAULT); + gBS->Stall (LAN91X_STALL); + + // Stop Rx and Tx + WriteIoReg16 (LanDriver, LAN91X_RCR, RCR_CLEAR); + WriteIoReg16 (LanDriver, LAN91X_TCR, TCR_CLEAR); + + // Initialize the Control Register + Val16 = ReadIoReg16 (LanDriver, LAN91X_CTR); + Val16 |= CTR_AUTO_REL; + WriteIoReg16 (LanDriver, LAN91X_CTR, Val16); + + // Reset the MMU + MmuOperation (LanDriver, MMUCR_OP_RESET_MMU); + + return EFI_SUCCESS; +} + +/* +** Probe() +** +** Validate that there is a LAN91x device. +** +*/ +STATIC +EFI_STATUS +Probe ( + IN LAN91X_DRIVER *LanDriver + ) +{ + UINT16 Bank; + UINT16 Val16; + CHAR16 CONST *ChipId; + UINTN ResetTime; + + // First check that the Bank Select register is valid + Bank = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET); + if ((Bank & 0xff00) != 0x3300) { + DEBUG((EFI_D_ERROR, "LAN91x: signature error: expecting 33xx, read %04x\n", Bank)); + return EFI_DEVICE_ERROR; + } + + // Try reading the revision register next + LanDriver->BankSel = 0xff; + Val16 = ReadIoReg16 (LanDriver, LAN91X_REV); + + Bank = MmioRead16 (LanDriver->IoBase + LAN91X_BANK_OFFSET); + if ((Bank & 0xff03) != 0x3303) { + DEBUG((EFI_D_ERROR, "LAN91x: signature error: expecting 33x3, read %04x\n", Bank)); + return EFI_DEVICE_ERROR; + } + + // Validate the revision register + if ((Val16 & 0xff00) != 0x3300) { + DEBUG((EFI_D_ERROR, "LAN91x: revision error: expecting 33xx, read %04x\n", Val16)); + return EFI_DEVICE_ERROR; + } + + ChipId = ChipIds[(Val16 >> 4) & 0x0f]; + if (ChipId == NULL) { + DEBUG((EFI_D_ERROR, "LAN91x: unrecognized revision: %04x\n", Val16)); + return EFI_DEVICE_ERROR; + } + DEBUG((EFI_D_ERROR, "LAN91x: detected chip %s rev %d\n", ChipId, Val16 & 0xf)); + LanDriver->Revision = Val16 & 0xff; + + // Reload from EEPROM to get the hardware MAC address + WriteIoReg16 (LanDriver, LAN91X_CTR, CTR_RESERVED | CTR_RELOAD); + ResetTime = 1000; + while ((ReadIoReg16 (LanDriver, LAN91X_CTR) & CTR_RELOAD) != 0) { + if (--ResetTime == 0) { + DEBUG((EFI_D_ERROR, "LAN91x: reload from EEPROM timed-out\n")); + WriteIoReg16 (LanDriver, LAN91X_CTR, CTR_RESERVED); + return EFI_DEVICE_ERROR; + } + gBS->Stall (LAN91X_STALL); + } + + // Read and save the Permanent MAC Address + LanDriver->SnpMode.PermanentAddress = GetCurrentMacAddress (LanDriver); + LanDriver->SnpMode.CurrentAddress = LanDriver->SnpMode.PermanentAddress; + DEBUG((EFI_D_ERROR, //EFI_D_NET | EFI_D_INFO, + "LAN91x: HW MAC Address: %02x-%02x-%02x-%02x-%02x-%02x\n", + LanDriver->SnpMode.PermanentAddress.Addr[0], + LanDriver->SnpMode.PermanentAddress.Addr[1], + LanDriver->SnpMode.PermanentAddress.Addr[2], + LanDriver->SnpMode.PermanentAddress.Addr[3], + LanDriver->SnpMode.PermanentAddress.Addr[4], + LanDriver->SnpMode.PermanentAddress.Addr[5] + )); + + // Reset the device + SoftReset (LanDriver); + + // Try to detect a PHY + if (LanDriver->Revision > (CHIP_91100 << 4)) { + PhyDetect (LanDriver); + } else { + LanDriver->PhyAd = LAN91X_NO_PHY; + } + + return EFI_SUCCESS; +} + + + + +/*------------------ Simple Network Driver entry point functions ------------------*/ + +// Refer to the Simple Network Protocol section (21.1) +// in the UEFI 2.3.1 Specification for documentation. + +#define ReturnUnlock(s) do { Status = (s); goto exit_unlock; } while(0) + + +/* +** UEFI Start() function +** +*/ +EFI_STATUS +EFIAPI +SnpStart ( + IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp + ) +{ + EFI_SIMPLE_NETWORK_MODE *Mode; + EFI_TPL SavedTpl; + EFI_STATUS Status; + + // Check Snp instance + if (Snp == NULL) { + return EFI_INVALID_PARAMETER; + } + + // Serialize access to data and registers + SavedTpl = gBS->RaiseTPL (LAN91X_TPL); + Mode = Snp->Mode; + + // Check state of the driver + switch (Mode->State) { + case EfiSimpleNetworkStopped: + break; + case EfiSimpleNetworkStarted: + case EfiSimpleNetworkInitialized: + DEBUG((EFI_D_WARN, "LAN91x: Driver already started\n")); + ReturnUnlock (EFI_ALREADY_STARTED); + default: + DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n", + (UINTN)Snp->Mode->State)); + ReturnUnlock (EFI_DEVICE_ERROR); + } + + + // Change state + Mode->State = EfiSimpleNetworkStarted; + Status = EFI_SUCCESS; + + // Restore TPL and return +exit_unlock: + gBS->RestoreTPL (SavedTpl); + return Status; +} + +/* +** UEFI Stop() function +** +*/ +EFI_STATUS +EFIAPI +SnpStop ( + IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp + ) +{ + LAN91X_DRIVER *LanDriver; + EFI_TPL SavedTpl; + EFI_STATUS Status; + + // Check Snp Instance + if (Snp == NULL) { + return EFI_INVALID_PARAMETER; + } + + // Serialize access to data and registers + SavedTpl = gBS->RaiseTPL (LAN91X_TPL); + + // Check state of the driver + switch (Snp->Mode->State) { + case EfiSimpleNetworkStarted: + case EfiSimpleNetworkInitialized: + break; + case EfiSimpleNetworkStopped: + DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n")); + ReturnUnlock (EFI_NOT_STARTED); + default: + DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n", + (UINTN)Snp->Mode->State)); + ReturnUnlock (EFI_DEVICE_ERROR); + } + + // Find the LanDriver structure + LanDriver = INSTANCE_FROM_SNP_THIS(Snp); + + // Stop the Tx and Rx + ChipDisable (LanDriver); + + // Change the state + Snp->Mode->State = EfiSimpleNetworkStopped; + Status = EFI_SUCCESS; + + // Restore TPL and return +exit_unlock: + gBS->RestoreTPL (SavedTpl); + return Status; +} + +/* +** UEFI Initialize() function +** +*/ +EFI_STATUS +EFIAPI +SnpInitialize ( + IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp, + IN UINTN RxBufferSize OPTIONAL, + IN UINTN TxBufferSize OPTIONAL + ) +{ + LAN91X_DRIVER *LanDriver; + EFI_TPL SavedTpl; + EFI_STATUS Status; + + // Check Snp Instance + if (Snp == NULL) { + return EFI_INVALID_PARAMETER; + } + + // Serialize access to data and registers + SavedTpl = gBS->RaiseTPL (LAN91X_TPL); + + // Check that driver was started but not initialised + switch (Snp->Mode->State) { + case EfiSimpleNetworkStarted: + break; + case EfiSimpleNetworkInitialized: + DEBUG((EFI_D_WARN, "LAN91x: Driver already initialized\n")); + ReturnUnlock (EFI_SUCCESS); + case EfiSimpleNetworkStopped: + DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n")); + ReturnUnlock (EFI_NOT_STARTED); + default: + DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n", + (UINTN)Snp->Mode->State)); + ReturnUnlock (EFI_DEVICE_ERROR); + } + + // Find the LanDriver structure + LanDriver = INSTANCE_FROM_SNP_THIS(Snp); + + // Initiate a software reset + Status = SoftReset (LanDriver); + if (EFI_ERROR(Status)) { + DEBUG((EFI_D_WARN, "LAN91x: Soft reset failed\n")); + ReturnUnlock (EFI_DEVICE_ERROR); + } + + // Initiate a PHY reset + if (PhySoftReset (LanDriver) < 0) { + Snp->Mode->State = EfiSimpleNetworkStopped; + DEBUG((EFI_D_WARN, "LAN91x: PHY soft reset timeout\n")); + ReturnUnlock (EFI_NOT_STARTED); + } + + // Do auto-negotiation + Status = PhyAutoNegotiate (LanDriver); + if (EFI_ERROR(Status)) { + DEBUG((EFI_D_WARN, "LAN91x: PHY auto-negotiation failed\n")); + } + + // Enable the receiver and transmitter + ChipEnable (LanDriver); + + // Now acknowledge all interrupts + WriteIoReg8 (LanDriver, LAN91X_IST, 0xFF); + + // Declare the driver as initialized + Snp->Mode->State = EfiSimpleNetworkInitialized; + Status = EFI_SUCCESS; + + // Restore TPL and return +exit_unlock: + gBS->RestoreTPL (SavedTpl); + return Status; +} + +/* +** UEFI Reset () function +** +*/ +EFI_STATUS +EFIAPI +SnpReset ( + IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp, + IN BOOLEAN Verification + ) +{ + LAN91X_DRIVER *LanDriver; + EFI_TPL SavedTpl; + EFI_STATUS Status; + + // Check Snp Instance + if (Snp == NULL) { + return EFI_INVALID_PARAMETER; + } + + // Serialize access to data and registers + SavedTpl = gBS->RaiseTPL (LAN91X_TPL); + + // Check that driver was started and initialised + switch (Snp->Mode->State) { + case EfiSimpleNetworkInitialized: + break; + case EfiSimpleNetworkStarted: + DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n")); + ReturnUnlock (EFI_DEVICE_ERROR); + case EfiSimpleNetworkStopped: + DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n")); + ReturnUnlock (EFI_NOT_STARTED); + default: + DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n", + (UINTN)Snp->Mode->State)); + ReturnUnlock (EFI_DEVICE_ERROR); + } + + // Find the LanDriver structure + LanDriver = INSTANCE_FROM_SNP_THIS(Snp); + + // Initiate a software reset + if (EFI_ERROR (SoftReset (LanDriver))) { + DEBUG((EFI_D_WARN, "LAN91x: Soft reset failed\n")); + ReturnUnlock (EFI_DEVICE_ERROR); + } + + // Initiate a PHY reset + if (EFI_ERROR (PhySoftReset (LanDriver))) { + DEBUG((EFI_D_WARN, "LAN91x: PHY soft reset failed\n")); + ReturnUnlock (EFI_DEVICE_ERROR); + } + + // Enable the receiver and transmitter + Status = ChipEnable (LanDriver); + + // Restore TPL and return +exit_unlock: + gBS->RestoreTPL (SavedTpl); + return Status; +} + +/* +** UEFI Shutdown () function +** +*/ +EFI_STATUS +EFIAPI +SnpShutdown ( + IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp + ) +{ + LAN91X_DRIVER *LanDriver; + EFI_TPL SavedTpl; + EFI_STATUS Status; + + // Check Snp Instance + if (Snp == NULL) { + return EFI_INVALID_PARAMETER; + } + + // Serialize access to data and registers + SavedTpl = gBS->RaiseTPL (LAN91X_TPL); + + // First check that driver has already been initialized + switch (Snp->Mode->State) { + case EfiSimpleNetworkInitialized: + break; + case EfiSimpleNetworkStarted: + DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n")); + ReturnUnlock (EFI_DEVICE_ERROR); + case EfiSimpleNetworkStopped: + DEBUG((EFI_D_WARN, "LAN91x: Driver in stopped state\n")); + ReturnUnlock (EFI_NOT_STARTED); + default: + DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n", + (UINTN)Snp->Mode->State)); + ReturnUnlock (EFI_DEVICE_ERROR); + } + + // Find the LanDriver structure + LanDriver = INSTANCE_FROM_SNP_THIS(Snp); + + // Disable the interface + Status = ChipDisable (LanDriver); + + // Restore TPL and return +exit_unlock: + gBS->RestoreTPL (SavedTpl); + return Status; +} + + +/* +** UEFI ReceiveFilters() function +** +*/ +EFI_STATUS +EFIAPI +SnpReceiveFilters ( + IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp, + IN UINT32 Enable, + IN UINT32 Disable, + IN BOOLEAN Reset, + IN UINTN NumMfilter OPTIONAL, + IN EFI_MAC_ADDRESS *Mfilter OPTIONAL + ) +{ +#define MCAST_HASH_BYTES 8 + + LAN91X_DRIVER *LanDriver; + EFI_SIMPLE_NETWORK_MODE *SnpMode; + EFI_TPL SavedTpl; + EFI_STATUS Status; + UINTN i; + UINT32 Crc; + UINT16 RcvCtrl; + UINT8 McastHash[MCAST_HASH_BYTES]; + + // Check Snp Instance + if (Snp == NULL) { + return EFI_INVALID_PARAMETER; + } + + // Serialize access to data and registers + SavedTpl = gBS->RaiseTPL (LAN91X_TPL); + + // First check that driver has already been initialized + switch (Snp->Mode->State) { + case EfiSimpleNetworkInitialized: + break; + case EfiSimpleNetworkStarted: + DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n")); + ReturnUnlock (EFI_DEVICE_ERROR); + case EfiSimpleNetworkStopped: + DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n")); + ReturnUnlock (EFI_NOT_STARTED); + default: + DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n", + (UINTN)Snp->Mode->State)); + ReturnUnlock (EFI_DEVICE_ERROR); + } + + // Find the LanDriver structure + LanDriver = INSTANCE_FROM_SNP_THIS(Snp); + SnpMode = Snp->Mode; + +#ifdef LAN91X_PRINT_RECEIVE_FILTERS + DEBUG((EFI_D_ERROR, "LAN91x:SnpReceiveFilters()\n")); + DEBUG((EFI_D_ERROR, " Enable = %08x\n", Enable)); + DEBUG((EFI_D_ERROR, " Disable = %08x\n", Disable)); + DEBUG((EFI_D_ERROR, " Reset = %d\n", Reset)); + DEBUG((EFI_D_ERROR, " NumMfilter = %d\n", NumMfilter)); + for (i = 0; i < NumMfilter; ++i) { + DEBUG((EFI_D_ERROR, + " [%2d] = %02x-%02x-%02x-%02x-%02x-%02x\n", + i, + Mfilter[i].Addr[0], + Mfilter[i].Addr[1], + Mfilter[i].Addr[2], + Mfilter[i].Addr[3], + Mfilter[i].Addr[4], + Mfilter[i].Addr[5])); + } +#endif + + // Update the Multicast Hash registers + if (Reset) { + // Clear the hash table + SetMem (McastHash, MCAST_HASH_BYTES, 0); + SnpMode->MCastFilterCount = 0; + } else { + // Read the current hash table + for (i = 0; i < MCAST_HASH_BYTES; ++i) { + McastHash[i] = ReadIoReg8 (LanDriver, LAN91X_MT0 + i); + } + // Set the new additions + for (i = 0; i < NumMfilter; ++i) { + Crc = MulticastHash (&Mfilter[i], NET_ETHER_ADDR_LEN); + McastHash[(Crc >> 29) & 0x3] |= 1 << ((Crc >> 26) & 0x3); + } + SnpMode->MCastFilterCount = NumMfilter; + } + // If the hash registers need updating, write them + if (Reset || NumMfilter > 0) { + for (i = 0; i < MCAST_HASH_BYTES; ++i) { + WriteIoReg8 (LanDriver, LAN91X_MT0 + i, McastHash[i]); + } + } + + RcvCtrl = ReadIoReg16 (LanDriver, LAN91X_RCR); + if ((Enable & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS) != 0) { + RcvCtrl |= RCR_PRMS; + SnpMode->ReceiveFilterSetting |= EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS; + } + if ((Disable & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS) != 0) { + RcvCtrl &= ~RCR_PRMS; + SnpMode->ReceiveFilterSetting &= ~EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS; + } + + if ((Enable & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST) != 0) { + RcvCtrl |= RCR_ALMUL; + SnpMode->ReceiveFilterSetting |= EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST; + } + if ((Disable & EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST) != 0) { + RcvCtrl &= ~RCR_ALMUL; + SnpMode->ReceiveFilterSetting &= ~EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST; + } + WriteIoReg16 (LanDriver, LAN91X_RCR, RcvCtrl); + + Status = SetCurrentMacAddress (LanDriver, &SnpMode->CurrentAddress); + + // Restore TPL and return +exit_unlock: + gBS->RestoreTPL (SavedTpl); + return Status; +} + +/* +** UEFI StationAddress() function +** +*/ +EFI_STATUS +EFIAPI +SnpStationAddress ( + IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp, + IN BOOLEAN Reset, + IN EFI_MAC_ADDRESS *NewMac +) +{ + LAN91X_DRIVER *LanDriver; + EFI_TPL SavedTpl; + EFI_STATUS Status; + + // Check Snp instance + if (Snp == NULL) { + return EFI_INVALID_PARAMETER; + } + + // Serialize access to data and registers + SavedTpl = gBS->RaiseTPL (LAN91X_TPL); + + // Check that driver was started and initialised + switch (Snp->Mode->State) { + case EfiSimpleNetworkInitialized: + break; + case EfiSimpleNetworkStarted: + DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n")); + ReturnUnlock (EFI_DEVICE_ERROR); + case EfiSimpleNetworkStopped: + DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n")); + ReturnUnlock (EFI_NOT_STARTED); + default: + DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n", + (UINTN)Snp->Mode->State)); + ReturnUnlock (EFI_DEVICE_ERROR); + } + + // Find the LanDriver structure + LanDriver = INSTANCE_FROM_SNP_THIS(Snp); + + if (Reset) { + Snp->Mode->CurrentAddress = Snp->Mode->PermanentAddress; + } else { + if (NewMac == NULL) { + ReturnUnlock (EFI_INVALID_PARAMETER); + } + Snp->Mode->CurrentAddress = *NewMac; + } + + Status = SetCurrentMacAddress (LanDriver, &Snp->Mode->CurrentAddress); + + // Restore TPL and return +exit_unlock: + gBS->RestoreTPL (SavedTpl); + return Status; +} + +/* +** UEFI Statistics() function +** +*/ +EFI_STATUS +EFIAPI +SnpStatistics ( + IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp, + IN BOOLEAN Reset, + IN OUT UINTN *StatSize, + OUT EFI_NETWORK_STATISTICS *Statistics + ) +{ + LAN91X_DRIVER *LanDriver; + EFI_TPL SavedTpl; + EFI_STATUS Status; + + // Check Snp instance + if (Snp == NULL) { + return EFI_INVALID_PARAMETER; + } + + // Check pointless condition + if ((!Reset) && (StatSize == NULL) && (Statistics == NULL)) { + return EFI_SUCCESS; + } + + // Check the parameters + if ((StatSize == NULL) && (Statistics != NULL)) { + return EFI_INVALID_PARAMETER; + } + + // Serialize access to data and registers + SavedTpl = gBS->RaiseTPL (LAN91X_TPL); + + // Check that driver was started and initialised + switch (Snp->Mode->State) { + case EfiSimpleNetworkInitialized: + break; + case EfiSimpleNetworkStarted: + DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n")); + ReturnUnlock (EFI_DEVICE_ERROR); + case EfiSimpleNetworkStopped: + DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n")); + ReturnUnlock (EFI_NOT_STARTED); + default: + DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n", + (UINTN)Snp->Mode->State)); + ReturnUnlock (EFI_DEVICE_ERROR); + } + + // Find the LanDriver structure + LanDriver = INSTANCE_FROM_SNP_THIS(Snp); + + // Do a reset if required + if (Reset) { + ZeroMem (&LanDriver->Stats, sizeof(EFI_NETWORK_STATISTICS)); + } + + // Check buffer size + if (*StatSize < sizeof(EFI_NETWORK_STATISTICS)) { + *StatSize = sizeof(EFI_NETWORK_STATISTICS); + ReturnUnlock (EFI_BUFFER_TOO_SMALL); + goto exit_unlock; + } + + // Fill in the statistics + CopyMem(&Statistics, &LanDriver->Stats, sizeof(EFI_NETWORK_STATISTICS)); + Status = EFI_SUCCESS; + + // Restore TPL and return +exit_unlock: + gBS->RestoreTPL (SavedTpl); + return Status; +} + +/* +** UEFI MCastIPtoMAC() function +** +*/ +EFI_STATUS +EFIAPI +SnpMcastIptoMac ( + IN EFI_SIMPLE_NETWORK_PROTOCOL* Snp, + IN BOOLEAN IsIpv6, + IN EFI_IP_ADDRESS *Ip, + OUT EFI_MAC_ADDRESS *McastMac + ) +{ + // Check Snp instance + if (Snp == NULL) { + return EFI_INVALID_PARAMETER; + } + + // Check parameters + if ((McastMac == NULL) || (Ip == NULL)) { + return EFI_INVALID_PARAMETER; + } + + // Make sure MAC address is empty + ZeroMem (McastMac, sizeof(EFI_MAC_ADDRESS)); + + // If we need ipv4 address + if (!IsIpv6) { + // Most significant 25 bits of a multicast HW address are set + McastMac->Addr[0] = 0x01; + McastMac->Addr[1] = 0x00; + McastMac->Addr[2] = 0x5E; + + // Lower 23 bits from ipv4 address + McastMac->Addr[3] = (Ip->v4.Addr[1] & 0x7F); // Clear the ms bit (25th bit of MAC must be 0) + McastMac->Addr[4] = Ip->v4.Addr[2]; + McastMac->Addr[5] = Ip->v4.Addr[3]; + } else { + // Most significant 16 bits of multicast v6 HW address are set + McastMac->Addr[0] = 0x33; + McastMac->Addr[1] = 0x33; + + // lower four octets are taken from ipv6 address + McastMac->Addr[2] = Ip->v6.Addr[8]; + McastMac->Addr[3] = Ip->v6.Addr[9]; + McastMac->Addr[4] = Ip->v6.Addr[10]; + McastMac->Addr[5] = Ip->v6.Addr[11]; + } + + return EFI_SUCCESS; +} + +/* +** UEFI NvData() function +** +*/ +EFI_STATUS +EFIAPI +SnpNvData ( + IN EFI_SIMPLE_NETWORK_PROTOCOL* pobj, + IN BOOLEAN read_write, + IN UINTN offset, + IN UINTN buff_size, + IN OUT VOID *data + ) +{ + DEBUG((EFI_D_ERROR, "LAN91x: Non-volatile storage not supported\n")); + + return EFI_UNSUPPORTED; +} + + +/* +** UEFI GetStatus () function +** +*/ +EFI_STATUS +EFIAPI +SnpGetStatus ( + IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp, + OUT UINT32 *IrqStat OPTIONAL, + OUT VOID **TxBuff OPTIONAL + ) +{ + LAN91X_DRIVER *LanDriver; + EFI_TPL SavedTpl; + EFI_STATUS Status; + BOOLEAN MediaPresent; + UINT8 IstReg; + + // Check preliminaries + if (Snp == NULL) { + return EFI_INVALID_PARAMETER; + } + + // Serialize access to data and registers + SavedTpl = gBS->RaiseTPL (LAN91X_TPL); + + // Check that driver was started and initialised + switch (Snp->Mode->State) { + case EfiSimpleNetworkInitialized: + break; + case EfiSimpleNetworkStarted: + DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n")); + ReturnUnlock (EFI_DEVICE_ERROR); + case EfiSimpleNetworkStopped: + DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n")); + ReturnUnlock (EFI_NOT_STARTED); + default: + DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n", + (UINTN)Snp->Mode->State)); + ReturnUnlock (EFI_DEVICE_ERROR); + } + + // Find the LanDriver structure + LanDriver = INSTANCE_FROM_SNP_THIS(Snp); + + // Arbitrarily set the interrupt status to 0 + if (IrqStat != NULL) { + *IrqStat = 0; + IstReg = ReadIoReg8 (LanDriver, LAN91X_IST); + if ((IstReg & IST_RCV) != 0) { + *IrqStat |= EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT; + } + if ((IstReg & IST_TX) != 0) { + *IrqStat |= EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT; + } + } + + // Pass back the completed buffer address + if (TxBuff != NULL) { + *TxBuff = TxQueRemove (LanDriver); + } + + // Update the media status + MediaPresent = CheckLinkStatus (LanDriver); + if (MediaPresent != Snp->Mode->MediaPresent) { + DEBUG((EFI_D_WARN, "LAN91x: Link %s\n", MediaPresent ? L"up" : L"down")); + } + Snp->Mode->MediaPresent = MediaPresent; + Status = EFI_SUCCESS; + + // Restore TPL and return +exit_unlock: + gBS->RestoreTPL (SavedTpl); + return Status; +} + + +/* +** UEFI Transmit() function +** +*/ +EFI_STATUS +EFIAPI +SnpTransmit ( + IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp, + IN UINTN HdrSize, + IN UINTN BufSize, + IN VOID *BufAddr, + IN EFI_MAC_ADDRESS *SrcAddr OPTIONAL, + IN EFI_MAC_ADDRESS *DstAddr OPTIONAL, + IN UINT16 *Protocol OPTIONAL + ) +{ + LAN91X_DRIVER *LanDriver; + EFI_TPL SavedTpl; + EFI_STATUS Status; + UINT8 *Ptr; + UINTN Len; + UINTN MmuPages; + UINTN Retries; + UINT16 Proto; + UINT8 PktNum; + + // Check preliminaries + if ((Snp == NULL) || (BufAddr == NULL)) { + DEBUG((EFI_D_ERROR, "LAN91x: SnpTransmit(): NULL Snp (%p) or BufAddr (%p)\n", + Snp, BufAddr)); + return EFI_INVALID_PARAMETER; + } + + // Serialize access to data and registers + SavedTpl = gBS->RaiseTPL (LAN91X_TPL); + + // Check that driver was started and initialised + switch (Snp->Mode->State) { + case EfiSimpleNetworkInitialized: + break; + case EfiSimpleNetworkStarted: + DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n")); + ReturnUnlock (EFI_DEVICE_ERROR); + case EfiSimpleNetworkStopped: + DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n")); + ReturnUnlock (EFI_NOT_STARTED); + default: + DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n", + (UINTN)Snp->Mode->State)); + ReturnUnlock (EFI_DEVICE_ERROR); + } + + // Find the LanDriver structure + LanDriver = INSTANCE_FROM_SNP_THIS(Snp); + + // Ensure header is correct size if non-zero + if (HdrSize != 0) { + if (HdrSize != Snp->Mode->MediaHeaderSize) { + DEBUG((EFI_D_ERROR, "LAN91x: SnpTransmit(): Invalid HdrSize %d\n", HdrSize)); + ReturnUnlock (EFI_INVALID_PARAMETER); + } + + if ((DstAddr == NULL) || (Protocol == NULL)) { + DEBUG((EFI_D_ERROR, "LAN91x: SnpTransmit(): NULL DstAddr %p or Protocol %p\n", + DstAddr, Protocol)); + ReturnUnlock (EFI_INVALID_PARAMETER); + } + } + + // Before transmitting check the link status + if (!Snp->Mode->MediaPresent) { + DEBUG((EFI_D_WARN, "LAN91x: SnpTransmit(): Link not ready\n")); + ReturnUnlock (EFI_NOT_READY); + } + + // Calculate the request size in 256-byte "pages" minus 1 + // The 91C111 ignores this, but some older devices need it. + MmuPages = ((BufSize & ~1) + LAN91X_PKT_OVERHEAD - 1) >> 8; + if (MmuPages > 7) { + DEBUG((EFI_D_WARN, "LAN91x: Tx buffer too large (%d bytes)\n", BufSize)); + LanDriver->Stats.TxOversizeFrames += 1; + LanDriver->Stats.TxDroppedFrames += 1; + ReturnUnlock (EFI_BAD_BUFFER_SIZE); + } + + // Request allocation of a transmit buffer + Status = MmuOperation (LanDriver, MMUCR_OP_TX_ALLOC | MmuPages); + if (EFI_ERROR (Status)) { + DEBUG((EFI_D_ERROR, "LAN91x: Tx buffer request failure: %d\n", Status)); + ReturnUnlock (EFI_DEVICE_ERROR); + } + + // Wait for allocation request completion + Retries = LAN91X_MEMORY_ALLOC_POLLS; + while ((ReadIoReg8 (LanDriver, LAN91X_IST) & IST_ALLOC) == 0) { + if (--Retries == 0) { + DEBUG((EFI_D_ERROR, "LAN91x: Tx buffer allocation timeout\n")); + ReturnUnlock (EFI_TIMEOUT); + } + } + + // Check for successful allocation + PktNum = ReadIoReg8 (LanDriver, LAN91X_ARR); + if ((PktNum & ARR_FAILED) != 0) { + DEBUG((EFI_D_ERROR, "LAN91x: Tx buffer allocation failure: %02x\n", PktNum)); + ReturnUnlock (EFI_NOT_READY); + } + PktNum &= ARR_PACKET; + + // Check for the nature of the frame + if (DstAddr->Addr[0] == 0xFF) { + LanDriver->Stats.TxBroadcastFrames += 1; + } else if ((DstAddr->Addr[0] & 0x1) == 1) { + LanDriver->Stats.TxMulticastFrames += 1; + } else { + LanDriver->Stats.TxUnicastFrames += 1; + } + + // Set the Packet Number and Pointer registers + WriteIoReg8 (LanDriver, LAN91X_PNR, PktNum); + WriteIoReg16 (LanDriver, LAN91X_PTR, PTR_AUTO_INCR); + + // Set up mutable buffer information variables + Ptr = BufAddr; + Len = BufSize; + + // Write Status and Byte Count first + WriteIoReg16 (LanDriver, LAN91X_DATA0, 0); + WriteIoReg16 (LanDriver, LAN91X_DATA0, (Len + LAN91X_PKT_OVERHEAD) & BCW_COUNT); + + // This packet may come with a preconfigured Ethernet header. + // If not, we need to construct one from optional parameters. + if (HdrSize) { + + // Write the destination address + WriteIoData (LanDriver, DstAddr, NET_ETHER_ADDR_LEN); + + // Write the Source Address + if (SrcAddr != NULL) { + WriteIoData (LanDriver, SrcAddr, NET_ETHER_ADDR_LEN); + } else { + WriteIoData (LanDriver, &LanDriver->SnpMode.CurrentAddress, NET_ETHER_ADDR_LEN); + } + + // Write the Protocol word + Proto = HTONS (*Protocol); + WriteIoReg16 (LanDriver, LAN91X_DATA0, Proto); + + // Adjust the data start and length + Ptr += sizeof(ETHER_HEAD); + Len -= sizeof(ETHER_HEAD); + } + + // Copy the remainder data buffer, except the odd byte + WriteIoData (LanDriver, Ptr, Len & ~1); + Ptr += Len & ~1; + Len &= 1; + + // Write the Packet Control Word and odd byte + WriteIoReg16 (LanDriver, LAN91X_DATA0, + (Len != 0) ? (PCW_ODD | PCW_CRC | *Ptr) : PCW_CRC); + + // Release the packet for transmission + Status = MmuOperation (LanDriver, MMUCR_OP_TX_PUSH); + if (EFI_ERROR (Status)) { + DEBUG((EFI_D_ERROR, "LAN91x: Tx buffer release failure: %d\n", Status)); + ReturnUnlock (EFI_DEVICE_ERROR); + } + + // Update the Rx statistics + LanDriver->Stats.TxTotalBytes += BufSize; + LanDriver->Stats.TxGoodFrames += 1; + + // Update the Tx Buffer cache + if (!TxQueInsert (LanDriver, BufAddr)) { + DEBUG((EFI_D_WARN, "LAN91x: SnpTransmit(): TxQueue insert failure.\n")); + } + Status = EFI_SUCCESS; + + // Dump the packet header +#if LAN91X_PRINT_PACKET_HEADERS + Ptr = BufAddr; + DEBUG((EFI_D_ERROR, "LAN91X:SnpTransmit()\n")); + DEBUG((EFI_D_ERROR, " HdrSize: %d, SrcAddr: %p, Length: %d, Last byte: %02x\n", + HdrSize, SrcAddr, BufSize, Ptr[BufSize - 1])); + PrintIpDgram ( + (HdrSize == 0) ? (EFI_MAC_ADDRESS *)&Ptr[0] : DstAddr, + (HdrSize == 0) ? (EFI_MAC_ADDRESS *)&Ptr[6] : (SrcAddr != NULL) ? SrcAddr : &LanDriver->SnpMode.CurrentAddress, + (HdrSize == 0) ? (UINT16 *)&Ptr[12] : &Proto, + &Ptr[14] + ); +#endif + + // Restore TPL and return +exit_unlock: + gBS->RestoreTPL (SavedTpl); + return Status; +} + + +/* +** UEFI Receive() function +** +*/ +EFI_STATUS +EFIAPI +SnpReceive ( + IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp, + OUT UINTN *HdrSize OPTIONAL, + IN OUT UINTN *BuffSize, + OUT VOID *Data, + OUT EFI_MAC_ADDRESS *SrcAddr OPTIONAL, + OUT EFI_MAC_ADDRESS *DstAddr OPTIONAL, + OUT UINT16 *Protocol OPTIONAL + ) +{ + EFI_TPL SavedTpl; + EFI_STATUS Status; + LAN91X_DRIVER *LanDriver; + UINT8 *DataPtr; + UINT16 PktStatus; + UINT16 PktLength; + UINT16 PktControl; + UINT8 IstReg; + + // Check preliminaries + if ((Snp == NULL) || (Data == NULL)) { + return EFI_INVALID_PARAMETER; + } + + // Serialize access to data and registers + SavedTpl = gBS->RaiseTPL (LAN91X_TPL); + + // Check that driver was started and initialised + switch (Snp->Mode->State) { + case EfiSimpleNetworkInitialized: + break; + case EfiSimpleNetworkStarted: + DEBUG((EFI_D_WARN, "LAN91x: Driver not yet initialized\n")); + ReturnUnlock (EFI_DEVICE_ERROR); + case EfiSimpleNetworkStopped: + DEBUG((EFI_D_WARN, "LAN91x: Driver not started\n")); + ReturnUnlock (EFI_NOT_STARTED); + default: + DEBUG((EFI_D_ERROR, "LAN91x: Driver in an invalid state: %u\n", + (UINTN)Snp->Mode->State)); + ReturnUnlock (EFI_DEVICE_ERROR); + } + + // Find the LanDriver structure + LanDriver = INSTANCE_FROM_SNP_THIS(Snp); + + // Check for Rx Overrun + IstReg = ReadIoReg8 (LanDriver, LAN91X_IST); + if ((IstReg & IST_RX_OVRN) != 0) { + LanDriver->Stats.RxTotalFrames += 1; + LanDriver->Stats.RxDroppedFrames += 1; + WriteIoReg8 (LanDriver, LAN91X_IST, IST_RX_OVRN); + DEBUG((EFI_D_WARN, "LAN91x: Receiver overrun\n")); + } + + // Check for Rx data available + if ((IstReg & IST_RCV) == 0) { + ReturnUnlock (EFI_NOT_READY); + } + + // Configure the PTR register for reading + WriteIoReg16 (LanDriver, LAN91X_PTR, PTR_RCV | PTR_AUTO_INCR | PTR_READ); + + // Read the Packet Status and Packet Length words + PktStatus = ReadIoReg16 (LanDriver, LAN91X_DATA0); + PktLength = ReadIoReg16 (LanDriver, LAN91X_DATA0) & BCW_COUNT; + + // Check for valid received packet + if ((PktStatus == 0) && (PktLength == 0)) { + DEBUG((EFI_D_WARN, "LAN91x: Received zero-length packet. IST=%04x\n", IstReg)); + ReturnUnlock (EFI_NOT_READY); + } + LanDriver->Stats.RxTotalFrames += 1; + + // Check if we got a CRC error + if ((PktStatus & RX_BAD_CRC) != 0) { + DEBUG((EFI_D_WARN, "LAN91x: Received frame CRC error\n")); + LanDriver->Stats.RxCrcErrorFrames += 1; + LanDriver->Stats.RxDroppedFrames += 1; + Status = EFI_DEVICE_ERROR; + goto exit_release; + } + + // Check if we got a too-short frame + if ((PktStatus & RX_TOO_SHORT) != 0) { + DEBUG((EFI_D_WARN, "LAN91x: Received frame too short (%d bytes)\n", PktLength)); + LanDriver->Stats.RxUndersizeFrames += 1; + LanDriver->Stats.RxDroppedFrames += 1; + Status = EFI_DEVICE_ERROR; + goto exit_release; + } + + // Check if we got a too-long frame + if ((PktStatus & RX_TOO_LONG) != 0) { + DEBUG((EFI_D_WARN, "LAN91x: Received frame too long (%d bytes)\n", PktLength)); + LanDriver->Stats.RxOversizeFrames += 1; + LanDriver->Stats.RxDroppedFrames += 1; + Status = EFI_DEVICE_ERROR; + goto exit_release; + } + + // Check if we got an alignment error + if ((PktStatus & RX_ALGN_ERR) != 0) { + DEBUG((EFI_D_WARN, "LAN91x: Received frame alignment error\n")); + // Don't seem to keep track of these specifically + LanDriver->Stats.RxDroppedFrames += 1; + Status = EFI_DEVICE_ERROR; + goto exit_release; + } + + // Classify the received fram + if ((PktStatus & RX_MULTICAST) != 0) { + LanDriver->Stats.RxMulticastFrames += 1; + } else if ((PktStatus & RX_BROADCAST) != 0) { + LanDriver->Stats.RxBroadcastFrames += 1; + } else { + LanDriver->Stats.RxUnicastFrames += 1; + } + + // Calculate the received packet data length + PktLength -= LAN91X_PKT_OVERHEAD; + if ((PktStatus & RX_ODD_FRAME) != 0) { + PktLength += 1; + } + + // Check buffer size + if (*BuffSize < PktLength) { + DEBUG((EFI_D_WARN, "LAN91x: Receive buffer too small for packet (%d < %d)\n", + *BuffSize, PktLength)); + *BuffSize = PktLength; + Status = EFI_BUFFER_TOO_SMALL; + goto exit_release; + } + + // Transfer the data bytes + DataPtr = Data; + ReadIoData (LanDriver, DataPtr, PktLength & ~0x0001); + + // Read the PktControl and Odd Byte from the FIFO + PktControl = ReadIoReg16 (LanDriver, LAN91X_DATA0); + if ((PktControl & PCW_ODD) != 0) { + DataPtr[PktLength - 1] = PktControl & PCW_ODD_BYTE; + } + + // Update buffer size + *BuffSize = PktLength; + + if (HdrSize != NULL) { + *HdrSize = LanDriver->SnpMode.MediaHeaderSize; + } + + // Extract the destination address + if (DstAddr != NULL) { + CopyMem (DstAddr, &DataPtr[0], NET_ETHER_ADDR_LEN); + } + + // Get the source address + if (SrcAddr != NULL) { + CopyMem (SrcAddr, &DataPtr[6], NET_ETHER_ADDR_LEN); + } + + // Get the protocol + if (Protocol != NULL) { + *Protocol = NTOHS (*(UINT16*)(&DataPtr[12])); + } + + // Update the Rx statistics + LanDriver->Stats.RxTotalBytes += PktLength; + LanDriver->Stats.RxGoodFrames += 1; + Status = EFI_SUCCESS; + +#if LAN91X_PRINT_PACKET_HEADERS + // Dump the packet header + DEBUG((EFI_D_ERROR, "LAN91X:SnpReceive()\n")); + DEBUG((EFI_D_ERROR, " HdrSize: %p, SrcAddr: %p, DstAddr: %p, Protocol: %p\n", + HdrSize, SrcAddr, DstAddr, Protocol)); + DEBUG((EFI_D_ERROR, " Length: %d, Last byte: %02x\n", PktLength, DataPtr[PktLength - 1])); + PrintIpDgram (&DataPtr[0], &DataPtr[6], &DataPtr[12], &DataPtr[14]); +#endif + + // Release the FIFO buffer +exit_release: + MmuOperation (LanDriver, MMUCR_OP_RX_POP_REL); + + // Restore TPL and return +exit_unlock: + gBS->RestoreTPL (SavedTpl); + return Status; +} + + +/*------------------ Driver Execution Environment main entry point ------------------*/ + +/* +** Entry point for the LAN91x driver +** +*/ +EFI_STATUS +Lan91xDxeEntry ( + IN EFI_HANDLE Handle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + LAN91X_DRIVER *LanDriver; + EFI_SIMPLE_NETWORK_PROTOCOL *Snp; + EFI_SIMPLE_NETWORK_MODE *SnpMode; + LAN91X_DEVICE_PATH *Lan91xPath; + + // The PcdLan91xDxeBaseAddress PCD must be defined + ASSERT(PcdGet32 (PcdLan91xDxeBaseAddress) != 0); + + // Allocate Resources + LanDriver = AllocateZeroPool (sizeof(LAN91X_DRIVER)); + Lan91xPath = AllocateCopyPool (sizeof(LAN91X_DEVICE_PATH), &Lan91xPathTemplate); + + // Initialize I/O Space access info + LanDriver->IoBase = PcdGet32 (PcdLan91xDxeBaseAddress); + LanDriver->PhyAd = LAN91X_NO_PHY; + LanDriver->BankSel = 0xff; + + // Initialize pointers + Snp = &(LanDriver->Snp); + SnpMode = &(LanDriver->SnpMode); + Snp->Mode = SnpMode; + + // Set the signature of the LAN Driver structure + LanDriver->Signature = LAN91X_SIGNATURE; + + // Probe the device + Status = Probe (LanDriver); + if (EFI_ERROR(Status)) { + DEBUG((EFI_D_ERROR, "LAN91x:Lan91xDxeEntry(): Probe failed with status %d\n", Status)); + return Status; + } + +#ifdef LAN91X_PRINT_REGISTERS + PrintIoRegisters (LanDriver); + PrintPhyRegisters (LanDriver); +#endif + + // Assign fields and func pointers + Snp->Revision = EFI_SIMPLE_NETWORK_PROTOCOL_REVISION; + Snp->WaitForPacket = NULL; + Snp->Initialize = SnpInitialize; + Snp->Start = SnpStart; + Snp->Stop = SnpStop; + Snp->Reset = SnpReset; + Snp->Shutdown = SnpShutdown; + Snp->ReceiveFilters = SnpReceiveFilters; + Snp->StationAddress = SnpStationAddress; + Snp->Statistics = SnpStatistics; + Snp->MCastIpToMac = SnpMcastIptoMac; + Snp->NvData = SnpNvData; + Snp->GetStatus = SnpGetStatus; + Snp->Transmit = SnpTransmit; + Snp->Receive = SnpReceive; + + // Fill in simple network mode structure + SnpMode->State = EfiSimpleNetworkStopped; + SnpMode->HwAddressSize = NET_ETHER_ADDR_LEN; // HW address is 6 bytes + SnpMode->MediaHeaderSize = sizeof(ETHER_HEAD); // Size of an Ethernet header + SnpMode->MaxPacketSize = EFI_PAGE_SIZE; // Ethernet Frame (with VLAN tag +4 bytes) + + // Supported receive filters + SnpMode->ReceiveFilterMask = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST | + EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST | + EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST | + EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS | + EFI_SIMPLE_NETWORK_RECEIVE_PROMISCUOUS_MULTICAST; + + // Initially-enabled receive filters + SnpMode->ReceiveFilterSetting = EFI_SIMPLE_NETWORK_RECEIVE_UNICAST | + EFI_SIMPLE_NETWORK_RECEIVE_MULTICAST | + EFI_SIMPLE_NETWORK_RECEIVE_BROADCAST; + + // LAN91x has 64bit hash table. We can filter an infinite MACs, but + // higher-level software must filter out any hash collisions. + SnpMode->MaxMCastFilterCount = MAX_MCAST_FILTER_CNT; + SnpMode->MCastFilterCount = 0; + ZeroMem (&SnpMode->MCastFilter, MAX_MCAST_FILTER_CNT * sizeof(EFI_MAC_ADDRESS)); + + // Set the interface type (1: Ethernet or 6: IEEE 802 Networks) + SnpMode->IfType = NET_IFTYPE_ETHERNET; + + // Mac address is changeable + SnpMode->MacAddressChangeable = TRUE; + + // We can only transmit one packet at a time + SnpMode->MultipleTxSupported = FALSE; + + // MediaPresent checks for cable connection and partner link + SnpMode->MediaPresentSupported = TRUE; + SnpMode->MediaPresent = FALSE; + + // Set broadcast address + SetMem (&SnpMode->BroadcastAddress, sizeof (EFI_MAC_ADDRESS), 0xFF); + + // Assign fields for device path + Lan91xPath->Lan91x.MacAddress = SnpMode->PermanentAddress; + Lan91xPath->Lan91x.IfType = SnpMode->IfType; + + // Initialise the protocol + Status = gBS->InstallMultipleProtocolInterfaces ( + &LanDriver->ControllerHandle, + &gEfiSimpleNetworkProtocolGuid, Snp, + &gEfiDevicePathProtocolGuid, Lan91xPath, + NULL + ); + + // Say what the status of loading the protocol structure is + if (EFI_ERROR(Status)) { + FreePool (LanDriver); + } + + return Status; +} diff --git a/EmbeddedPkg/Drivers/LAN91xDxe/LAN91xDxe.inf b/EmbeddedPkg/Drivers/LAN91xDxe/LAN91xDxe.inf new file mode 100644 index 000000000..9f1580e09 --- /dev/null +++ b/EmbeddedPkg/Drivers/LAN91xDxe/LAN91xDxe.inf @@ -0,0 +1,58 @@ +#/** @file +# INF file for the SMSC LAN91x series Network Controller Driver. +# +# Copyright (c) 2013 Linaro.org +# +# Derived from the LAN9118 driver. Original sources +# Copyright (c) 2012-2013, ARM Limited. All rights reserved. +# +# This program and the accompanying materials are licensed and +# made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license +# may be found at: http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010006 + BASE_NAME = LAN91xDxe + FILE_GUID = 5c12ea2f-9897-48af-8138-25f4ce6ff8d6 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 0.1 + ENTRY_POINT = Lan91xDxeEntry + +[Sources.common] + LAN91xDxe.c + LAN91xDxeHw.h + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + NetworkPkg/NetworkPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + UefiLib + NetLib + UefiDriverEntryPoint + BaseMemoryLib + ArmLib + IoLib + TimerLib + DevicePathLib + +[Protocols] + gEfiSimpleNetworkProtocolGuid + gEfiMetronomeArchProtocolGuid + gEfiPxeBaseCodeProtocolGuid + gEfiDevicePathProtocolGuid + +[FixedPcd] + gEmbeddedTokenSpaceGuid.PcdLan91xDxeBaseAddress + +[Depex] + TRUE diff --git a/EmbeddedPkg/Drivers/LAN91xDxe/LAN91xDxeHw.h b/EmbeddedPkg/Drivers/LAN91xDxe/LAN91xDxeHw.h new file mode 100644 index 000000000..9274ba072 --- /dev/null +++ b/EmbeddedPkg/Drivers/LAN91xDxe/LAN91xDxeHw.h @@ -0,0 +1,278 @@ +/** @file +* SMSC LAN91x series Network Controller Driver. +* +* Copyright (c) 2013 Linaro.org +* +* This program and the accompanying materials are licensed and +* made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license +* may be found at: http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __LAN91XDXEHW_H__ +#define __LAN91XDXEHW_H__ + +#include <Base.h> + +#define MakeRegister(Bank, Offset) (((Bank) << 8) | (Offset)) +#define RegisterToBank(Register) (((Register) >> 8) & 0x07) +#define RegisterToOffset(Register) ((Register) & 0x0f) + +/*--------------------------------------------------------------------------------------------------------------------- + + SMSC LAN91x Registers + +---------------------------------------------------------------------------------------------------------------------*/ +#define LAN91X_BANK_OFFSET 0xe // Bank Select Register (all banks) + +#define LAN91X_TCR MakeRegister (0, 0x0) // Transmit Control Register +#define LAN91X_EPHSR MakeRegister (0, 0x2) // EPH Status Register +#define LAN91X_RCR MakeRegister (0, 0x4) // Receive Control Register +#define LAN91X_ECR MakeRegister (0, 0x6) // Counter Register +#define LAN91X_MIR MakeRegister (0, 0x8) // Memory Information Register +#define LAN91X_RPCR MakeRegister (0, 0xa) // Receive/Phy Control Register + +#define LAN91X_CR MakeRegister (1, 0x0) // Configuration Register +#define LAN91X_BAR MakeRegister (1, 0x2) // Base Address Register +#define LAN91X_IAR0 MakeRegister (1, 0x4) // Individual Address Register 0 +#define LAN91X_IAR1 MakeRegister (1, 0x5) // Individual Address Register 1 +#define LAN91X_IAR2 MakeRegister (1, 0x6) // Individual Address Register 2 +#define LAN91X_IAR3 MakeRegister (1, 0x7) // Individual Address Register 3 +#define LAN91X_IAR4 MakeRegister (1, 0x8) // Individual Address Register 4 +#define LAN91X_IAR5 MakeRegister (1, 0x9) // Individual Address Register 5 +#define LAN91X_GPR MakeRegister (1, 0xa) // General Purpose Register +#define LAN91X_CTR MakeRegister (1, 0xc) // Control Register + +#define LAN91X_MMUCR MakeRegister (2, 0x0) // MMU Command Register +#define LAN91X_PNR MakeRegister (2, 0x2) // Packet Number Register +#define LAN91X_ARR MakeRegister (2, 0x3) // Allocation Result Register +#define LAN91X_FIFO MakeRegister (2, 0x4) // FIFO Ports Register +#define LAN91X_PTR MakeRegister (2, 0x6) // Pointer Register +#define LAN91X_DATA0 MakeRegister (2, 0x8) // Data Register 0 +#define LAN91X_DATA1 MakeRegister (2, 0x9) // Data Register 1 +#define LAN91X_DATA2 MakeRegister (2, 0xa) // Data Register 2 +#define LAN91X_DATA3 MakeRegister (2, 0xb) // Data Register 3 +#define LAN91X_IST MakeRegister (2, 0xc) // Interrupt Status Register +#define LAN91X_MSK MakeRegister (2, 0xd) // Interrupt Mask Register + +#define LAN91X_MT0 MakeRegister (3, 0x0) // Multicast Table Register 0 +#define LAN91X_MT1 MakeRegister (3, 0x1) // Multicast Table Register 1 +#define LAN91X_MT2 MakeRegister (3, 0x2) // Multicast Table Register 2 +#define LAN91X_MT3 MakeRegister (3, 0x3) // Multicast Table Register 3 +#define LAN91X_MT4 MakeRegister (3, 0x4) // Multicast Table Register 4 +#define LAN91X_MT5 MakeRegister (3, 0x5) // Multicast Table Register 5 +#define LAN91X_MT6 MakeRegister (3, 0x6) // Multicast Table Register 6 +#define LAN91X_MT7 MakeRegister (3, 0x7) // Multicast Table Register 7 +#define LAN91X_MGMT MakeRegister (3, 0x8) // Management Interface Register +#define LAN91X_REV MakeRegister (3, 0xa) // Revision Register +#define LAN91X_RCV MakeRegister (3, 0xc) // RCV Register + +// Transmit Control Register Bits +#define TCR_TXENA BIT0 +#define TCR_LOOP BIT1 +#define TCR_FORCOL BIT2 +#define TCR_PAD_EN BIT7 +#define TCR_NOCRC BIT8 +#define TCR_MON_CSN BIT10 +#define TCR_FDUPLX BIT11 +#define TCR_STP_SQET BIT12 +#define TCR_EPH_LOOP BIT13 +#define TCR_SWFDUP BIT15 + +#define TCR_DEFAULT (TCR_TXENA | TCR_PAD_EN) +#define TCR_CLEAR 0x0 + +// EPH Status Register Bits +#define EPHSR_TX_SUC BIT0 +#define EPHSR_SNGLCOL BIT1 +#define EPHSR_MULCOL BIT2 +#define EPHSR_LTX_MULT BIT3 +#define EPHSR_16COL BIT4 +#define EPHSR_SQET BIT5 +#define EPHSR_LTX_BRD BIT6 +#define EPHSR_TX_DEFR BIT7 +#define EPHSR_LATCOL BIT9 +#define EPHSR_LOST_CARR BIT10 +#define EPHSR_EXC_DEF BIT11 +#define EPHSR_CTR_ROL BIT12 +#define EPHSR_LINK_OK BIT14 + +// Receive Control Register Bits +#define RCR_RX_ABORT BIT0 +#define RCR_PRMS BIT1 +#define RCR_ALMUL BIT2 +#define RCR_RXEN BIT8 +#define RCR_STRIP_CRC BIT9 +#define RCR_ABORT_ENB BIT13 +#define RCR_FILT_CAR BIT14 +#define RCR_SOFT_RST BIT15 + +#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) +#define RCR_CLEAR 0x0 + +// Receive/Phy Control Register Bits +#define RPCR_LS0B BIT2 +#define RPCR_LS1B BIT3 +#define RPCR_LS2B BIT4 +#define RPCR_LS0A BIT5 +#define RPCR_LS1A BIT6 +#define RPCR_LS2A BIT7 +#define RPCR_ANEG BIT11 +#define RPCR_DPLX BIT12 +#define RPCR_SPEED BIT13 + +// Configuration Register Bits +#define CR_EXT_PHY BIT9 +#define CR_GPCNTRL BIT10 +#define CR_NO_WAIT BIT12 +#define CR_EPH_POWER_EN BIT15 + +#define CR_DEFAULT (CR_EPH_POWER_EN | CR_NO_WAIT) + +// Control Register Bits +#define CTR_STORE BIT0 +#define CTR_RELOAD BIT1 +#define CTR_EEPROM_SEL BIT2 +#define CTR_TE_ENABLE BIT5 +#define CTR_CR_ENABLE BIT6 +#define CTR_LE_ENABLE BIT7 +#define CTR_AUTO_REL BIT11 +#define CTR_RCV_BAD BIT14 + +#define CTR_RESERVED (BIT12 | BIT9 | BIT4) +#define CTR_DEFAULT (CTR_RESERVED | CTR_AUTO_REL) + +// MMU Command Register Bits +#define MMUCR_BUSY BIT0 + +// MMU Command Register Operaction Codes +#define MMUCR_OP_NOOP (0 << 5) // No operation +#define MMUCR_OP_TX_ALLOC (1 << 5) // Allocate memory for TX +#define MMUCR_OP_RESET_MMU (2 << 5) // Reset MMU to initial state +#define MMUCR_OP_RX_POP (3 << 5) // Remove frame from top of RX FIFO +#define MMUCR_OP_RX_POP_REL (4 << 5) // Remove and release frame from top of RX FIFO +#define MMUCR_OP_RX_REL (5 << 5) // Release specific RX frame +#define MMUCR_OP_TX_PUSH (6 << 5) // Enqueue packet number into TX FIFO +#define MMUCR_OP_TX_RESET (7 << 5) // Reset TX FIFOs + +// Packet Number Register Bits +#define PNR_PACKET (0x3f) + +// Allocation Result Register Bits +#define ARR_PACKET (0x3f) +#define ARR_FAILED BIT7 + +// FIFO Ports Register Bits +#define FIFO_TX_PACKET (0x003f) +#define FIFO_TEMPTY BIT7 +#define FIFO_RX_PACKET (0x3f00) +#define FIFO_REMPTY BIT15 + +// Pointer Register Bits +#define PTR_POINTER (0x07ff) +#define PTR_NOT_EMPTY BIT11 +#define PTR_READ BIT13 +#define PTR_AUTO_INCR BIT14 +#define PTR_RCV BIT15 + +// Interupt Status and Mask Register Bits +#define IST_RCV BIT0 +#define IST_TX BIT1 +#define IST_TX_EMPTY BIT2 +#define IST_ALLOC BIT3 +#define IST_RX_OVRN BIT4 +#define IST_EPH BIT5 +#define IST_MD BIT7 + +// Management Interface +#define MGMT_MDO BIT0 +#define MGMT_MDI BIT1 +#define MGMT_MCLK BIT2 +#define MGMT_MDOE BIT3 +#define MGMT_MSK_CRS100 BIT14 + +// RCV Register +#define RCV_MBO (0x1f) +#define RCV_RCV_DISCRD BIT7 + +// Packet RX Status word bits +#define RX_MULTICAST BIT0 +#define RX_HASH (0x7e) +#define RX_TOO_SHORT BIT10 +#define RX_TOO_LONG BIT11 +#define RX_ODD_FRAME BIT12 +#define RX_BAD_CRC BIT13 +#define RX_BROADCAST BIT14 +#define RX_ALGN_ERR BIT15 + +// Packet Byte Count word bits +#define BCW_COUNT (0x7fe) + +// Packet Control Word bits +#define PCW_ODD_BYTE (0x00ff) +#define PCW_CRC BIT12 +#define PCW_ODD BIT13 + +/*--------------------------------------------------------------------------------------------------------------------- + + SMSC PHY Registers + + Most of these should be common, as there is + documented STANDARD for PHY registers! + +---------------------------------------------------------------------------------------------------------------------*/ +// +// PHY Register Numbers +// +#define PHY_INDEX_BASIC_CTRL 0 +#define PHY_INDEX_BASIC_STATUS 1 +#define PHY_INDEX_ID1 2 +#define PHY_INDEX_ID2 3 +#define PHY_INDEX_AUTO_NEG_ADVERT 4 +#define PHY_INDEX_AUTO_NEG_LINK_ABILITY 5 + +#define PHY_INDEX_CONFIG1 16 +#define PHY_INDEX_CONFIG2 17 +#define PHY_INDEX_STATUS_OUTPUT 18 +#define PHY_INDEX_MASK 19 + + +// PHY control register bits +#define PHYCR_COLL_TEST BIT7 // Collision test enable +#define PHYCR_DUPLEX_MODE BIT8 // Set Duplex Mode +#define PHYCR_RST_AUTO BIT9 // Restart Auto-Negotiation of Link abilities +#define PHYCR_PD BIT11 // Power-Down switch +#define PHYCR_AUTO_EN BIT12 // Auto-Negotiation Enable +#define PHYCR_SPEED_SEL BIT13 // Link Speed Selection +#define PHYCR_LOOPBK BIT14 // Set loopback mode +#define PHYCR_RESET BIT15 // Do a PHY reset + +// PHY status register bits +#define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Register capability +#define PHYSTS_JABBER BIT1 // Jabber condition detected +#define PHYSTS_LINK_STS BIT2 // Link Status +#define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability +#define PHYSTS_REMOTE_FAULT BIT4 // Remote fault detected +#define PHYSTS_AUTO_COMP BIT5 // Auto-Negotiation Completed +#define PHYSTS_10BASET_HDPLX BIT11 // 10Mbps Half-Duplex ability +#define PHYSTS_10BASET_FDPLX BIT12 // 10Mbps Full-Duplex ability +#define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability +#define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability +#define PHYSTS_100BASE_T4 BIT15 // Base T4 ability + +// PHY Auto-Negotiation advertisement +#define PHYANA_SEL_MASK ((UINT32)0x1F) // Link type selector +#define PHYANA_CSMA BIT0 // Advertise CSMA capability +#define PHYANA_10BASET BIT5 // Advertise 10BASET capability +#define PHYANA_10BASETFD BIT6 // Advertise 10BASET Full duplex capability +#define PHYANA_100BASETX BIT7 // Advertise 100BASETX capability +#define PHYANA_100BASETXFD BIT8 // Advertise 100 BASETX Full duplex capability +#define PHYANA_100BASET4 BIT9 // Advertise 100 BASETX Full duplex capability +#define PHYANA_PAUSE_OP_MASK (3 << 10) // Advertise PAUSE frame capability +#define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected + +#endif /* __LAN91XDXEHW_H__ */ diff --git a/EmbeddedPkg/EmbeddedPkg.dec b/EmbeddedPkg/EmbeddedPkg.dec index ee3ff31dd..e164b1e95 100644 --- a/EmbeddedPkg/EmbeddedPkg.dec +++ b/EmbeddedPkg/EmbeddedPkg.dec @@ -61,7 +61,7 @@ gAndroidFastbootTransportProtocolGuid = { 0x74bd9fe0, 0x8902, 0x11e3, {0xb9, 0xd3, 0xf7, 0x22, 0x38, 0xfc, 0x9a, 0x31}}
gAndroidFastbootPlatformProtocolGuid = { 0x524685a0, 0x89a0, 0x11e3, {0x9d, 0x4d, 0xbf, 0xa9, 0xf6, 0xa4, 0x03, 0x08}}
gUsbDeviceProtocolGuid = { 0x021bd2ca, 0x51d2, 0x11e3, {0x8e, 0x56, 0xb7, 0x54, 0x17, 0xc7, 0x0b, 0x44 }}
- +
[PcdsFeatureFlag.common]
gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|FALSE|BOOLEAN|0x00000001
gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE|BOOLEAN|0x00000002
@@ -133,6 +133,9 @@ gEmbeddedTokenSpaceGuid.PcdLan9118DxeBaseAddress|0x0|UINT32|0x00000025
gEmbeddedTokenSpaceGuid.PcdLan9118DefaultMacAddress|0x0|UINT64|0x00000026
+ # LAN91x Ethernet Driver PCDs
+ gEmbeddedTokenSpaceGuid.PcdLan91xDxeBaseAddress|0x0|UINT32|0x000000FE
+
#
# Android FastBoot
#
diff --git a/EmulatorPkg/EmulatorPkg.dsc b/EmulatorPkg/EmulatorPkg.dsc index 926411d37..60eddddb7 100644 --- a/EmulatorPkg/EmulatorPkg.dsc +++ b/EmulatorPkg/EmulatorPkg.dsc @@ -393,7 +393,7 @@ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
- PathLib|ShellPkg/Library/BasePathLib/BasePathLib.inf
+ PathLib|MdeModulePkg/Library/BasePathLib/BasePathLib.inf
# MemoryAllocationLib|EmulatorPkg/Library/GuardUefiMemoryAllocationLib/GuardUefiMemoryAllocationLib.inf
# SafeBlockIoLib|ShellPkg/Library/SafeBlockIoLib/SafeBlockIoLib.inf
# SafeOpenProtocolLib|ShellPkg/Library/SafeOpenProtocolLib/SafeOpenProtocolLib.inf
diff --git a/HisiPkg/D01BoardPkg/Application/Ebl/Ebl.efi b/HisiPkg/D01BoardPkg/Application/Ebl/Ebl.efi Binary files differnew file mode 100644 index 000000000..50c6aaa9c --- /dev/null +++ b/HisiPkg/D01BoardPkg/Application/Ebl/Ebl.efi diff --git a/HisiPkg/D01BoardPkg/Application/Ebl/Ebl.inf b/HisiPkg/D01BoardPkg/Application/Ebl/Ebl.inf new file mode 100644 index 000000000..3c1c21618 --- /dev/null +++ b/HisiPkg/D01BoardPkg/Application/Ebl/Ebl.inf @@ -0,0 +1,37 @@ +#/** @file
+# EBL Applicaiton
+#
+# This is a shell application that will display Hello World.
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = Ebl
+ FILE_GUID = 3CEF354A-3B7A-4519-AD70-72A134698311
+ MODULE_TYPE = UEFI_APPLICATION
+ VERSION_STRING = 1.0
+ ENTRY_POINT = EdkBootLoaderEntry
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+[Binaries.common]
+ PE32|Ebl.efi|*
+
diff --git a/HisiPkg/D01BoardPkg/Bds/Bds.c b/HisiPkg/D01BoardPkg/Bds/Bds.c new file mode 100644 index 000000000..0c367fad5 --- /dev/null +++ b/HisiPkg/D01BoardPkg/Bds/Bds.c @@ -0,0 +1,809 @@ +/** @file
+*
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+* Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "BdsInternal.h"
+
+#include <Library/PcdLib.h>
+#include <Library/PerformanceLib.h>
+
+#include <Protocol/Bds.h>
+#include <Protocol/NorFlashProtocol.h>
+#include <Library/BspUartLib.h>
+#include <libfdt_env.h>
+#include <Protocol/NandFlashProtocol.h>
+
+char gpoint3[2][100] = {{0}}; +
+#ifndef U8
+typedef unsigned char U8;
+#endif
+
+#define EFI_SET_TIMER_TO_SECOND 10000000
+#define FLASH_ECC_RESADDR 0x31000000
+#define FLASH_ECC_RESADDR_OFFSET 0x1000000
+#define RAM_TEST_WORK_TAG (0x5A5A5A5A)
+#define RAM_TEST_NOWORK_TAG (0x0A0A0A0A)
+
+EFI_HANDLE mImageHandle;
+
+//************************************************
+#define SEEK_SET 0
+#define SEEK_CUR 1
+#define SEEK_END 2
+#define EOF (-1)
+
+#define CPBSP_BASE_ID (0x0)
+#define M_bootload (26 << 16)
+#define M_common (0 << 16)
+#define M_common_PARAMETER_ERR (M_common | 1)
+#define M_bootload_LOADVXWORKS_FAIL (CPBSP_BASE_ID | M_bootload | 7)
+
+#define GET_CHAR_FROM_COM(timeout) BspGetChar(timeout*23000)
+
+/* max number of image which you can choice,there are two file name for NODEB*/
+#define PRODUCT_FILENUM 2
+U32 g_ulProductVerSelectNum = PRODUCT_FILENUM;
+#define BOOTUP_CONFIG_FILE "Bootup.ini" /* bootup config file */
+
+STATUS BootTovxWorks( void );
+void BSP_GetProductFileName(char* cProductVerName);
+U32 BSP_LoadVxworks (char *pFileName);
+STATUS BSP_LoadVxworksByName( char *fileName );
+
+extern EFI_STATUS
+BootLinuxAtagLoader (
+ IN LIST_ENTRY *BootOptionsList
+ );
+EFI_STATUS
+BootGo (
+ IN LIST_ENTRY *BootOptionsList
+ );
+
+//************************************************
+//address of Linux in DDR
+#define TEXT_DDR_BASE 0x10c00000
+#define MONITOR_DDR_BASE 0x10c08000
+#define KERNEL_DDR_BASE 0x10008000
+#define FILESYSTEM_DDR_BASE 0x10d00000
+
+//estimate size of Linux kernel,the size for copying file to DDR isn't bigger than this
+#define TEXT_SIZE 0x400000
+#define MONITOR_SIZE 0x400000
+#define KERNEL_SIZE 0xa00000
+#define FILESYSTEM_SIZE 0x1800000
+
+//actual size of copying file to DDR, it should not bigger than estimate size
+#define TEXT_COPY_SIZE 0x20000
+#define MONITOR_COPY_SIZE 0x20000
+#define KERNEL_COPY_SIZE 0xa00000
+#define FILESYSTEM_COPY_SIZE 0x1800000
+
+//address of Linux in NORFLASH
+#define TEXT_FLASH_BASE (PcdGet32(PcdNorFlashBase) + 0x1000000)
+#define MONITOR_FLASH_BASE (TEXT_FLASH_BASE + TEXT_SIZE)
+#define KERNEL_FLASH_BASE (MONITOR_FLASH_BASE + MONITOR_SIZE)
+#define FILESYSTEM_FLASH_BASE (KERNEL_FLASH_BASE + KERNEL_SIZE)
+
+//address of Linux in NANDFlash
+#define TEXT_BLOCKNUM_NANDFLASH (0)
+#define MONITOR_BLOCKNUM_NANDFLASH (TEXT_BLOCKNUM_NANDFLASH + TEXT_SIZE / 0x20000)
+#define KERNEL_BLOCKNUM_NANDFLASH (MONITOR_BLOCKNUM_NANDFLASH + MONITOR_SIZE / 0x20000)
+#define FILESYSTEM_BLOCKNUM_NANDFLASH (KERNEL_BLOCKNUM_NANDFLASH + KERNEL_SIZE / 0x20000)
+
+STATIC
+EFI_STATUS
+GetConsoleDevicePathFromVariable (
+ IN CHAR16* ConsoleVarName,
+ IN CHAR16* DefaultConsolePaths,
+ OUT EFI_DEVICE_PATH** DevicePaths
+ )
+{
+ EFI_STATUS Status;
+ UINTN Size;
+ EFI_DEVICE_PATH_PROTOCOL* DevicePathInstances;
+ EFI_DEVICE_PATH_PROTOCOL* DevicePathInstance;
+ CHAR16* DevicePathStr;
+ CHAR16* NextDevicePathStr;
+ EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL *EfiDevicePathFromTextProtocol;
+
+ Status = GetGlobalEnvironmentVariable (ConsoleVarName, NULL, NULL, (VOID**)&DevicePathInstances);
+ if (EFI_ERROR(Status)) {
+ // In case no default console device path has been defined we assume a driver handles the console (eg: SimpleTextInOutSerial)
+ if ((DefaultConsolePaths == NULL) || (DefaultConsolePaths[0] == L'\0')) {
+ *DevicePaths = NULL;
+ return EFI_SUCCESS;
+ }
+
+ Status = gBS->LocateProtocol (&gEfiDevicePathFromTextProtocolGuid, NULL, (VOID **)&EfiDevicePathFromTextProtocol);
+ ASSERT_EFI_ERROR(Status);
+
+ DevicePathInstances = NULL;
+
+ // Extract the Device Path instances from the multi-device path string
+ while ((DefaultConsolePaths != NULL) && (DefaultConsolePaths[0] != L'\0')) {
+ NextDevicePathStr = StrStr (DefaultConsolePaths, L";");
+ if (NextDevicePathStr == NULL) {
+ DevicePathStr = DefaultConsolePaths;
+ DefaultConsolePaths = NULL;
+ } else {
+ DevicePathStr = (CHAR16*)AllocateCopyPool ((NextDevicePathStr - DefaultConsolePaths + 1) * sizeof(CHAR16), DefaultConsolePaths);
+ *(DevicePathStr + (NextDevicePathStr - DefaultConsolePaths)) = L'\0';
+ DefaultConsolePaths = NextDevicePathStr;
+ if (DefaultConsolePaths[0] == L';') {
+ DefaultConsolePaths++;
+ }
+ }
+
+ DevicePathInstance = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath (DevicePathStr);
+ ASSERT(DevicePathInstance != NULL);
+ DevicePathInstances = AppendDevicePathInstance (DevicePathInstances, DevicePathInstance);
+
+ if (NextDevicePathStr != NULL) {
+ FreePool (DevicePathStr);
+ }
+ FreePool (DevicePathInstance);
+ }
+
+ // Set the environment variable with this device path multi-instances
+ Size = GetDevicePathSize (DevicePathInstances);
+ if (Size > 0) {
+ gRT->SetVariable (
+ ConsoleVarName,
+ &gEfiGlobalVariableGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ Size,
+ DevicePathInstances
+ );
+ } else {
+ Status = EFI_INVALID_PARAMETER;
+ }
+ }
+
+ if (!EFI_ERROR(Status)) {
+ *DevicePaths = DevicePathInstances;
+ }
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+InitializeConsolePipe (
+ IN EFI_DEVICE_PATH *ConsoleDevicePaths,
+ IN EFI_GUID *Protocol,
+ OUT EFI_HANDLE *Handle,
+ OUT VOID* *Interface
+ )
+{
+ EFI_STATUS Status;
+ UINTN Size;
+ UINTN NoHandles;
+ EFI_HANDLE *Buffer;
+ EFI_DEVICE_PATH_PROTOCOL* DevicePath;
+
+ // Connect all the Device Path Consoles
+ while (ConsoleDevicePaths != NULL) {
+ DevicePath = GetNextDevicePathInstance (&ConsoleDevicePaths, &Size);
+
+ Status = BdsConnectDevicePath (DevicePath, Handle, NULL);
+ DEBUG_CODE_BEGIN();
+ if (EFI_ERROR(Status)) {
+ // We convert back to the text representation of the device Path
+ EFI_DEVICE_PATH_TO_TEXT_PROTOCOL* DevicePathToTextProtocol;
+ CHAR16* DevicePathTxt;
+ EFI_STATUS Status;
+
+ Status = gBS->LocateProtocol(&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol);
+ if (!EFI_ERROR(Status)) {
+ DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText (DevicePath, TRUE, TRUE);
+
+ DEBUG((EFI_D_ERROR,"Fail to start the console with the Device Path '%s'. (Error '%r')\n", DevicePathTxt, Status));
+
+ FreePool (DevicePathTxt);
+ }
+ }
+ DEBUG_CODE_END();
+
+ // If the console splitter driver is not supported by the platform then use the first Device Path
+ // instance for the console interface.
+ if (!EFI_ERROR(Status) && (*Interface == NULL)) {
+ Status = gBS->HandleProtocol (*Handle, Protocol, Interface);
+ }
+ }
+
+ // No Device Path has been defined for this console interface. We take the first protocol implementation
+ if (*Interface == NULL) {
+ Status = gBS->LocateHandleBuffer (ByProtocol, Protocol, NULL, &NoHandles, &Buffer);
+ if (EFI_ERROR (Status)) {
+ BdsConnectAllDrivers();
+ Status = gBS->LocateHandleBuffer (ByProtocol, Protocol, NULL, &NoHandles, &Buffer);
+ }
+
+ if (!EFI_ERROR(Status)) {
+ *Handle = Buffer[0];
+ Status = gBS->HandleProtocol (*Handle, Protocol, Interface);
+ ASSERT_EFI_ERROR(Status);
+ }
+ FreePool (Buffer);
+ } else {
+ Status = EFI_SUCCESS;
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+InitializeConsole (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_DEVICE_PATH* ConOutDevicePaths;
+ EFI_DEVICE_PATH* ConInDevicePaths;
+ EFI_DEVICE_PATH* ConErrDevicePaths;
+
+ // By getting the Console Device Paths from the environment variables before initializing the console pipe, we
+ // create the 3 environment variables (ConIn, ConOut, ConErr) that allows to initialize all the console interface
+ // of newly installed console drivers
+ Status = GetConsoleDevicePathFromVariable (L"ConOut", (CHAR16*)PcdGetPtr(PcdDefaultConOutPaths), &ConOutDevicePaths);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConsoleDevicePathFromVariable (L"ConIn", (CHAR16*)PcdGetPtr(PcdDefaultConInPaths), &ConInDevicePaths);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConsoleDevicePathFromVariable (L"ErrOut", (CHAR16*)PcdGetPtr(PcdDefaultConOutPaths), &ConErrDevicePaths);
+ ASSERT_EFI_ERROR (Status);
+
+ // Initialize the Consoles
+ Status = InitializeConsolePipe (ConOutDevicePaths, &gEfiSimpleTextOutProtocolGuid, &gST->ConsoleOutHandle, (VOID **)&gST->ConOut);
+ ASSERT_EFI_ERROR (Status);
+ Status = InitializeConsolePipe (ConInDevicePaths, &gEfiSimpleTextInProtocolGuid, &gST->ConsoleInHandle, (VOID **)&gST->ConIn);
+ ASSERT_EFI_ERROR (Status);
+ Status = InitializeConsolePipe (ConErrDevicePaths, &gEfiSimpleTextOutProtocolGuid, &gST->StandardErrorHandle, (VOID **)&gST->StdErr);
+ if (EFI_ERROR(Status)) {
+ // In case of error, we reuse the console output for the error output
+ gST->StandardErrorHandle = gST->ConsoleOutHandle;
+ gST->StdErr = gST->ConOut;
+ }
+
+ // Free Memory allocated for reading the UEFI Variables
+ if (ConOutDevicePaths) {
+ FreePool (ConOutDevicePaths);
+ }
+ if (ConInDevicePaths) {
+ FreePool (ConInDevicePaths);
+ }
+ if (ConErrDevicePaths) {
+ FreePool (ConErrDevicePaths);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+DefineDefaultBootEntries (
+ VOID
+ )
+{
+ BDS_LOAD_OPTION* BdsLoadOption;
+ UINTN Size;
+ EFI_STATUS Status;
+ EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL* EfiDevicePathFromTextProtocol;
+ EFI_DEVICE_PATH* BootDevicePath;
+ UINT8* OptionalData;
+ UINTN OptionalDataSize;
+ ARM_BDS_LOADER_ARGUMENTS* BootArguments;
+ ARM_BDS_LOADER_TYPE BootType;
+ EFI_DEVICE_PATH* InitrdPath;
+ UINTN InitrdSize;
+ UINTN CmdLineSize;
+ UINTN CmdLineAsciiSize;
+ CHAR16* DefaultBootArgument;
+ CHAR8* AsciiDefaultBootArgument;
+
+ //
+ // If Boot Order does not exist then create a default entry
+ //
+ Size = 0;
+ Status = gRT->GetVariable (L"BootOrder", &gEfiGlobalVariableGuid, NULL, &Size, NULL);
+ if (Status == EFI_NOT_FOUND) {
+ if ((PcdGetPtr(PcdDefaultBootDevicePath) == NULL) || (StrLen ((CHAR16*)PcdGetPtr(PcdDefaultBootDevicePath)) == 0)) {
+ return EFI_UNSUPPORTED;
+ }
+
+ Status = gBS->LocateProtocol (&gEfiDevicePathFromTextProtocolGuid, NULL, (VOID **)&EfiDevicePathFromTextProtocol);
+ if (EFI_ERROR(Status)) {
+ // You must provide an implementation of DevicePathFromTextProtocol in your firmware (eg: DevicePathDxe)
+ DEBUG((EFI_D_ERROR,"Error: Bds requires DevicePathFromTextProtocol\n"));
+ return Status;
+ }
+ BootDevicePath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath ((CHAR16*)PcdGetPtr(PcdDefaultBootDevicePath));
+
+ DEBUG_CODE_BEGIN();
+ // We convert back to the text representation of the device Path to see if the initial text is correct
+ EFI_DEVICE_PATH_TO_TEXT_PROTOCOL* DevicePathToTextProtocol;
+ CHAR16* DevicePathTxt;
+
+ Status = gBS->LocateProtocol(&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol);
+ ASSERT_EFI_ERROR(Status);
+ DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText (BootDevicePath, TRUE, TRUE);
+
+ ASSERT (StrCmp ((CHAR16*)PcdGetPtr(PcdDefaultBootDevicePath), DevicePathTxt) == 0);
+
+ FreePool (DevicePathTxt);
+ DEBUG_CODE_END();
+
+ // Create the entry is the Default values are correct
+ if (BootDevicePath != NULL) {
+ BootType = (ARM_BDS_LOADER_TYPE)PcdGet32 (PcdDefaultBootType);
+
+ // We do not support NULL pointer
+ ASSERT (PcdGetPtr (PcdDefaultBootArgument) != NULL);
+
+ //
+ // Logic to handle ASCII or Unicode default parameters
+ //
+ if (*(CHAR8*)PcdGetPtr (PcdDefaultBootArgument) == '\0') {
+ CmdLineSize = 0;
+ CmdLineAsciiSize = 0;
+ DefaultBootArgument = NULL;
+ AsciiDefaultBootArgument = NULL;
+ } else if (IsUnicodeString ((CHAR16*)PcdGetPtr (PcdDefaultBootArgument))) {
+ // The command line is a Unicode string
+ DefaultBootArgument = (CHAR16*)PcdGetPtr (PcdDefaultBootArgument);
+ CmdLineSize = StrSize (DefaultBootArgument);
+
+ // Initialize ASCII variables
+ CmdLineAsciiSize = CmdLineSize / 2;
+ AsciiDefaultBootArgument = AllocatePool (CmdLineAsciiSize);
+ if (AsciiDefaultBootArgument == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ UnicodeStrToAsciiStr ((CHAR16*)PcdGetPtr (PcdDefaultBootArgument), AsciiDefaultBootArgument);
+ } else {
+ // The command line is a ASCII string
+ AsciiDefaultBootArgument = (CHAR8*)PcdGetPtr (PcdDefaultBootArgument);
+ CmdLineAsciiSize = AsciiStrSize (AsciiDefaultBootArgument);
+
+ // Initialize ASCII variables
+ CmdLineSize = CmdLineAsciiSize * 2;
+ DefaultBootArgument = AllocatePool (CmdLineSize);
+ if (DefaultBootArgument == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ AsciiStrToUnicodeStr (AsciiDefaultBootArgument, DefaultBootArgument);
+ }
+
+ if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_FDT)) {
+ InitrdPath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath ((CHAR16*)PcdGetPtr(PcdDefaultBootInitrdPath));
+ InitrdSize = GetDevicePathSize (InitrdPath);
+
+ OptionalDataSize = sizeof(ARM_BDS_LOADER_ARGUMENTS) + CmdLineAsciiSize + InitrdSize;
+ BootArguments = (ARM_BDS_LOADER_ARGUMENTS*)AllocatePool (OptionalDataSize);
+ if (BootArguments == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ BootArguments->LinuxArguments.CmdLineSize = CmdLineAsciiSize;
+ BootArguments->LinuxArguments.InitrdSize = InitrdSize;
+
+ CopyMem ((VOID*)(BootArguments + 1), AsciiDefaultBootArgument, CmdLineAsciiSize);
+ CopyMem ((VOID*)((UINTN)(BootArguments + 1) + CmdLineAsciiSize), InitrdPath, InitrdSize);
+
+ OptionalData = (UINT8*)BootArguments;
+ } else {
+ OptionalData = (UINT8*)DefaultBootArgument;
+ OptionalDataSize = CmdLineSize;
+ }
+
+ BootOptionCreate (LOAD_OPTION_ACTIVE | LOAD_OPTION_CATEGORY_BOOT,
+ (CHAR16*)PcdGetPtr(PcdDefaultBootDescription),
+ BootDevicePath,
+ BootType,
+ OptionalData,
+ OptionalDataSize,
+ &BdsLoadOption
+ );
+ FreePool (BdsLoadOption);
+
+ if (DefaultBootArgument == (CHAR16*)PcdGetPtr (PcdDefaultBootArgument)) {
+ FreePool (AsciiDefaultBootArgument);
+ } else if (DefaultBootArgument != NULL) {
+ FreePool (DefaultBootArgument);
+ }
+ } else {
+ Status = EFI_UNSUPPORTED;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+StartDefaultBootOnTimeout (
+ VOID
+ )
+{
+ UINTN Size;
+ UINT16 Timeout;
+ UINT16 *TimeoutPtr;
+ EFI_EVENT WaitList[2];
+ UINTN WaitIndex;
+ UINT16 *BootOrder;
+ UINTN BootOrderSize;
+ UINTN Index;
+ CHAR16 BootVariableName[9];
+ EFI_STATUS Status;
+ EFI_INPUT_KEY Key;
+
+ Size = sizeof(UINT16);
+ Timeout = (UINT16)PcdGet16 (PcdPlatformBootTimeOut);
+ Status = GetGlobalEnvironmentVariable (L"Timeout", &Timeout, &Size, (VOID**)&TimeoutPtr);
+ if (!EFI_ERROR (Status)) {
+ Timeout = *TimeoutPtr;
+ FreePool (TimeoutPtr);
+ }
+
+ if (Timeout != 0xFFFF) {
+ if (Timeout > 0) {
+ // Create the waiting events (keystroke and 1sec timer)
+ gBS->CreateEvent (EVT_TIMER, 0, NULL, NULL, &WaitList[0]);
+ gBS->SetTimer (WaitList[0], TimerPeriodic, EFI_SET_TIMER_TO_SECOND);
+ WaitList[1] = gST->ConIn->WaitForKey;
+
+ // Start the timer
+ WaitIndex = 0;
+ Print(L"The default boot selection will start in ");
+ while ((Timeout > 0) && (WaitIndex == 0)) {
+ Print(L"%3d seconds",Timeout);
+ gBS->WaitForEvent (2, WaitList, &WaitIndex);
+ if (WaitIndex == 0) {
+ Print(L"\b\b\b\b\b\b\b\b\b\b\b");
+ Timeout--;
+ }
+ }
+ // Discard key in the buffer
+ do {
+ Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);
+ } while(!EFI_ERROR(Status));
+ gBS->CloseEvent (WaitList[0]);
+ Print(L"\n\r");
+ }
+
+ // In case of Timeout we start the default boot selection
+ if (Timeout == 0) {
+ // Get the Boot Option Order from the environment variable (a default value should have been created)
+ GetGlobalEnvironmentVariable (L"BootOrder", NULL, &BootOrderSize, (VOID**)&BootOrder);
+
+ for (Index = 0; Index < BootOrderSize / sizeof (UINT16); Index++) {
+ UnicodeSPrint (BootVariableName, 9 * sizeof(CHAR16), L"Boot%04X", BootOrder[Index]);
+ Status = BdsStartBootOption (BootVariableName);
+ if(!EFI_ERROR(Status)){
+ // Boot option returned successfully, hence don't need to start next boot option
+ break;
+ }
+ // In case of success, we should not return from this call.
+ }
+ FreePool (BootOrder);
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+//copy image from NANDFLASH to DDR,file in NANDFLASH must be block align
+EFI_STATUS CopyNandToMem(void* Dest, UINT32 StartBlockNum, UINT32 LengthCopy)
+{
+ EFI_NAND_DRIVER_PROTOCOL *nandDriver= NULL;
+ EFI_STATUS Status;
+ NAND_CMD_INFO_STRU ulNandCMDInfo = {0, 0, 0};
+ UINT8 *pucData = NULL;
+ UINT32 ulChunkNum = 0;
+ UINT32 BlockNumCopy = 0;
+ UINT32 i = 0;
+ UINT32 PagePerBlock = 0;
+ UINT32 PageNumCopy = 0;
+
+ DEBUG((EFI_D_ERROR, "[%a : %d]\n", __FUNCTION__, __LINE__));
+ Status = gBS->LocateProtocol (&gNANDDriverProtocolGuid, NULL, (VOID *) &nandDriver);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "[%a : %d]LocateProtocol:gNANDDriverProtocolGuid fail!\n", __FUNCTION__, __LINE__));
+ return EFI_ABORTED;
+ }
+
+ ulNandCMDInfo = nandDriver->NandFlashGetCMDInfo(nandDriver);
+ if(0 != LengthCopy % ulNandCMDInfo.ulBlockSize)
+ {
+ DEBUG((EFI_D_ERROR, "[%a : %d]input parameter ERROR!\n", __FUNCTION__, __LINE__));
+ return EFI_ABORTED;
+ }
+
+ if (NULL == (pucData = (UINT8*)AllocatePool(ulNandCMDInfo.ulPageSize)))
+ {
+ DEBUG((EFI_D_ERROR, "[%a : %d]Apply buffer failed!\n", __FUNCTION__, __LINE__));
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ PagePerBlock = ulNandCMDInfo.ulBlockSize / ulNandCMDInfo.ulPageSize;
+ BlockNumCopy = (0 == LengthCopy % ulNandCMDInfo.ulBlockSize) ? (LengthCopy / ulNandCMDInfo.ulBlockSize) : (LengthCopy / ulNandCMDInfo.ulBlockSize + 1);
+ PageNumCopy = PagePerBlock * BlockNumCopy;
+ DEBUG((EFI_D_ERROR, "[%a : %d]PageNumCopy = %x!\n", __FUNCTION__, __LINE__, PageNumCopy));
+ for(i = 0;i < PageNumCopy; i++)
+ {
+ //calculate chunk number of your want to read in NANDFLASH
+ ulChunkNum = StartBlockNum * PagePerBlock + i;
+ gBS->SetMem(pucData, ulNandCMDInfo.ulPageSize, 0);
+ Status = (int)nandDriver->NandFlashReadEcc(nandDriver, ulChunkNum, 0, ulNandCMDInfo.ulPageSize, pucData, NULL);
+ if(EFI_SUCCESS != Status)
+ {
+ DEBUG((EFI_D_ERROR, "[%a : %d]NandFlashReadEcc ERROR!\n", __FUNCTION__, __LINE__));
+ gBS->FreePool(pucData);
+ return EFI_ABORTED;
+ }
+ memcpy((void *)((UINT32)Dest + i * ulNandCMDInfo.ulPageSize), (void *)pucData, ulNandCMDInfo.ulPageSize);
+ }
+ gBS->FreePool(pucData);
+ return EFI_SUCCESS;
+}
+#define NANDFLASHREAD 1
+
+/**
+ This function uses policy data from the platform to determine what operating
+ system or system utility should be loaded and invoked. This function call
+ also optionally make the use of user input to determine the operating system
+ or system utility to be loaded and invoked. When the DXE Core has dispatched
+ all the drivers on the dispatch queue, this function is called. This
+ function will attempt to connect the boot devices required to load and invoke
+ the selected operating system or system utility. During this process,
+ additional firmware volumes may be discovered that may contain addition DXE
+ drivers that can be dispatched by the DXE Core. If a boot device cannot be
+ fully connected, this function calls the DXE Service Dispatch() to allow the
+ DXE drivers from any newly discovered firmware volumes to be dispatched.
+ Then the boot device connection can be attempted again. If the same boot
+ device connection operation fails twice in a row, then that boot device has
+ failed, and should be skipped. This function should never return.
+
+ @param This The EFI_BDS_ARCH_PROTOCOL instance.
+
+ @return None.
+
+**/
+
+VOID
+EFIAPI
+BdsEntry (
+ IN EFI_BDS_ARCH_PROTOCOL *This
+ )
+{
+ UINTN Size;
+ EFI_STATUS Status;
+ //STATUS Result;
+ UINT16 *BootNext;
+ UINTN BootNextSize;
+ CHAR16 BootVariableName[9];
+ EFI_NAND_DRIVER_PROTOCOL *nandDriver= NULL;
+
+ //UNI_NOR_FLASH_PROTOCOL *Flash;
+
+ PERF_END (NULL, "DXE", NULL, 0);
+ //U32 buffer[9];
+
+ char ckeyValue = 0 ;
+ LIST_ENTRY BootOptionsList;
+ //
+ // Declare the Firmware Vendor
+ //
+ if (FixedPcdGetPtr(PcdFirmwareVendor) != NULL) {
+ Size = 0x100;
+ gST->FirmwareVendor = AllocateRuntimePool (Size);
+ ASSERT (gST->FirmwareVendor != NULL);
+ UnicodeSPrint (gST->FirmwareVendor, Size, L"%a EFI %a %a", PcdGetPtr(PcdFirmwareVendor), __DATE__, __TIME__);
+ }
+
+ // If BootNext environment variable is defined then we just load it !
+ BootNextSize = sizeof(UINT16);
+ Status = GetGlobalEnvironmentVariable (L"BootNext", NULL, &BootNextSize, (VOID**)&BootNext);
+ if (!EFI_ERROR(Status)) {
+ ASSERT(BootNextSize == sizeof(UINT16));
+
+ // Generate the requested Boot Entry variable name
+ UnicodeSPrint (BootVariableName, 9 * sizeof(CHAR16), L"Boot%04X", *BootNext);
+
+ // Set BootCurrent variable
+ gRT->SetVariable (L"BootCurrent", &gEfiGlobalVariableGuid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ BootNextSize, BootNext);
+
+ FreePool (BootNext);
+
+ // Start the requested Boot Entry
+ Status = BdsStartBootOption (BootVariableName);
+ if (Status != EFI_NOT_FOUND) {
+ // BootNext has not been succeeded launched
+ if (EFI_ERROR(Status)) {
+ Print(L"Fail to start BootNext.\n");
+ }
+
+ // Delete the BootNext environment variable
+ gRT->SetVariable (L"BootNext", &gEfiGlobalVariableGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ 0, NULL);
+ }
+
+ // Clear BootCurrent variable
+ gRT->SetVariable (L"BootCurrent", &gEfiGlobalVariableGuid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ 0, NULL);
+ }
+
+ // If Boot Order does not exist then create a default entry
+ DefineDefaultBootEntries ();
+
+ // Now we need to setup the EFI System Table with information about the console devices.
+ InitializeConsole ();
+
+ Status = gBS->LocateProtocol (&gNANDDriverProtocolGuid, NULL, (VOID *) &nandDriver);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "LocateProtocol:gNANDDriverProtocolGuid fail!\n"));
+ }
+
+ DEBUG((EFI_D_ERROR, "NandFlashInit start\n"));
+ Status = (int)nandDriver->NandFlashInit(nandDriver);
+ if(EFI_SUCCESS != Status)
+ {
+ DEBUG((EFI_D_ERROR, "NAND Flash Init Error! Status = %r\n", Status));
+ }
+ else
+ {
+ DEBUG((EFI_D_ERROR, "NAND Flash Init OK! Status = %r\n", Status));
+ }
+
+
+ (VOID)AsciiPrint("\n\rAuto boot or not ?(Press 's' to Boot Menu)");
+ (VOID)AsciiPrint("\n\rNow wait for 2 seconds...\n");
+
+ ckeyValue = GET_CHAR_FROM_COM(2);
+
+ if ( 0x73 != ckeyValue )
+ {
+ (VOID)AsciiPrint("\n\rNot Press 's', Start Auto Boot!\n");
+ Status = gBS->LocateProtocol (&gNANDDriverProtocolGuid, NULL, (VOID *) &nandDriver);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "LocateProtocol:gNANDDriverProtocolGuid fail!\n"));
+ }
+
+ //Status = BootMenuMain ();
+ //ASSERT_EFI_ERROR (Status);
+
+ #if 1
+ /*2.copy image from FLASH to DDR,and start*/
+ (VOID)AsciiPrint("\nTransmit OS from FLASH to DDR now, please wait!");
+
+ #ifdef NANDFLASHREAD
+ CopyNandToMem((void *)TEXT_DDR_BASE, TEXT_BLOCKNUM_NANDFLASH, TEXT_COPY_SIZE);
+ (VOID)AsciiPrint("\nThe .text file is transmitted ok!\n");
+ #else
+ /* copy.text */
+ memcpy((void *)TEXT_DDR_BASE, (void *)TEXT_FLASH_BASE, TEXT_COPY_SIZE);
+ (VOID)AsciiPrint("\nThe .text file is transmitted ok!\n");
+ #endif
+// /* compare text in FLASH and the same file in DDR*/
+// if (CompareMem((void *)TEXT_DDR_BASE, (void *)TEXT_FLASH_BASE, TEXT_COPY_SIZE) != 0)
+// {
+// (VOID)AsciiPrint("The .text file check fail!\n");
+// //return;
+// }
+// else
+// {
+// (VOID)AsciiPrint("The .text file check sucess!\n");
+// }
+
+ #ifdef NANDFLASHREAD
+ /* copy .monitor */
+ CopyNandToMem((void *)MONITOR_DDR_BASE, MONITOR_BLOCKNUM_NANDFLASH, MONITOR_COPY_SIZE);
+ (VOID)AsciiPrint("The .monitor file is transmitted ok!\n");
+ #else
+ /* copy .monitor */
+ memcpy((void *)MONITOR_DDR_BASE, (void *)MONITOR_FLASH_BASE, MONITOR_COPY_SIZE);
+ (VOID)AsciiPrint("The .monitor file is transmitted ok!\n");
+ #endif
+// /* compare uimage in FLASH and the same file in DDR*/
+// if (CompareMem((void *)MONITOR_DDR_BASE, (void *)MONITOR_FLASH_BASE, MONITOR_COPY_SIZE) != 0)
+// {
+// (VOID)AsciiPrint("The .monitor file check fail!\n");
+// //return;
+// }
+// else
+// {
+// (VOID)AsciiPrint("The .monitor file check sucess!\n");
+// }
+
+ #ifdef NANDFLASHREAD
+ /* copy.kernel */
+ CopyNandToMem((void *)KERNEL_DDR_BASE, KERNEL_BLOCKNUM_NANDFLASH, KERNEL_COPY_SIZE);
+ (VOID)AsciiPrint("\nThe .kernel file is transmitted ok!\n");
+ #else
+ /* copy.kernel */
+ memcpy((void *)KERNEL_DDR_BASE, (void *)KERNEL_FLASH_BASE, KERNEL_COPY_SIZE);
+ (VOID)AsciiPrint("\nThe .kernel file is transmitted ok!\n");
+ #endif
+// /* compare kernel in FLASH and the same file in DDR*/
+// if (CompareMem((void *)KERNEL_DDR_BASE, (void *)KERNEL_FLASH_BASE, KERNEL_COPY_SIZE) != 0)
+// {
+// (VOID)AsciiPrint("The .kernel file check fail!\n");
+// //return;
+// }
+// else
+// {
+// (VOID)AsciiPrint("The .kernel file check sucess!\n\n");
+// }
+
+ #ifdef NANDFLASHREAD
+ CopyNandToMem((void *)FILESYSTEM_DDR_BASE, FILESYSTEM_BLOCKNUM_NANDFLASH, FILESYSTEM_COPY_SIZE);
+ (VOID)AsciiPrint("The .filesystem file is transmitted ok!\n");
+ #else
+ memcpy((void *)FILESYSTEM_DDR_BASE, (void *)FILESYSTEM_FLASH_BASE, FILESYSTEM_COPY_SIZE);
+ (VOID)AsciiPrint("The .filesystem file is transmitted ok!\n");
+ #endif
+
+// /* compare initrd in FLASH and the same file in DDR*/
+// if (CompareMem((void *)FILESYSTEM_DDR_BASE, (void *)FILESYSTEM_FLASH_BASE, FILESYSTEM_COPY_SIZE) != 0)
+// {
+// (VOID)AsciiPrint("The .filesystem file check fail!\n");
+// //return;
+// }
+// else
+// {
+// (VOID)AsciiPrint("The .filesystem file check sucess!\n\n");
+// }
+
+ /*---------------OS-----------------*/
+ BootOptionList (&BootOptionsList);
+ BootGo (&BootOptionsList);
+ #endif
+ }
+ (VOID)AsciiPrint("Press 's', Start Boot Menu!\n\n");
+
+ // Timer before initiating the default boot selection
+ StartDefaultBootOnTimeout ();
+
+ // Start the Boot Menu
+ Status = BootMenuMain ();
+ ASSERT_EFI_ERROR (Status);
+
+}
+
+EFI_BDS_ARCH_PROTOCOL gBdsProtocol = {
+ BdsEntry,
+};
+
+EFI_STATUS
+EFIAPI
+BdsInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ mImageHandle = ImageHandle;
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gEfiBdsArchProtocolGuid, &gBdsProtocol,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/HisiPkg/D01BoardPkg/Bds/Bds.inf b/HisiPkg/D01BoardPkg/Bds/Bds.inf new file mode 100644 index 000000000..f7416bf3c --- /dev/null +++ b/HisiPkg/D01BoardPkg/Bds/Bds.inf @@ -0,0 +1,84 @@ +#/** @file
+#
+# Component description file for Bds module
+#
+# Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmPlatformBds
+ FILE_GUID = 5a50aa81-c3ae-4608-a0e3-41a2e69baf94
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = BdsInitialize
+
+[Sources.common]
+ Bds.c
+ BdsHelper.c
+ BootMenu.c
+ BootOption.c
+ BootOptionSupport.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ HisiPkg/HisiPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+
+[LibraryClasses]
+ BdsLib
+ TimerLib
+ PerformanceLib
+ UefiBootServicesTableLib
+ DxeServicesTableLib
+ UefiDriverEntryPoint
+ DebugLib
+ PrintLib
+ BaseLib
+ ArmLib
+ BspUartLib
+
+[Guids]
+ gEfiFileSystemInfoGuid
+ gArmGlobalVariableGuid
+
+[Protocols]
+ gEfiBdsArchProtocolGuid
+ gEfiBlockIoProtocolGuid
+ gEfiSimpleTextInProtocolGuid
+ gEfiPxeBaseCodeProtocolGuid
+ gEfiSimpleNetworkProtocolGuid
+ gEfiDevicePathToTextProtocolGuid
+ gUniNorFlashProtocolGuid
+ gNANDDriverProtocolGuid
+
+[Pcd]
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootType
+ gArmPlatformTokenSpaceGuid.PcdFdtDevicePath
+ gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths
+ gHwTokenSpaceGuid.PcdNorFlashBase
+
+[Depex]
+ TRUE
diff --git a/HisiPkg/D01BoardPkg/Bds/BdsHelper.c b/HisiPkg/D01BoardPkg/Bds/BdsHelper.c new file mode 100644 index 000000000..c07b8af0f --- /dev/null +++ b/HisiPkg/D01BoardPkg/Bds/BdsHelper.c @@ -0,0 +1,416 @@ +/** @file
+*
+* Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "BdsInternal.h"
+
+EFI_STATUS
+EditHIInputStr (
+ IN OUT CHAR16 *CmdLine,
+ IN UINTN MaxCmdLine
+ )
+{
+ UINTN CmdLineIndex;
+ UINTN WaitIndex;
+ CHAR8 Char;
+ EFI_INPUT_KEY Key;
+ EFI_STATUS Status;
+
+ // The command line must be at least one character long
+ ASSERT (MaxCmdLine > 0);
+
+ // Ensure the last character of the buffer is the NULL character
+ CmdLine[MaxCmdLine - 1] = '\0';
+
+ Print (CmdLine);
+
+ // To prevent a buffer overflow, we only allow to enter (MaxCmdLine-1) characters
+ for (CmdLineIndex = StrLen (CmdLine); CmdLineIndex < MaxCmdLine; ) {
+ Status = gBS->WaitForEvent (1, &gST->ConIn->WaitForKey, &WaitIndex);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);
+ ASSERT_EFI_ERROR (Status);
+
+ // Unicode character is valid when Scancode is NUll
+ if (Key.ScanCode == SCAN_NULL) {
+ // Scan code is NUll, hence read Unicode character
+ Char = (CHAR8)Key.UnicodeChar;
+ } else {
+ Char = CHAR_NULL;
+ }
+
+ if ((Char == CHAR_LINEFEED) || (Char == CHAR_CARRIAGE_RETURN) || (Char == 0x7f)) {
+ CmdLine[CmdLineIndex] = '\0';
+ Print (L"\r\n");
+
+ return EFI_SUCCESS;
+ } else if ((Key.UnicodeChar == L'\b') || (Key.ScanCode == SCAN_LEFT) || (Key.ScanCode == SCAN_DELETE)){
+ if (CmdLineIndex != 0) {
+ CmdLineIndex--;
+ Print (L"\b \b");
+ }
+ } else if ((Key.ScanCode == SCAN_ESC) || (Char == 0x1B) || (Char == 0x0)) {
+ return EFI_INVALID_PARAMETER;
+ } else if (CmdLineIndex < (MaxCmdLine-1)) {
+ CmdLine[CmdLineIndex++] = Key.UnicodeChar;
+ Print (L"%c", Key.UnicodeChar);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+GetHIInputStr (
+ IN OUT CHAR16 *CmdLine,
+ IN UINTN MaxCmdLine
+ )
+{
+ EFI_STATUS Status;
+
+ // For a new input just passed an empty string
+ CmdLine[0] = L'\0';
+
+ Status = EditHIInputStr (CmdLine, MaxCmdLine);
+
+ return Status;
+}
+
+EFI_STATUS
+EditHIInputAscii (
+ IN OUT CHAR8 *CmdLine,
+ IN UINTN MaxCmdLine
+ )
+{
+ CHAR16* Str;
+ EFI_STATUS Status;
+
+ Str = (CHAR16*)AllocatePool (MaxCmdLine * sizeof(CHAR16));
+ AsciiStrToUnicodeStr (CmdLine, Str);
+
+ Status = EditHIInputStr (Str, MaxCmdLine);
+ if (!EFI_ERROR(Status)) {
+ UnicodeStrToAsciiStr (Str, CmdLine);
+ }
+ FreePool (Str);
+
+ return Status;
+}
+
+EFI_STATUS
+GetHIInputAscii (
+ IN OUT CHAR8 *CmdLine,
+ IN UINTN MaxCmdLine
+ )
+{
+ // For a new input just passed an empty string
+ CmdLine[0] = '\0';
+
+ return EditHIInputAscii (CmdLine,MaxCmdLine);
+}
+
+EFI_STATUS
+GetHIInputInteger (
+ OUT UINTN *Integer
+ )
+{
+ CHAR16 CmdLine[255];
+ EFI_STATUS Status;
+
+ CmdLine[0] = '\0';
+ Status = EditHIInputStr (CmdLine, 255);
+ if (!EFI_ERROR(Status)) {
+ *Integer = StrDecimalToUintn (CmdLine);
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+GetHIInputIP (
+ OUT EFI_IP_ADDRESS *Ip
+ )
+{
+ CHAR16 CmdLine[255];
+ CHAR16 *Str;
+ EFI_STATUS Status;
+
+ CmdLine[0] = '\0';
+ Status = EditHIInputStr (CmdLine,255);
+ if (!EFI_ERROR(Status)) {
+ Str = CmdLine;
+ Ip->v4.Addr[0] = (UINT8)StrDecimalToUintn (Str);
+
+ Str = StrStr (Str, L".");
+ if (Str == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Ip->v4.Addr[1] = (UINT8)StrDecimalToUintn (++Str);
+
+ Str = StrStr (Str, L".");
+ if (Str == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Ip->v4.Addr[2] = (UINT8)StrDecimalToUintn (++Str);
+
+ Str = StrStr (Str, L".");
+ if (Str == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Ip->v4.Addr[3] = (UINT8)StrDecimalToUintn (++Str);
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+GetHIInputBoolean (
+ OUT BOOLEAN *Value
+ )
+{
+ CHAR16 CmdBoolean[2];
+ EFI_STATUS Status;
+
+ while(1) {
+ Print (L"[y/n] ");
+ Status = GetHIInputStr (CmdBoolean, 2);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ } else if ((CmdBoolean[0] == L'y') || (CmdBoolean[0] == L'Y')) {
+ if (Value) *Value = TRUE;
+ return EFI_SUCCESS;
+ } else if ((CmdBoolean[0] == L'n') || (CmdBoolean[0] == L'N')) {
+ if (Value) *Value = FALSE;
+ return EFI_SUCCESS;
+ }
+ }
+}
+
+BOOLEAN
+HasFilePathEfiExtension (
+ IN CHAR16* FilePath
+ )
+{
+ return (StrCmp (FilePath + (StrSize (FilePath) / sizeof (CHAR16)) - 5, L".EFI") == 0) ||
+ (StrCmp (FilePath + (StrSize (FilePath) / sizeof (CHAR16)) - 5, L".efi") == 0);
+}
+
+// Return the last non end-type Device Path Node from a Device Path
+EFI_DEVICE_PATH*
+GetLastDevicePathNode (
+ IN EFI_DEVICE_PATH* DevicePath
+ )
+{
+ EFI_DEVICE_PATH* PrevDevicePathNode;
+
+ PrevDevicePathNode = DevicePath;
+ while (!IsDevicePathEndType (DevicePath)) {
+ PrevDevicePathNode = DevicePath;
+ DevicePath = NextDevicePathNode (DevicePath);
+ }
+
+ return PrevDevicePathNode;
+}
+
+EFI_STATUS
+GenerateDeviceDescriptionName (
+ IN EFI_HANDLE Handle,
+ IN OUT CHAR16* Description
+ )
+{
+ EFI_STATUS Status;
+ EFI_COMPONENT_NAME_PROTOCOL* ComponentName2Protocol;
+ EFI_DEVICE_PATH_TO_TEXT_PROTOCOL* DevicePathToTextProtocol;
+ EFI_DEVICE_PATH_PROTOCOL* DevicePathProtocol;
+ CHAR16* DriverName;
+ CHAR16* DevicePathTxt;
+ EFI_DEVICE_PATH* DevicePathNode;
+
+ ComponentName2Protocol = NULL;
+ Status = gBS->HandleProtocol (Handle, &gEfiComponentName2ProtocolGuid, (VOID **)&ComponentName2Protocol);
+ if (!EFI_ERROR(Status)) {
+ //TODO: Fixme. we must find the best langague
+ Status = ComponentName2Protocol->GetDriverName (ComponentName2Protocol,"en",&DriverName);
+ if (!EFI_ERROR(Status)) {
+ StrnCpy (Description, DriverName, BOOT_DEVICE_DESCRIPTION_MAX);
+ }
+ }
+
+ if (EFI_ERROR(Status)) {
+ // Use the lastest non null entry of the Device path as a description
+ Status = gBS->HandleProtocol (Handle, &gEfiDevicePathProtocolGuid, (VOID **)&DevicePathProtocol);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ // Convert the last non end-type Device Path Node in text for the description
+ DevicePathNode = GetLastDevicePathNode (DevicePathProtocol);
+ Status = gBS->LocateProtocol (&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol);
+ ASSERT_EFI_ERROR(Status);
+ DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText (DevicePathNode, TRUE, TRUE);
+ StrnCpy (Description, DevicePathTxt, BOOT_DEVICE_DESCRIPTION_MAX);
+ FreePool (DevicePathTxt);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+BdsStartBootOption (
+ IN CHAR16* BootOption
+ )
+{
+ EFI_STATUS Status;
+ BDS_LOAD_OPTION *BdsLoadOption;
+
+ Status = BootOptionFromLoadOptionVariable (BootOption, &BdsLoadOption);
+ if (!EFI_ERROR(Status)) {
+ Status = BootOptionStart (BdsLoadOption);
+ FreePool (BdsLoadOption);
+
+ if (!EFI_ERROR(Status)) {
+ Status = EFI_SUCCESS;
+ } else {
+ Status = EFI_NOT_STARTED;
+ }
+ } else {
+ Status = EFI_NOT_FOUND;
+ }
+ return Status;
+}
+
+UINTN
+GetUnalignedDevicePathSize (
+ IN EFI_DEVICE_PATH* DevicePath
+ )
+{
+ UINTN Size;
+ EFI_DEVICE_PATH* AlignedDevicePath;
+
+ if ((UINTN)DevicePath & 0x1) {
+ AlignedDevicePath = DuplicateDevicePath (DevicePath);
+ Size = GetDevicePathSize (AlignedDevicePath);
+ FreePool (AlignedDevicePath);
+ } else {
+ Size = GetDevicePathSize (DevicePath);
+ }
+ return Size;
+}
+
+EFI_DEVICE_PATH*
+GetAlignedDevicePath (
+ IN EFI_DEVICE_PATH* DevicePath
+ )
+{
+ if ((UINTN)DevicePath & 0x1) {
+ return DuplicateDevicePath (DevicePath);
+ } else {
+ return DevicePath;
+ }
+}
+
+BOOLEAN
+IsUnicodeString (
+ IN VOID* String
+ )
+{
+ // We do not support NULL pointer
+ ASSERT (String != NULL);
+
+ if (*(CHAR16*)String < 0x100) {
+ //Note: We could get issue if the string is an empty Ascii string...
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+}
+
+/*
+ * Try to detect if the given string is an ASCII or Unicode string
+ *
+ * There are actually few limitation to this function but it is mainly to give
+ * a user friendly output.
+ *
+ * Some limitations:
+ * - it only supports unicode string that use ASCII character (< 0x100)
+ * - single character ASCII strings are interpreted as Unicode string
+ * - string cannot be longer than 2 x BOOT_DEVICE_OPTION_MAX (600 bytes)
+ *
+ * @param String Buffer that might contain a Unicode or Ascii string
+ * @param IsUnicode If not NULL this boolean value returns if the string is an
+ * ASCII or Unicode string.
+ */
+BOOLEAN
+IsPrintableString (
+ IN VOID* String,
+ OUT BOOLEAN *IsUnicode
+ )
+{
+ BOOLEAN UnicodeDetected;
+ BOOLEAN IsPrintable;
+ UINTN Index;
+ CHAR16 Character;
+
+ // We do not support NULL pointer
+ ASSERT (String != NULL);
+
+ // Test empty string
+ if (*(CHAR16*)String == L'\0') {
+ if (IsUnicode) {
+ *IsUnicode = TRUE;
+ }
+ return TRUE;
+ } else if (*(CHAR16*)String == '\0') {
+ if (IsUnicode) {
+ *IsUnicode = FALSE;
+ }
+ return TRUE;
+ }
+
+ // Limitation: if the string is an ASCII single character string. This comparison
+ // will assume it is a Unicode string.
+ if (*(CHAR16*)String < 0x100) {
+ UnicodeDetected = TRUE;
+ } else {
+ UnicodeDetected = FALSE;
+ }
+
+ IsPrintable = FALSE;
+ for (Index = 0; Index < BOOT_DEVICE_OPTION_MAX * 2; Index++) {
+ if (UnicodeDetected) {
+ Character = ((CHAR16*)String)[Index];
+ } else {
+ Character = ((CHAR8*)String)[Index];
+ }
+
+ if (Character == '\0') {
+ // End of the string
+ IsPrintable = TRUE;
+ break;
+ } else if ((Character < 0x20) || (Character > 0x7f)) {
+ // We only support the range of printable ASCII character
+ IsPrintable = FALSE;
+ break;
+ }
+ }
+
+ if (IsPrintable && IsUnicode) {
+ *IsUnicode = UnicodeDetected;
+ }
+
+ return IsPrintable;
+}
diff --git a/HisiPkg/D01BoardPkg/Bds/BdsInternal.h b/HisiPkg/D01BoardPkg/Bds/BdsInternal.h new file mode 100644 index 000000000..447b8c9cd --- /dev/null +++ b/HisiPkg/D01BoardPkg/Bds/BdsInternal.h @@ -0,0 +1,281 @@ +/** @file
+*
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _BDSINTERNAL_H_
+#define _BDSINTERNAL_H_
+
+#include <PiDxe.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/BdsLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/UefiLib.h>
+#include <Library/PrintLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+
+#include <Protocol/DevicePathFromText.h>
+#include <Protocol/DevicePathToText.h>
+
+#include <Guid/GlobalVariable.h>
+
+#define BOOT_DEVICE_DESCRIPTION_MAX 100
+#define BOOT_DEVICE_FILEPATH_MAX 100
+#define BOOT_DEVICE_OPTION_MAX 300
+#define BOOT_DEVICE_ADDRESS_MAX (sizeof(L"0x0000000000000000"))
+
+#define ARM_BDS_OPTIONAL_DATA_SIGNATURE SIGNATURE_32('a', 'b', 'o', 'd')
+
+#define IS_ARM_BDS_BOOTENTRY(ptr) \
+ (((ptr)->OptionalData != NULL) && \
+ (ReadUnaligned32 ((CONST UINT32*)&((ARM_BDS_LOADER_OPTIONAL_DATA*)((ptr)->OptionalData))->Header.Signature) \
+ == ARM_BDS_OPTIONAL_DATA_SIGNATURE))
+
+#define UPDATE_BOOT_ENTRY L"Update entry: "
+#define DELETE_BOOT_ENTRY L"Delete entry: "
+
+typedef enum {
+ BDS_LOADER_EFI_APPLICATION = 0,
+ BDS_LOADER_KERNEL_LINUX_ATAG,
+ BDS_LOADER_KERNEL_LINUX_FDT,
+} ARM_BDS_LOADER_TYPE;
+
+typedef struct {
+ UINT16 CmdLineSize;
+ UINT16 InitrdSize;
+
+ // These following fields have variable length and are packed:
+ //CHAR8 *CmdLine;
+ //EFI_DEVICE_PATH_PROTOCOL *InitrdPathList;
+} ARM_BDS_LINUX_ARGUMENTS;
+
+typedef union {
+ ARM_BDS_LINUX_ARGUMENTS LinuxArguments;
+} ARM_BDS_LOADER_ARGUMENTS;
+
+typedef struct {
+ UINT32 Signature;
+ ARM_BDS_LOADER_TYPE LoaderType;
+} ARM_BDS_LOADER_OPTIONAL_DATA_HEADER;
+
+typedef struct {
+ ARM_BDS_LOADER_OPTIONAL_DATA_HEADER Header;
+ ARM_BDS_LOADER_ARGUMENTS Arguments;
+} ARM_BDS_LOADER_OPTIONAL_DATA;
+
+typedef struct {
+ LIST_ENTRY Link;
+ BDS_LOAD_OPTION* BdsLoadOption;
+} BDS_LOAD_OPTION_ENTRY;
+
+typedef enum {
+ BDS_DEVICE_FILESYSTEM = 0,
+ BDS_DEVICE_MEMMAP,
+ BDS_DEVICE_PXE,
+ BDS_DEVICE_TFTP,
+ BDS_DEVICE_MAX
+} BDS_SUPPORTED_DEVICE_TYPE;
+
+typedef struct {
+ LIST_ENTRY Link;
+ CHAR16 Description[BOOT_DEVICE_DESCRIPTION_MAX];
+ EFI_DEVICE_PATH_PROTOCOL* DevicePathProtocol;
+ struct _BDS_LOAD_OPTION_SUPPORT* Support;
+} BDS_SUPPORTED_DEVICE;
+
+#define SUPPORTED_BOOT_DEVICE_FROM_LINK(a) BASE_CR(a, BDS_SUPPORTED_DEVICE, Link)
+
+typedef struct _BDS_LOAD_OPTION_SUPPORT {
+ BDS_SUPPORTED_DEVICE_TYPE Type;
+ EFI_STATUS (*ListDevices)(IN OUT LIST_ENTRY* BdsLoadOptionList);
+ BOOLEAN (*IsSupported)(IN EFI_DEVICE_PATH *DevicePath);
+ EFI_STATUS (*CreateDevicePathNode)(IN CHAR16* FileName, OUT EFI_DEVICE_PATH_PROTOCOL **DevicePathNodes, OUT BOOLEAN *RequestBootType);
+ EFI_STATUS (*UpdateDevicePathNode)(IN EFI_DEVICE_PATH *OldDevicePath, IN CHAR16* FileName, OUT EFI_DEVICE_PATH_PROTOCOL** NewDevicePath, OUT BOOLEAN *RequestBootType);
+} BDS_LOAD_OPTION_SUPPORT;
+
+#define LOAD_OPTION_ENTRY_FROM_LINK(a) BASE_CR(a, BDS_LOAD_OPTION_ENTRY, Link)
+#define LOAD_OPTION_FROM_LINK(a) ((BDS_LOAD_OPTION_ENTRY*)BASE_CR(a, BDS_LOAD_OPTION_ENTRY, Link))->BdsLoadOption
+
+EFI_STATUS
+BootDeviceListSupportedInit (
+ IN OUT LIST_ENTRY *SupportedDeviceList
+ );
+
+EFI_STATUS
+BootDeviceListSupportedFree (
+ IN LIST_ENTRY *SupportedDeviceList,
+ IN BDS_SUPPORTED_DEVICE *Except
+ );
+
+EFI_STATUS
+BootDeviceGetDeviceSupport (
+ IN EFI_DEVICE_PATH *DevicePath,
+ OUT BDS_LOAD_OPTION_SUPPORT **DeviceSupport
+ );
+
+EFI_STATUS
+GetHIInputStr (
+ IN OUT CHAR16 *CmdLine,
+ IN UINTN MaxCmdLine
+ );
+
+EFI_STATUS
+EditHIInputStr (
+ IN OUT CHAR16 *CmdLine,
+ IN UINTN MaxCmdLine
+ );
+
+EFI_STATUS
+GetHIInputAscii (
+ IN OUT CHAR8 *CmdLine,
+ IN UINTN MaxCmdLine
+ );
+
+EFI_STATUS
+EditHIInputAscii (
+ IN OUT CHAR8 *CmdLine,
+ IN UINTN MaxCmdLine
+ );
+
+EFI_STATUS
+GetHIInputInteger (
+ IN OUT UINTN *Integer
+ );
+
+EFI_STATUS
+GetHIInputIP (
+ OUT EFI_IP_ADDRESS *Ip
+ );
+
+EFI_STATUS
+GetHIInputBoolean (
+ OUT BOOLEAN *Value
+ );
+
+BOOLEAN
+HasFilePathEfiExtension (
+ IN CHAR16* FilePath
+ );
+
+EFI_DEVICE_PATH*
+GetLastDevicePathNode (
+ IN EFI_DEVICE_PATH* DevicePath
+ );
+
+EFI_STATUS
+BdsStartBootOption (
+ IN CHAR16* BootOption
+ );
+
+UINTN
+GetUnalignedDevicePathSize (
+ IN EFI_DEVICE_PATH* DevicePath
+ );
+
+EFI_DEVICE_PATH*
+GetAlignedDevicePath (
+ IN EFI_DEVICE_PATH* DevicePath
+ );
+
+EFI_STATUS
+GenerateDeviceDescriptionName (
+ IN EFI_HANDLE Handle,
+ IN OUT CHAR16* Description
+ );
+
+EFI_STATUS
+BootOptionList (
+ IN OUT LIST_ENTRY *BootOptionList
+ );
+
+EFI_STATUS
+BootOptionParseLoadOption (
+ IN EFI_LOAD_OPTION EfiLoadOption,
+ IN UINTN EfiLoadOptionSize,
+ OUT BDS_LOAD_OPTION **BdsLoadOption
+ );
+
+EFI_STATUS
+BootOptionStart (
+ IN BDS_LOAD_OPTION *BootOption
+ );
+
+EFI_STATUS
+BootOptionCreate (
+ IN UINT32 Attributes,
+ IN CHAR16* BootDescription,
+ IN EFI_DEVICE_PATH_PROTOCOL* DevicePath,
+ IN ARM_BDS_LOADER_TYPE BootType,
+ IN UINT8* OptionalData,
+ IN UINTN OptionalDataSize,
+ OUT BDS_LOAD_OPTION** BdsLoadOption
+ );
+
+EFI_STATUS
+BootOptionUpdate (
+ IN BDS_LOAD_OPTION* BdsLoadOption,
+ IN UINT32 Attributes,
+ IN CHAR16* BootDescription,
+ IN EFI_DEVICE_PATH_PROTOCOL* DevicePath,
+ IN ARM_BDS_LOADER_TYPE BootType,
+ IN UINT8* OptionalData,
+ IN UINTN OptionalDataSize
+ );
+
+EFI_STATUS
+BootOptionDelete (
+ IN BDS_LOAD_OPTION *BootOption
+ );
+
+EFI_STATUS
+BootDeviceGetType (
+ IN EFI_DEVICE_PATH* DevicePath,
+ OUT ARM_BDS_LOADER_TYPE *BootType,
+ OUT UINT32 *Attributes
+ );
+
+EFI_STATUS
+BootMenuMain (
+ VOID
+ );
+
+BOOLEAN
+IsUnicodeString (
+ IN VOID* String
+ );
+
+/*
+ * Try to detect if the given string is an ASCII or Unicode string
+ *
+ * There are actually few limitation to this function but it is mainly to give
+ * a user friendly output.
+ *
+ * Some limitations:
+ * - it only supports unicode string that use ASCII character (< 0x100)
+ * - single character ASCII strings are interpreted as Unicode string
+ * - string cannot be longer than 2 x BOOT_DEVICE_OPTION_MAX (600 bytes)
+ *
+ * @param String Buffer that might contain a Unicode or Ascii string
+ * @param IsUnicode If not NULL this boolean value returns if the string is an
+ * ASCII or Unicode string.
+ */
+BOOLEAN
+IsPrintableString (
+ IN VOID* String,
+ OUT BOOLEAN *IsUnicode
+ );
+
+#endif /* _BDSINTERNAL_H_ */
diff --git a/HisiPkg/D01BoardPkg/Bds/BootMenu.c b/HisiPkg/D01BoardPkg/Bds/BootMenu.c new file mode 100644 index 000000000..c9cc4b08d --- /dev/null +++ b/HisiPkg/D01BoardPkg/Bds/BootMenu.c @@ -0,0 +1,967 @@ +/** @file
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "BdsInternal.h"
+#include <Guid/ArmGlobalVariableHob.h>
+#include <Library/ArmLib.h>
+#include <Library/BrdCommon.h>
+
+typedef int (*LinuxEntry)();
+
+extern EFI_HANDLE mImageHandle;
+extern BDS_LOAD_OPTION_SUPPORT *BdsLoadOptionSupportList;
+extern EFI_STATUS
+ShutdownUefiBootServices (
+ VOID
+ );
+
+EFI_STATUS
+SelectBootDevice (
+ OUT BDS_SUPPORTED_DEVICE** SupportedBootDevice
+ )
+{
+ EFI_STATUS Status;
+ LIST_ENTRY SupportedDeviceList;
+ UINTN SupportedDeviceCount;
+ LIST_ENTRY* Entry;
+ UINTN SupportedDeviceSelected;
+ UINTN Index;
+
+ //
+ // List the Boot Devices supported
+ //
+
+ // Start all the drivers first
+ BdsConnectAllDrivers ();
+
+ // List the supported devices
+ Status = BootDeviceListSupportedInit (&SupportedDeviceList);
+ ASSERT_EFI_ERROR(Status);
+
+ SupportedDeviceCount = 0;
+ for (Entry = GetFirstNode (&SupportedDeviceList);
+ !IsNull (&SupportedDeviceList,Entry);
+ Entry = GetNextNode (&SupportedDeviceList,Entry)
+ )
+ {
+ *SupportedBootDevice = SUPPORTED_BOOT_DEVICE_FROM_LINK(Entry);
+ Print(L"[%d] %s\n",SupportedDeviceCount+1,(*SupportedBootDevice)->Description);
+
+ DEBUG_CODE_BEGIN();
+ CHAR16* DevicePathTxt;
+ EFI_DEVICE_PATH_TO_TEXT_PROTOCOL* DevicePathToTextProtocol;
+
+ Status = gBS->LocateProtocol (&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol);
+ ASSERT_EFI_ERROR(Status);
+ DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText ((*SupportedBootDevice)->DevicePathProtocol,TRUE,TRUE);
+
+ Print(L"\t- %s\n",DevicePathTxt);
+
+ FreePool(DevicePathTxt);
+ DEBUG_CODE_END();
+
+ SupportedDeviceCount++;
+ }
+
+ if (SupportedDeviceCount == 0) {
+ Print(L"There is no supported device.\n");
+ Status = EFI_ABORTED;
+ goto EXIT;
+ }
+
+ //
+ // Select the Boot Device
+ //
+ SupportedDeviceSelected = 0;
+ while (SupportedDeviceSelected == 0) {
+ Print(L"Select the Boot Device: ");
+ Status = GetHIInputInteger (&SupportedDeviceSelected);
+ if (EFI_ERROR(Status)) {
+ Status = EFI_ABORTED;
+ goto EXIT;
+ } else if ((SupportedDeviceSelected == 0) || (SupportedDeviceSelected > SupportedDeviceCount)) {
+ Print(L"Invalid input (max %d)\n",SupportedDeviceCount);
+ SupportedDeviceSelected = 0;
+ }
+ }
+
+ //
+ // Get the Device Path for the selected boot device
+ //
+ Index = 1;
+ for (Entry = GetFirstNode (&SupportedDeviceList);
+ !IsNull (&SupportedDeviceList,Entry);
+ Entry = GetNextNode (&SupportedDeviceList,Entry)
+ )
+ {
+ if (Index == SupportedDeviceSelected) {
+ *SupportedBootDevice = SUPPORTED_BOOT_DEVICE_FROM_LINK(Entry);
+ break;
+ }
+ Index++;
+ }
+
+EXIT:
+ BootDeviceListSupportedFree (&SupportedDeviceList, *SupportedBootDevice);
+ return Status;
+}
+
+EFI_STATUS
+BootMenuAddBootOption (
+ IN LIST_ENTRY *BootOptionsList
+ )
+{
+ EFI_STATUS Status;
+ BDS_SUPPORTED_DEVICE* SupportedBootDevice;
+ ARM_BDS_LOADER_ARGUMENTS* BootArguments;
+ CHAR16 BootDescription[BOOT_DEVICE_DESCRIPTION_MAX];
+ CHAR8 AsciiCmdLine[BOOT_DEVICE_OPTION_MAX];
+ CHAR16 CmdLine[BOOT_DEVICE_OPTION_MAX];
+ UINT32 Attributes;
+ ARM_BDS_LOADER_TYPE BootType;
+ BDS_LOAD_OPTION_ENTRY *BdsLoadOptionEntry;
+ EFI_DEVICE_PATH *DevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePathNodes;
+ EFI_DEVICE_PATH_PROTOCOL *InitrdPathNodes;
+ EFI_DEVICE_PATH_PROTOCOL *InitrdPath;
+ UINTN CmdLineSize;
+ BOOLEAN InitrdSupport;
+ UINTN InitrdSize;
+ UINT8* OptionalData;
+ UINTN OptionalDataSize;
+ BOOLEAN RequestBootType;
+
+ Attributes = 0;
+ SupportedBootDevice = NULL;
+
+ // List the Boot Devices supported
+ Status = SelectBootDevice (&SupportedBootDevice);
+ if (EFI_ERROR(Status)) {
+ Status = EFI_ABORTED;
+ goto EXIT;
+ }
+
+ // Create the specific device path node
+ RequestBootType = TRUE;
+ Status = SupportedBootDevice->Support->CreateDevicePathNode (L"EFI Application or the kernel", &DevicePathNodes, &RequestBootType);
+ if (EFI_ERROR(Status)) {
+ Status = EFI_ABORTED;
+ goto EXIT;
+ }
+ // Append the Device Path to the selected device path
+ DevicePath = AppendDevicePath (SupportedBootDevice->DevicePathProtocol, (CONST EFI_DEVICE_PATH_PROTOCOL *)DevicePathNodes);
+ if (DevicePath == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto EXIT;
+ }
+
+ if (RequestBootType) {
+ Status = BootDeviceGetType (DevicePath, &BootType, &Attributes);
+ if (EFI_ERROR(Status)) {
+ Status = EFI_ABORTED;
+ goto EXIT;
+ }
+ } else {
+ BootType = BDS_LOADER_EFI_APPLICATION;
+ }
+
+ if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_FDT)) {
+ Print(L"Add an initrd: ");
+ Status = GetHIInputBoolean (&InitrdSupport);
+ if (EFI_ERROR(Status)) {
+ Status = EFI_ABORTED;
+ goto EXIT;
+ }
+
+ if (InitrdSupport) {
+ // Create the specific device path node
+ Status = SupportedBootDevice->Support->CreateDevicePathNode (L"initrd", &InitrdPathNodes, NULL);
+ if (EFI_ERROR(Status) && Status != EFI_NOT_FOUND) { // EFI_NOT_FOUND is returned on empty input string, but we can boot without an initrd
+ Status = EFI_ABORTED;
+ goto EXIT;
+ }
+
+ if (InitrdPathNodes != NULL) {
+ // Append the Device Path to the selected device path
+ InitrdPath = AppendDevicePath (SupportedBootDevice->DevicePathProtocol, (CONST EFI_DEVICE_PATH_PROTOCOL *)InitrdPathNodes);
+ if (InitrdPath == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto EXIT;
+ }
+ } else {
+ InitrdPath = NULL;
+ }
+ } else {
+ InitrdPath = NULL;
+ }
+
+ Print(L"Arguments to pass to the binary: ");
+ Status = GetHIInputAscii (AsciiCmdLine, BOOT_DEVICE_OPTION_MAX);
+ if (EFI_ERROR(Status)) {
+ Status = EFI_ABORTED;
+ goto FREE_DEVICE_PATH;
+ }
+
+ CmdLineSize = AsciiStrSize (AsciiCmdLine);
+ InitrdSize = GetDevicePathSize (InitrdPath);
+
+ OptionalDataSize = sizeof(ARM_BDS_LOADER_ARGUMENTS) + CmdLineSize + InitrdSize;
+ BootArguments = (ARM_BDS_LOADER_ARGUMENTS*)AllocatePool (OptionalDataSize);
+
+ BootArguments->LinuxArguments.CmdLineSize = CmdLineSize;
+ BootArguments->LinuxArguments.InitrdSize = InitrdSize;
+ CopyMem ((VOID*)(&BootArguments->LinuxArguments + 1), CmdLine, CmdLineSize);
+ CopyMem ((VOID*)((UINTN)(&BootArguments->LinuxArguments + 1) + CmdLineSize), InitrdPath, InitrdSize);
+
+ OptionalData = (UINT8*)BootArguments;
+ } else {
+ Print (L"Arguments to pass to the EFI Application: ");
+ Status = GetHIInputStr (CmdLine, BOOT_DEVICE_OPTION_MAX);
+ if (EFI_ERROR (Status)) {
+ Status = EFI_ABORTED;
+ goto EXIT;
+ }
+
+ OptionalData = (UINT8*)CmdLine;
+ OptionalDataSize = StrSize (CmdLine);
+ }
+
+ Print(L"Description for this new Entry: ");
+ Status = GetHIInputStr (BootDescription, BOOT_DEVICE_DESCRIPTION_MAX);
+ if (EFI_ERROR(Status)) {
+ Status = EFI_ABORTED;
+ goto FREE_DEVICE_PATH;
+ }
+
+ // Create new entry
+ BdsLoadOptionEntry = (BDS_LOAD_OPTION_ENTRY*)AllocatePool (sizeof(BDS_LOAD_OPTION_ENTRY));
+ Status = BootOptionCreate (Attributes, BootDescription, DevicePath, BootType, OptionalData, OptionalDataSize, &BdsLoadOptionEntry->BdsLoadOption);
+ if (!EFI_ERROR(Status)) {
+ InsertTailList (BootOptionsList, &BdsLoadOptionEntry->Link);
+ }
+
+FREE_DEVICE_PATH:
+ FreePool (DevicePath);
+
+EXIT:
+ if (Status == EFI_ABORTED) {
+ Print(L"\n");
+ }
+ FreePool(SupportedBootDevice);
+ return Status;
+}
+
+STATIC
+EFI_STATUS
+BootMenuSelectBootOption (
+ IN LIST_ENTRY* BootOptionsList,
+ IN CONST CHAR16* InputStatement,
+ OUT BDS_LOAD_OPTION_ENTRY** BdsLoadOptionEntry
+ )
+{
+ EFI_STATUS Status;
+ LIST_ENTRY* Entry;
+ BDS_LOAD_OPTION* BdsLoadOption;
+ UINTN BootOptionSelected;
+ UINTN BootOptionCount;
+ UINTN Index;
+ BOOLEAN IsUnicode;
+
+ // Display the list of supported boot devices
+ BootOptionCount = 0;
+ for (Entry = GetFirstNode (BootOptionsList);
+ !IsNull (BootOptionsList,Entry);
+ Entry = GetNextNode (BootOptionsList, Entry)
+ )
+ {
+ BdsLoadOption = LOAD_OPTION_FROM_LINK(Entry);
+
+ Print (L"[%d] %s\n", (BootOptionCount + 1), BdsLoadOption->Description);
+
+ DEBUG_CODE_BEGIN();
+ CHAR16* DevicePathTxt;
+ EFI_DEVICE_PATH_TO_TEXT_PROTOCOL* DevicePathToTextProtocol;
+ ARM_BDS_LOADER_TYPE LoaderType;
+ ARM_BDS_LOADER_OPTIONAL_DATA* OptionalData;
+
+ Status = gBS->LocateProtocol(&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol);
+ ASSERT_EFI_ERROR(Status);
+ DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText(BdsLoadOption->FilePathList,TRUE,TRUE);
+
+ Print(L"\t- %s\n",DevicePathTxt);
+ OptionalData = BdsLoadOption->OptionalData;
+ if (IS_ARM_BDS_BOOTENTRY (BdsLoadOption)) {
+ LoaderType = (ARM_BDS_LOADER_TYPE)ReadUnaligned32 ((CONST UINT32*)&OptionalData->Header.LoaderType);
+ if ((LoaderType == BDS_LOADER_KERNEL_LINUX_ATAG) || (LoaderType == BDS_LOADER_KERNEL_LINUX_FDT)) {
+ Print (L"\t- Arguments: %a\n",&OptionalData->Arguments.LinuxArguments + 1);
+ }
+ } else if (OptionalData != NULL) {
+ if (IsPrintableString (OptionalData, &IsUnicode)) {
+ if (IsUnicode) {
+ Print (L"\t- Arguments: %s\n", OptionalData);
+ } else {
+ AsciiPrint ("\t- Arguments: %a\n", OptionalData);
+ }
+ }
+ }
+
+ FreePool(DevicePathTxt);
+ DEBUG_CODE_END();
+
+ BootOptionCount++;
+ }
+
+ // Check if a valid boot option(s) is found
+ if (BootOptionCount == 0) {
+ if (StrCmp (InputStatement, DELETE_BOOT_ENTRY) == 0) {
+ Print (L"Nothing to remove!\n");
+ } else if (StrCmp (InputStatement, UPDATE_BOOT_ENTRY) == 0) {
+ Print (L"Couldn't find valid boot entries\n");
+ } else{
+ Print (L"No supported Boot Entry.\n");
+ }
+
+ return EFI_NOT_FOUND;
+ }
+
+ // Get the index of the boot device to delete
+ BootOptionSelected = 0;
+ while (BootOptionSelected == 0) {
+ Print(InputStatement);
+ Status = GetHIInputInteger (&BootOptionSelected);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ } else if ((BootOptionSelected == 0) || (BootOptionSelected > BootOptionCount)) {
+ Print(L"Invalid input (max %d)\n",BootOptionCount);
+ BootOptionSelected = 0;
+ }
+ }
+
+ // Get the structure of the Boot device to delete
+ Index = 1;
+ for (Entry = GetFirstNode (BootOptionsList);
+ !IsNull (BootOptionsList, Entry);
+ Entry = GetNextNode (BootOptionsList,Entry)
+ )
+ {
+ if (Index == BootOptionSelected) {
+ *BdsLoadOptionEntry = LOAD_OPTION_ENTRY_FROM_LINK(Entry);
+ break;
+ }
+ Index++;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+BootMenuRemoveBootOption (
+ IN LIST_ENTRY *BootOptionsList
+ )
+{
+ EFI_STATUS Status;
+ BDS_LOAD_OPTION_ENTRY* BootOptionEntry;
+
+ Status = BootMenuSelectBootOption (BootOptionsList, DELETE_BOOT_ENTRY, &BootOptionEntry);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ // If the Boot Option was attached to a list remove it
+ if (!IsListEmpty (&BootOptionEntry->Link)) {
+ // Remove the entry from the list
+ RemoveEntryList (&BootOptionEntry->Link);
+ }
+
+ // Delete the BDS Load option structures
+ BootOptionDelete (BootOptionEntry->BdsLoadOption);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+BootMenuUpdateBootOption (
+ IN LIST_ENTRY *BootOptionsList
+ )
+{
+ EFI_STATUS Status;
+ BDS_LOAD_OPTION_ENTRY *BootOptionEntry;
+ BDS_LOAD_OPTION *BootOption;
+ BDS_LOAD_OPTION_SUPPORT* DeviceSupport;
+ ARM_BDS_LOADER_ARGUMENTS* BootArguments;
+ CHAR16 BootDescription[BOOT_DEVICE_DESCRIPTION_MAX];
+ CHAR8 CmdLine[BOOT_DEVICE_OPTION_MAX];
+ CHAR16 UnicodeCmdLine[BOOT_DEVICE_OPTION_MAX];
+ EFI_DEVICE_PATH *DevicePath;
+ EFI_DEVICE_PATH *TempInitrdPath;
+ ARM_BDS_LOADER_TYPE BootType;
+ ARM_BDS_LOADER_OPTIONAL_DATA* LoaderOptionalData;
+ ARM_BDS_LINUX_ARGUMENTS* LinuxArguments;
+ EFI_DEVICE_PATH *InitrdPathNodes;
+ EFI_DEVICE_PATH *InitrdPath;
+ UINTN InitrdSize;
+ UINTN CmdLineSize;
+ BOOLEAN InitrdSupport;
+ UINT8* OptionalData;
+ UINTN OptionalDataSize;
+ BOOLEAN RequestBootType;
+ BOOLEAN IsPrintable;
+ BOOLEAN IsUnicode;
+
+ Status = BootMenuSelectBootOption (BootOptionsList, UPDATE_BOOT_ENTRY, &BootOptionEntry);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ BootOption = BootOptionEntry->BdsLoadOption;
+
+ // Get the device support for this Boot Option
+ Status = BootDeviceGetDeviceSupport (BootOption->FilePathList, &DeviceSupport);
+ if (EFI_ERROR(Status)) {
+ Print(L"Not possible to retrieve the supported device for the update\n");
+ return EFI_UNSUPPORTED;
+ }
+
+ RequestBootType = TRUE;
+ Status = DeviceSupport->UpdateDevicePathNode (BootOption->FilePathList, L"EFI Application or the kernel", &DevicePath, &RequestBootType);
+ if (EFI_ERROR(Status)) {
+ Status = EFI_ABORTED;
+ goto EXIT;
+ }
+
+ if (RequestBootType) {
+ Status = BootDeviceGetType (DevicePath, &BootType, &BootOption->Attributes);
+ if (EFI_ERROR(Status)) {
+ Status = EFI_ABORTED;
+ goto EXIT;
+ }
+ }
+
+ LoaderOptionalData = BootOption->OptionalData;
+ if (LoaderOptionalData != NULL) {
+ BootType = (ARM_BDS_LOADER_TYPE)ReadUnaligned32 ((UINT32 *)(&LoaderOptionalData->Header.LoaderType));
+ } else {
+ BootType = BDS_LOADER_EFI_APPLICATION;
+ }
+
+ if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_FDT)) {
+ LinuxArguments = &LoaderOptionalData->Arguments.LinuxArguments;
+
+ CmdLineSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->CmdLineSize);
+
+ InitrdSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->InitrdSize);
+ if (InitrdSize > 0) {
+ Print(L"Keep the initrd: ");
+ } else {
+ Print(L"Add an initrd: ");
+ }
+ Status = GetHIInputBoolean (&InitrdSupport);
+ if (EFI_ERROR(Status)) {
+ Status = EFI_ABORTED;
+ goto EXIT;
+ }
+
+ if (InitrdSupport) {
+ if (InitrdSize > 0) {
+ // Case we update the initrd device path
+ Status = DeviceSupport->UpdateDevicePathNode ((EFI_DEVICE_PATH*)((UINTN)(LinuxArguments + 1) + CmdLineSize), L"initrd", &InitrdPath, NULL);
+ if (EFI_ERROR(Status) && Status != EFI_NOT_FOUND) {// EFI_NOT_FOUND is returned on empty input string, but we can boot without an initrd
+ Status = EFI_ABORTED;
+ goto EXIT;
+ }
+ InitrdSize = GetDevicePathSize (InitrdPath);
+ } else {
+ // Case we create the initrd device path
+
+ Status = DeviceSupport->CreateDevicePathNode (L"initrd", &InitrdPathNodes, NULL);
+ if (EFI_ERROR(Status) && Status != EFI_NOT_FOUND) { // EFI_NOT_FOUND is returned on empty input string, but we can boot without an initrd
+ Status = EFI_ABORTED;
+ goto EXIT;
+ }
+
+ if (InitrdPathNodes != NULL) {
+ // Duplicate Linux kernel Device Path
+ TempInitrdPath = DuplicateDevicePath (BootOption->FilePathList);
+ // Replace Linux kernel Node by EndNode
+ SetDevicePathEndNode (GetLastDevicePathNode (TempInitrdPath));
+ // Append the Device Path to the selected device path
+ InitrdPath = AppendDevicePath (TempInitrdPath, (CONST EFI_DEVICE_PATH_PROTOCOL *)InitrdPathNodes);
+ FreePool (TempInitrdPath);
+ if (InitrdPath == NULL) {
+ Status = EFI_OUT_OF_RESOURCES;
+ goto EXIT;
+ }
+ InitrdSize = GetDevicePathSize (InitrdPath);
+ } else {
+ InitrdPath = NULL;
+ }
+ }
+ } else {
+ InitrdSize = 0;
+ }
+
+ Print(L"Arguments to pass to the binary: ");
+ if (CmdLineSize > 0) {
+ AsciiStrnCpy(CmdLine, (CONST CHAR8*)(LinuxArguments + 1), CmdLineSize);
+ } else {
+ CmdLine[0] = '\0';
+ }
+ Status = EditHIInputAscii (CmdLine, BOOT_DEVICE_OPTION_MAX);
+ if (EFI_ERROR(Status)) {
+ Status = EFI_ABORTED;
+ goto FREE_DEVICE_PATH;
+ }
+
+ CmdLineSize = AsciiStrSize (CmdLine);
+
+ OptionalDataSize = sizeof(ARM_BDS_LOADER_ARGUMENTS) + CmdLineSize + InitrdSize;
+ BootArguments = (ARM_BDS_LOADER_ARGUMENTS*)AllocatePool (OptionalDataSize);
+ BootArguments->LinuxArguments.CmdLineSize = CmdLineSize;
+ BootArguments->LinuxArguments.InitrdSize = InitrdSize;
+ CopyMem (&BootArguments->LinuxArguments + 1, CmdLine, CmdLineSize);
+ CopyMem ((VOID*)((UINTN)(&BootArguments->LinuxArguments + 1) + CmdLineSize), InitrdPath, InitrdSize);
+
+ OptionalData = (UINT8*)BootArguments;
+ } else {
+ Print (L"Arguments to pass to the EFI Application: ");
+
+ if (BootOption->OptionalDataSize > 0) {
+ IsPrintable = IsPrintableString (BootOption->OptionalData, &IsUnicode);
+ if (IsPrintable) {
+ if (IsUnicode) {
+ StrnCpy (UnicodeCmdLine, BootOption->OptionalData, BootOption->OptionalDataSize / 2);
+ } else {
+ AsciiStrnCpy (CmdLine, BootOption->OptionalData, BootOption->OptionalDataSize);
+ }
+ }
+ } else {
+ UnicodeCmdLine[0] = L'\0';
+ IsPrintable = TRUE;
+ IsUnicode = TRUE;
+ }
+
+ // We do not request arguments for OptionalData that cannot be printed
+ if (IsPrintable) {
+ if (IsUnicode) {
+ Status = EditHIInputStr (UnicodeCmdLine, BOOT_DEVICE_OPTION_MAX);
+ if (EFI_ERROR (Status)) {
+ Status = EFI_ABORTED;
+ goto FREE_DEVICE_PATH;
+ }
+
+ OptionalData = (UINT8*)UnicodeCmdLine;
+ OptionalDataSize = StrSize (UnicodeCmdLine);
+ } else {
+ Status = EditHIInputAscii (CmdLine, BOOT_DEVICE_OPTION_MAX);
+ if (EFI_ERROR (Status)) {
+ Status = EFI_ABORTED;
+ goto FREE_DEVICE_PATH;
+ }
+
+ OptionalData = (UINT8*)CmdLine;
+ OptionalDataSize = AsciiStrSize (CmdLine);
+ }
+ } else {
+ // We keep the former OptionalData
+ OptionalData = BootOption->OptionalData;
+ OptionalDataSize = BootOption->OptionalDataSize;
+ }
+ }
+
+ Print(L"Description for this new Entry: ");
+ StrnCpy (BootDescription, BootOption->Description, BOOT_DEVICE_DESCRIPTION_MAX);
+ Status = EditHIInputStr (BootDescription, BOOT_DEVICE_DESCRIPTION_MAX);
+ if (EFI_ERROR(Status)) {
+ Status = EFI_ABORTED;
+ goto FREE_DEVICE_PATH;
+ }
+
+ // Update the entry
+ Status = BootOptionUpdate (BootOption, BootOption->Attributes, BootDescription, DevicePath, BootType, OptionalData, OptionalDataSize);
+
+FREE_DEVICE_PATH:
+ FreePool (DevicePath);
+
+EXIT:
+ if (Status == EFI_ABORTED) {
+ Print(L"\n");
+ }
+ return Status;
+}
+
+EFI_STATUS
+UpdateFdtPath (
+ IN LIST_ENTRY *BootOptionsList
+ )
+{
+ EFI_STATUS Status;
+ UINTN FdtDevicePathSize;
+ BDS_SUPPORTED_DEVICE *SupportedBootDevice;
+ EFI_DEVICE_PATH_PROTOCOL *FdtDevicePathNodes;
+ EFI_DEVICE_PATH_PROTOCOL *FdtDevicePath;
+
+ Status = SelectBootDevice (&SupportedBootDevice);
+ if (EFI_ERROR(Status)) {
+ Status = EFI_ABORTED;
+ goto EXIT;
+ }
+
+ // Create the specific device path node
+ Status = SupportedBootDevice->Support->CreateDevicePathNode (L"FDT blob", &FdtDevicePathNodes, NULL);
+ if (EFI_ERROR(Status)) {
+ Status = EFI_ABORTED;
+ goto EXIT;
+ }
+
+ if (FdtDevicePathNodes != NULL) {
+ // Append the Device Path node to the select device path
+ FdtDevicePath = AppendDevicePath (SupportedBootDevice->DevicePathProtocol, FdtDevicePathNodes);
+ FdtDevicePathSize = GetDevicePathSize (FdtDevicePath);
+ Status = gRT->SetVariable (
+ (CHAR16*)L"Fdt",
+ &gArmGlobalVariableGuid,
+ EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
+ FdtDevicePathSize,
+ FdtDevicePath
+ );
+ ASSERT_EFI_ERROR(Status);
+ } else {
+ gRT->SetVariable (
+ (CHAR16*)L"Fdt",
+ &gArmGlobalVariableGuid,
+ EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
+ 0,
+ NULL
+ );
+ ASSERT_EFI_ERROR(Status);
+ }
+
+EXIT:
+ if (Status == EFI_ABORTED) {
+ Print(L"\n");
+ }
+ FreePool(SupportedBootDevice);
+ return Status;
+}
+
+struct BOOT_MANAGER_ENTRY {
+ CONST CHAR16* Description;
+ EFI_STATUS (*Callback) (IN LIST_ENTRY *BootOptionsList);
+} BootManagerEntries[] = {
+ { L"Add Boot Device Entry", BootMenuAddBootOption },
+ { L"Update Boot Device Entry", BootMenuUpdateBootOption },
+ { L"Remove Boot Device Entry", BootMenuRemoveBootOption },
+ { L"Update FDT path", UpdateFdtPath },
+};
+
+EFI_STATUS
+BootMenuManager (
+ IN LIST_ENTRY *BootOptionsList
+ )
+{
+ UINTN Index;
+ UINTN OptionSelected;
+ UINTN BootManagerEntryCount;
+ EFI_STATUS Status;
+
+ BootManagerEntryCount = sizeof(BootManagerEntries) / sizeof(struct BOOT_MANAGER_ENTRY);
+
+ while (TRUE) {
+ // Display Boot Manager menu
+ for (Index = 0; Index < BootManagerEntryCount; Index++) {
+ Print(L"[%d] %s\n",Index+1,BootManagerEntries[Index]);
+ }
+ Print(L"[%d] Return to main menu\n",Index+1);
+
+ // Select which entry to call
+ Print(L"Choice: ");
+ Status = GetHIInputInteger (&OptionSelected);
+ if (EFI_ERROR(Status) || (OptionSelected == (BootManagerEntryCount+1))) {
+ if (EFI_ERROR(Status)) {
+ Print(L"\n");
+ }
+ return EFI_SUCCESS;
+ } else if ((OptionSelected > 0) && (OptionSelected <= BootManagerEntryCount)) {
+ BootManagerEntries[OptionSelected-1].Callback (BootOptionsList);
+ }
+ }
+ // Should never go here
+}
+
+EFI_STATUS
+BootEBL (
+ IN LIST_ENTRY *BootOptionsList
+ )
+{
+ EFI_STATUS Status;
+
+ // Start EFI Shell
+ Status = BdsLoadApplication (mImageHandle, (CHAR16 *)L"Ebl", 0, NULL);
+ if (Status == EFI_NOT_FOUND) {
+ Print ((CHAR16 *)L"Error: EFI Application not found.\n");
+ } else if (EFI_ERROR(Status)) {
+ Print ((CHAR16 *)L"Error: Status Code: 0x%X\n",(UINT32)Status);
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+BootShell (
+ IN LIST_ENTRY *BootOptionsList
+ )
+{
+ EFI_STATUS Status;
+
+ // Start EFI Shell
+ Status = BdsLoadApplication (mImageHandle, L"Shell", 0, NULL);
+ if (Status == EFI_NOT_FOUND) {
+ Print (L"Error: EFI Application not found.\n");
+ } else if (EFI_ERROR(Status)) {
+ Print (L"Error: Status Code: 0x%X\n",(UINT32)Status);
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+Reboot (
+ IN LIST_ENTRY *BootOptionsList
+ )
+{
+ gRT->ResetSystem(EfiResetCold, EFI_SUCCESS, 0, NULL);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+Shutdown (
+ IN LIST_ENTRY *BootOptionsList
+ )
+{
+ gRT->ResetSystem(EfiResetShutdown, EFI_SUCCESS, 0, NULL);
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+BootLinuxAtagLoader (
+ IN LIST_ENTRY *BootOptionsList
+ )
+{
+ EFI_STATUS Status;
+
+ Status = BdsLoadApplication (mImageHandle, (CHAR16 *)L"LinuxAtagLoader", 0, NULL);
+ if (Status == EFI_NOT_FOUND) {
+ Print ((CHAR16 *)L"Error: EFI Application linuxloader not found.\n");
+ } else if (EFI_ERROR(Status)) {
+ Print ((CHAR16 *)L"Error: Status Code: 0x%X\n",(UINT32)Status);
+ }
+
+ return Status;
+}
+
+EFI_STATUS LoadLinuxAtSecEnd()
+{
+ LinuxEntry entry = (LinuxEntry)(0x10c00000);
+ EFI_STATUS Status = EFI_SUCCESS;
+ ArmDisableDataCache();
+ ArmCleanInvalidateDataCache();
+ ArmDisableInstructionCache ();
+ ArmInvalidateInstructionCache ();
+ ArmDisableMmu();
+ DEBUG(( EFI_D_ERROR, "MOVE PC 0x10c00000\n"));
+ (void)entry();
+ return Status;
+}
+
+EFI_STATUS
+BootGo (
+ IN LIST_ENTRY *BootOptionsList
+ )
+{
+ EFI_STATUS Status;
+
+ Status = ShutdownUefiBootServices ();
+ if(EFI_ERROR(Status)) {
+ DEBUG((EFI_D_ERROR,"ERROR: Can not shutdown UEFI boot services. Status=0x%X\n", Status));
+ }
+
+ *(UINTN*)(UINTN)(0xe302b000 + 0x18) = 0;
+ *(UINTN*)(UINTN)(0xe302b000 + 0x1c) = 0;
+
+ *(volatile UINT32 *)(0xe0000000 + 0x100) = 0x10c00000;
+ ArmCleanDataCache();
+ *(UINT8*)(0xf4007000) = 'G';
+ Status = LoadLinuxAtSecEnd();
+ if (EFI_ERROR(Status))
+ {
+ (VOID)AsciiPrint ("GoCmd error!\n");
+ }
+
+ return Status;
+}
+
+struct BOOT_MAIN_ENTRY {
+ CONST CHAR16* Description;
+ EFI_STATUS (*Callback) (IN LIST_ENTRY *BootOptionsList);
+} BootMainEntries[] = {
+ { L"Boot Manager", BootMenuManager },
+ { L"EBL", BootEBL },
+ { L"Shell", BootShell },
+ { L"Reboot", Reboot },
+ { L"Shutdown", Shutdown },
+ { L"GO", BootGo },
+};
+
+
+EFI_STATUS
+BootMenuMain (
+ VOID
+ )
+{
+ LIST_ENTRY BootOptionsList;
+ UINTN OptionCount;
+ UINTN BootOptionCount;
+ EFI_STATUS Status;
+ LIST_ENTRY* Entry;
+ BDS_LOAD_OPTION* BootOption;
+ UINTN BootOptionSelected;
+ UINTN Index;
+ UINTN BootMainEntryCount;
+ BOOLEAN IsUnicode;
+
+ BootOption = NULL;
+ BootMainEntryCount = sizeof(BootMainEntries) / sizeof(struct BOOT_MAIN_ENTRY);
+
+ while (TRUE) {
+ // Get Boot#### list
+ BootOptionList (&BootOptionsList);
+
+ OptionCount = 1;
+
+ // Display the Boot options
+ for (Entry = GetFirstNode (&BootOptionsList);
+ !IsNull (&BootOptionsList,Entry);
+ Entry = GetNextNode (&BootOptionsList,Entry)
+ )
+ {
+ BootOption = LOAD_OPTION_FROM_LINK(Entry);
+
+ Print(L"[%d] %s\n", OptionCount, BootOption->Description);
+
+ DEBUG_CODE_BEGIN();
+ CHAR16* DevicePathTxt;
+ EFI_DEVICE_PATH_TO_TEXT_PROTOCOL* DevicePathToTextProtocol;
+ ARM_BDS_LOADER_OPTIONAL_DATA* OptionalData;
+ UINTN CmdLineSize;
+ ARM_BDS_LOADER_TYPE LoaderType;
+
+ Status = gBS->LocateProtocol (&gEfiDevicePathToTextProtocolGuid, NULL, (VOID **)&DevicePathToTextProtocol);
+ if (EFI_ERROR(Status)) {
+ // You must provide an implementation of DevicePathToTextProtocol in your firmware (eg: DevicePathDxe)
+ DEBUG((EFI_D_ERROR,"Error: Bds requires DevicePathToTextProtocol\n"));
+ return Status;
+ }
+ DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText (BootOption->FilePathList, TRUE, TRUE);
+
+ Print(L"\t- %s\n",DevicePathTxt);
+
+ // If it is a supported BootEntry then print its details
+ if (IS_ARM_BDS_BOOTENTRY (BootOption)) {
+ OptionalData = BootOption->OptionalData;
+ LoaderType = (ARM_BDS_LOADER_TYPE)ReadUnaligned32 ((CONST UINT32*)&OptionalData->Header.LoaderType);
+ if ((LoaderType == BDS_LOADER_KERNEL_LINUX_ATAG) || (LoaderType == BDS_LOADER_KERNEL_LINUX_FDT)) {
+ if (ReadUnaligned16 (&OptionalData->Arguments.LinuxArguments.InitrdSize) > 0) {
+ CmdLineSize = ReadUnaligned16 (&OptionalData->Arguments.LinuxArguments.CmdLineSize);
+ DevicePathTxt = DevicePathToTextProtocol->ConvertDevicePathToText (
+ GetAlignedDevicePath ((EFI_DEVICE_PATH*)((UINTN)(&OptionalData->Arguments.LinuxArguments + 1) + CmdLineSize)), TRUE, TRUE);
+ Print(L"\t- Initrd: %s\n", DevicePathTxt);
+ }
+ if (ReadUnaligned16 (&OptionalData->Arguments.LinuxArguments.CmdLineSize) > 0) {
+ Print(L"\t- Arguments: %a\n", (&OptionalData->Arguments.LinuxArguments + 1));
+ }
+ }
+
+ switch (LoaderType) {
+ case BDS_LOADER_EFI_APPLICATION:
+ Print(L"\t- LoaderType: EFI Application\n");
+ break;
+
+ case BDS_LOADER_KERNEL_LINUX_ATAG:
+ Print(L"\t- LoaderType: Linux kernel with ATAG support\n");
+ break;
+
+ case BDS_LOADER_KERNEL_LINUX_FDT:
+ Print(L"\t- LoaderType: Linux kernel with FDT support\n");
+ break;
+
+ default:
+ Print(L"\t- LoaderType: Not recognized (%d)\n", LoaderType);
+ }
+ } else if (BootOption->OptionalData != NULL) {
+ if (IsPrintableString (BootOption->OptionalData, &IsUnicode)) {
+ if (IsUnicode) {
+ Print (L"\t- Arguments: %s\n", BootOption->OptionalData);
+ } else {
+ AsciiPrint ("\t- Arguments: %a\n", BootOption->OptionalData);
+ }
+ }
+ }
+ FreePool(DevicePathTxt);
+ DEBUG_CODE_END();
+
+ OptionCount++;
+ }
+ BootOptionCount = OptionCount-1;
+
+ // Display the hardcoded Boot entries
+ for (Index = 0; Index < BootMainEntryCount; Index++) {
+ Print(L"[%d] %s\n",OptionCount,BootMainEntries[Index]);
+ OptionCount++;
+ }
+
+ // Request the boot entry from the user
+ BootOptionSelected = 0;
+ while (BootOptionSelected == 0) {
+ Print(L"Start: ");
+ Status = GetHIInputInteger (&BootOptionSelected);
+ if (EFI_ERROR(Status) || (BootOptionSelected == 0) || (BootOptionSelected > OptionCount)) {
+ Print(L"Invalid input (max %d)\n",(OptionCount-1));
+ BootOptionSelected = 0;
+ }
+ }
+
+ // Start the selected entry
+ if (BootOptionSelected > BootOptionCount) {
+ // Start the hardcoded entry
+ Status = BootMainEntries[BootOptionSelected - BootOptionCount - 1].Callback (&BootOptionsList);
+ } else {
+ // Find the selected entry from the Boot#### list
+ Index = 1;
+ for (Entry = GetFirstNode (&BootOptionsList);
+ !IsNull (&BootOptionsList,Entry);
+ Entry = GetNextNode (&BootOptionsList,Entry)
+ )
+ {
+ if (Index == BootOptionSelected) {
+ BootOption = LOAD_OPTION_FROM_LINK(Entry);
+ break;
+ }
+ Index++;
+ }
+
+ Status = BootOptionStart (BootOption);
+ }
+ }
+ // Should never go here
+}
diff --git a/HisiPkg/D01BoardPkg/Bds/BootOption.c b/HisiPkg/D01BoardPkg/Bds/BootOption.c new file mode 100644 index 000000000..52c9d831b --- /dev/null +++ b/HisiPkg/D01BoardPkg/Bds/BootOption.c @@ -0,0 +1,407 @@ +/** @file
+*
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Guid/ArmGlobalVariableHob.h>
+#include "BdsInternal.h"
+
+extern EFI_HANDLE mImageHandle;
+
+EFI_STATUS
+BootOptionStart (
+ IN BDS_LOAD_OPTION *BootOption
+ )
+{
+ EFI_STATUS Status;
+ EFI_DEVICE_PATH_FROM_TEXT_PROTOCOL* EfiDevicePathFromTextProtocol;
+ UINT32 LoaderType;
+ ARM_BDS_LOADER_OPTIONAL_DATA* OptionalData;
+ ARM_BDS_LINUX_ARGUMENTS* LinuxArguments;
+ EFI_DEVICE_PATH_PROTOCOL* FdtDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL* DefaultFdtDevicePath;
+ UINTN FdtDevicePathSize;
+ UINTN CmdLineSize;
+ UINTN InitrdSize;
+ EFI_DEVICE_PATH* Initrd;
+ UINT16 LoadOptionIndexSize;
+
+ if (IS_ARM_BDS_BOOTENTRY (BootOption)) {
+ Status = EFI_UNSUPPORTED;
+ OptionalData = BootOption->OptionalData;
+ LoaderType = ReadUnaligned32 ((CONST UINT32*)&OptionalData->Header.LoaderType);
+
+ if (LoaderType == BDS_LOADER_EFI_APPLICATION) {
+ if ((BootOption->Attributes & LOAD_OPTION_CATEGORY_BOOT) == 0) {
+ // Need to connect every drivers to ensure no dependencies are missing for the application
+ BdsConnectAllDrivers ();
+ }
+
+ Status = BdsStartEfiApplication (mImageHandle, BootOption->FilePathList, 0, NULL);
+ } else if (LoaderType == BDS_LOADER_KERNEL_LINUX_ATAG) {
+ LinuxArguments = &(OptionalData->Arguments.LinuxArguments);
+ CmdLineSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->CmdLineSize);
+ InitrdSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->InitrdSize);
+
+ if (InitrdSize > 0) {
+ Initrd = GetAlignedDevicePath ((EFI_DEVICE_PATH*)((UINTN)(LinuxArguments + 1) + CmdLineSize));
+ } else {
+ Initrd = NULL;
+ }
+
+ Status = BdsBootLinuxAtag (BootOption->FilePathList,
+ Initrd, // Initrd
+ (CHAR8*)(LinuxArguments + 1)); // CmdLine
+ } else if (LoaderType == BDS_LOADER_KERNEL_LINUX_FDT) {
+ LinuxArguments = &(OptionalData->Arguments.LinuxArguments);
+ CmdLineSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->CmdLineSize);
+ InitrdSize = ReadUnaligned16 ((CONST UINT16*)&LinuxArguments->InitrdSize);
+
+ if (InitrdSize > 0) {
+ Initrd = GetAlignedDevicePath ((EFI_DEVICE_PATH*)((UINTN)(LinuxArguments + 1) + CmdLineSize));
+ } else {
+ Initrd = NULL;
+ }
+
+ // Get the default FDT device path
+ Status = gBS->LocateProtocol (&gEfiDevicePathFromTextProtocolGuid, NULL, (VOID **)&EfiDevicePathFromTextProtocol);
+ ASSERT_EFI_ERROR(Status);
+ DefaultFdtDevicePath = EfiDevicePathFromTextProtocol->ConvertTextToDevicePath ((CHAR16*)PcdGetPtr(PcdFdtDevicePath));
+
+ // Get the FDT device path
+ FdtDevicePathSize = GetDevicePathSize (DefaultFdtDevicePath);
+ Status = GetEnvironmentVariable ((CHAR16 *)L"Fdt", &gArmGlobalVariableGuid,
+ DefaultFdtDevicePath, &FdtDevicePathSize, (VOID **)&FdtDevicePath);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = BdsBootLinuxFdt (BootOption->FilePathList,
+ Initrd, // Initrd
+ (CHAR8*)(LinuxArguments + 1),
+ FdtDevicePath);
+
+ FreePool (DefaultFdtDevicePath);
+ FreePool (FdtDevicePath);
+ }
+ } else {
+ // Connect all the drivers if the EFI Application is not a EFI OS Loader
+ if ((BootOption->Attributes & LOAD_OPTION_CATEGORY_BOOT) == 0) {
+ BdsConnectAllDrivers ();
+ }
+
+ // Set BootCurrent variable
+ LoadOptionIndexSize = sizeof(UINT16);
+ gRT->SetVariable (L"BootCurrent", &gEfiGlobalVariableGuid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ LoadOptionIndexSize, &(BootOption->LoadOptionIndex));
+
+ Status = BdsStartEfiApplication (mImageHandle, BootOption->FilePathList, BootOption->OptionalDataSize, BootOption->OptionalData);
+
+ // Clear BootCurrent variable
+ LoadOptionIndexSize = sizeof(UINT16);
+ gRT->SetVariable (L"BootCurrent", &gEfiGlobalVariableGuid,
+ EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ 0, NULL);
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+BootOptionList (
+ IN OUT LIST_ENTRY *BootOptionList
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ UINT16* BootOrder;
+ UINTN BootOrderSize;
+ BDS_LOAD_OPTION* BdsLoadOption;
+ BDS_LOAD_OPTION_ENTRY* BdsLoadOptionEntry;
+
+ InitializeListHead (BootOptionList);
+
+ // Get the Boot Option Order from the environment variable
+ Status = GetGlobalEnvironmentVariable (L"BootOrder", NULL, &BootOrderSize, (VOID**)&BootOrder);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ for (Index = 0; Index < BootOrderSize / sizeof (UINT16); Index++) {
+ Status = BootOptionFromLoadOptionIndex (BootOrder[Index], &BdsLoadOption);
+ if (!EFI_ERROR(Status)) {
+ BdsLoadOptionEntry = (BDS_LOAD_OPTION_ENTRY*)AllocatePool(sizeof(BDS_LOAD_OPTION_ENTRY));
+ BdsLoadOptionEntry->BdsLoadOption = BdsLoadOption;
+ InsertTailList (BootOptionList,&BdsLoadOptionEntry->Link);
+ }
+ }
+
+ FreePool (BootOrder);
+
+ return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+BootOptionSetFields (
+ IN BDS_LOAD_OPTION* BootOption,
+ IN UINT32 Attributes,
+ IN CHAR16* BootDescription,
+ IN EFI_DEVICE_PATH_PROTOCOL* DevicePath,
+ IN ARM_BDS_LOADER_TYPE BootType,
+ IN UINT8* OptionalData,
+ IN UINTN OptionalDataSize
+ )
+{
+ EFI_LOAD_OPTION EfiLoadOption;
+ UINTN EfiLoadOptionSize;
+ UINTN BootDescriptionSize;
+ UINT16 FilePathListLength;
+ UINT8* EfiLoadOptionPtr;
+ UINT8* InitrdPathListPtr;
+ ARM_BDS_LINUX_ARGUMENTS* DestLinuxArguments;
+ ARM_BDS_LINUX_ARGUMENTS* SrcLinuxArguments;
+ ARM_BDS_LOADER_ARGUMENTS* BootArguments;
+
+ // If we are overwriting an existent Boot Option then we have to free previously allocated memory
+ if (BootOption->LoadOption) {
+ FreePool (BootOption->LoadOption);
+ }
+
+ BootDescriptionSize = StrSize (BootDescription);
+
+ // Fixup the size in case of entry specific to ArmPlatformPkg/Bds
+ if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_FDT)) {
+ OptionalDataSize += sizeof(ARM_BDS_LOADER_OPTIONAL_DATA_HEADER);
+ }
+
+ // Compute the size of the FilePath list
+ FilePathListLength = GetUnalignedDevicePathSize (DevicePath);
+
+ // Allocate the memory for the EFI Load Option
+ EfiLoadOptionSize = sizeof(UINT32) + sizeof(UINT16) + BootDescriptionSize + FilePathListLength + OptionalDataSize;
+ EfiLoadOption = (EFI_LOAD_OPTION)AllocatePool(EfiLoadOptionSize);
+ EfiLoadOptionPtr = EfiLoadOption;
+
+ //
+ // Populate the EFI Load Option and BDS Boot Option structures
+ //
+
+ // Attributes fields
+ BootOption->Attributes = Attributes;
+ *(UINT32*)EfiLoadOptionPtr = Attributes;
+ EfiLoadOptionPtr += sizeof(UINT32);
+
+ // FilePath List fields
+ BootOption->FilePathListLength = FilePathListLength;
+ *(UINT16*)EfiLoadOptionPtr = FilePathListLength;
+ EfiLoadOptionPtr += sizeof(UINT16);
+
+ // Boot description fields
+ BootOption->Description = (CHAR16*)EfiLoadOptionPtr;
+ CopyMem (EfiLoadOptionPtr, BootDescription, BootDescriptionSize);
+ EfiLoadOptionPtr += BootDescriptionSize;
+
+ // File path fields
+ BootOption->FilePathList = (EFI_DEVICE_PATH_PROTOCOL*)EfiLoadOptionPtr;
+ CopyMem (EfiLoadOptionPtr, DevicePath, FilePathListLength);
+ EfiLoadOptionPtr += FilePathListLength;
+
+ // Optional Data fields, Do unaligned writes
+ BootOption->OptionalData = EfiLoadOptionPtr;
+
+ if ((BootType == BDS_LOADER_KERNEL_LINUX_ATAG) || (BootType == BDS_LOADER_KERNEL_LINUX_FDT)) {
+ // Write the header
+ WriteUnaligned32 ((UINT32 *)EfiLoadOptionPtr, ARM_BDS_OPTIONAL_DATA_SIGNATURE);
+ WriteUnaligned32 ((UINT32 *)(EfiLoadOptionPtr + 4), BootType);
+
+ BootArguments = (ARM_BDS_LOADER_ARGUMENTS*)OptionalData;
+ SrcLinuxArguments = &(BootArguments->LinuxArguments);
+ DestLinuxArguments = &((ARM_BDS_LOADER_OPTIONAL_DATA*)EfiLoadOptionPtr)->Arguments.LinuxArguments;
+
+ WriteUnaligned16 ((UINT16 *)&(DestLinuxArguments->CmdLineSize), SrcLinuxArguments->CmdLineSize);
+ WriteUnaligned16 ((UINT16 *)&(DestLinuxArguments->InitrdSize), SrcLinuxArguments->InitrdSize);
+
+ if (SrcLinuxArguments->CmdLineSize > 0) {
+ CopyMem ((VOID*)(DestLinuxArguments + 1), (VOID*)(SrcLinuxArguments + 1), SrcLinuxArguments->CmdLineSize);
+ }
+
+ if (SrcLinuxArguments->InitrdSize > 0) {
+ InitrdPathListPtr = (UINT8*)((UINTN)(DestLinuxArguments + 1) + SrcLinuxArguments->CmdLineSize);
+ CopyMem (InitrdPathListPtr, (VOID*)((UINTN)(SrcLinuxArguments + 1) + SrcLinuxArguments->CmdLineSize), SrcLinuxArguments->InitrdSize);
+ }
+ } else {
+ CopyMem (BootOption->OptionalData, OptionalData, OptionalDataSize);
+ }
+ BootOption->OptionalDataSize = OptionalDataSize;
+
+ // If this function is called at the creation of the Boot Device entry (not at the update) the
+ // BootOption->LoadOptionSize must be zero then we get a new BootIndex for this entry
+ if (BootOption->LoadOptionSize == 0) {
+ BootOption->LoadOptionIndex = BootOptionAllocateBootIndex ();
+ }
+
+ // Fill the EFI Load option fields
+ BootOption->LoadOption = EfiLoadOption;
+ BootOption->LoadOptionSize = EfiLoadOptionSize;
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+BootOptionCreate (
+ IN UINT32 Attributes,
+ IN CHAR16* BootDescription,
+ IN EFI_DEVICE_PATH_PROTOCOL* DevicePath,
+ IN ARM_BDS_LOADER_TYPE BootType,
+ IN UINT8* OptionalData,
+ IN UINTN OptionalDataSize,
+ OUT BDS_LOAD_OPTION** BdsLoadOption
+ )
+{
+ EFI_STATUS Status;
+ BDS_LOAD_OPTION_ENTRY* BootOptionEntry;
+ BDS_LOAD_OPTION* BootOption;
+ CHAR16 BootVariableName[9];
+ UINT16* BootOrder;
+ UINTN BootOrderSize;
+
+ //
+ // Allocate and fill the memory for the BDS Load Option structure
+ //
+ BootOptionEntry = (BDS_LOAD_OPTION_ENTRY*)AllocatePool (sizeof (BDS_LOAD_OPTION_ENTRY));
+ InitializeListHead (&BootOptionEntry->Link);
+ BootOptionEntry->BdsLoadOption = (BDS_LOAD_OPTION*)AllocateZeroPool (sizeof(BDS_LOAD_OPTION));
+
+ BootOption = BootOptionEntry->BdsLoadOption;
+ BootOptionSetFields (BootOption, Attributes, BootDescription, DevicePath, BootType, OptionalData, OptionalDataSize);
+
+ //
+ // Set the related environment variables
+ //
+
+ // Create Boot#### environment variable
+ UnicodeSPrint (BootVariableName, 9 * sizeof(CHAR16), L"Boot%04X", BootOption->LoadOptionIndex);
+ Status = gRT->SetVariable (
+ BootVariableName,
+ &gEfiGlobalVariableGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ BootOption->LoadOptionSize,
+ BootOption->LoadOption
+ );
+
+ // Add the new Boot Index to the list
+ Status = GetGlobalEnvironmentVariable (L"BootOrder", NULL, &BootOrderSize, (VOID**)&BootOrder);
+ if (!EFI_ERROR(Status)) {
+ BootOrder = ReallocatePool (BootOrderSize, BootOrderSize + sizeof(UINT16), BootOrder);
+ // Add the new index at the end
+ BootOrder[BootOrderSize / sizeof(UINT16)] = BootOption->LoadOptionIndex;
+ BootOrderSize += sizeof(UINT16);
+ } else {
+ // BootOrder does not exist. Create it
+ BootOrderSize = sizeof(UINT16);
+ BootOrder = &(BootOption->LoadOptionIndex);
+ }
+
+ // Update (or Create) the BootOrder environment variable
+ Status = gRT->SetVariable (
+ L"BootOrder",
+ &gEfiGlobalVariableGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ BootOrderSize,
+ BootOrder
+ );
+
+ // We only free it if the UEFI Variable 'BootOrder' was already existing
+ if (BootOrderSize > sizeof(UINT16)) {
+ FreePool (BootOrder);
+ }
+
+ *BdsLoadOption = BootOption;
+ return Status;
+}
+
+EFI_STATUS
+BootOptionUpdate (
+ IN BDS_LOAD_OPTION* BdsLoadOption,
+ IN UINT32 Attributes,
+ IN CHAR16* BootDescription,
+ IN EFI_DEVICE_PATH_PROTOCOL* DevicePath,
+ IN ARM_BDS_LOADER_TYPE BootType,
+ IN UINT8* OptionalData,
+ IN UINTN OptionalDataSize
+ )
+{
+ EFI_STATUS Status;
+ CHAR16 BootVariableName[9];
+
+ // Update the BDS Load Option structure
+ BootOptionSetFields (BdsLoadOption, Attributes, BootDescription, DevicePath, BootType, OptionalData, OptionalDataSize);
+
+ // Update the related environment variables
+ UnicodeSPrint (BootVariableName, 9 * sizeof(CHAR16), L"Boot%04X", BdsLoadOption->LoadOptionIndex);
+
+ Status = gRT->SetVariable (
+ BootVariableName,
+ &gEfiGlobalVariableGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ BdsLoadOption->LoadOptionSize,
+ BdsLoadOption->LoadOption
+ );
+
+ return Status;
+}
+
+EFI_STATUS
+BootOptionDelete (
+ IN BDS_LOAD_OPTION *BootOption
+ )
+{
+ UINTN Index;
+ UINTN BootOrderSize;
+ UINT16* BootOrder;
+ UINTN BootOrderCount;
+ EFI_STATUS Status;
+
+ // Remove the entry from the BootOrder environment variable
+ Status = GetGlobalEnvironmentVariable (L"BootOrder", NULL, &BootOrderSize, (VOID**)&BootOrder);
+ if (!EFI_ERROR(Status)) {
+ BootOrderCount = BootOrderSize / sizeof(UINT16);
+
+ // Find the index of the removed entry
+ for (Index = 0; Index < BootOrderCount; Index++) {
+ if (BootOrder[Index] == BootOption->LoadOptionIndex) {
+ // If it the last entry we do not need to rearrange the BootOrder list
+ if (Index + 1 != BootOrderCount) {
+ CopyMem (
+ &BootOrder[Index],
+ &BootOrder[Index + 1],
+ (BootOrderCount - (Index + 1)) * sizeof(UINT16)
+ );
+ }
+ break;
+ }
+ }
+
+ // Update the BootOrder environment variable
+ Status = gRT->SetVariable (
+ L"BootOrder",
+ &gEfiGlobalVariableGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ BootOrderSize - sizeof(UINT16),
+ BootOrder
+ );
+ }
+
+ FreePool (BootOrder);
+
+ return EFI_SUCCESS;
+}
diff --git a/HisiPkg/D01BoardPkg/Bds/BootOptionSupport.c b/HisiPkg/D01BoardPkg/Bds/BootOptionSupport.c new file mode 100644 index 000000000..dc70dc4a1 --- /dev/null +++ b/HisiPkg/D01BoardPkg/Bds/BootOptionSupport.c @@ -0,0 +1,942 @@ +/** @file
+*
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "BdsInternal.h"
+
+#include <Library/NetLib.h>
+
+#include <Protocol/BlockIo.h>
+#include <Protocol/DevicePathToText.h>
+#include <Protocol/PxeBaseCode.h>
+#include <Protocol/SimpleFileSystem.h>
+#include <Protocol/SimpleNetwork.h>
+
+#include <Guid/FileSystemInfo.h>
+
+#define IS_DEVICE_PATH_NODE(node,type,subtype) (((node)->Type == (type)) && ((node)->SubType == (subtype)))
+
+EFI_STATUS
+BdsLoadOptionFileSystemList (
+ IN OUT LIST_ENTRY* BdsLoadOptionList
+ );
+
+EFI_STATUS
+BdsLoadOptionFileSystemCreateDevicePath (
+ IN CHAR16* FileName,
+ OUT EFI_DEVICE_PATH_PROTOCOL **DevicePathNodes,
+ OUT BOOLEAN *RequestBootType
+ );
+
+EFI_STATUS
+BdsLoadOptionFileSystemUpdateDevicePath (
+ IN EFI_DEVICE_PATH *OldDevicePath,
+ IN CHAR16* FileName,
+ OUT EFI_DEVICE_PATH_PROTOCOL **NewDevicePath,
+ OUT BOOLEAN *RequestBootType
+ );
+
+BOOLEAN
+BdsLoadOptionFileSystemIsSupported (
+ IN EFI_DEVICE_PATH *DevicePath
+ );
+
+EFI_STATUS
+BdsLoadOptionMemMapList (
+ IN OUT LIST_ENTRY* BdsLoadOptionList
+ );
+
+EFI_STATUS
+BdsLoadOptionMemMapCreateDevicePath (
+ IN CHAR16* FileName,
+ OUT EFI_DEVICE_PATH_PROTOCOL **DevicePathNodes,
+ OUT BOOLEAN *RequestBootType
+ );
+
+EFI_STATUS
+BdsLoadOptionMemMapUpdateDevicePath (
+ IN EFI_DEVICE_PATH *OldDevicePath,
+ IN CHAR16* FileName,
+ OUT EFI_DEVICE_PATH_PROTOCOL **NewDevicePath,
+ OUT BOOLEAN *RequestBootType
+ );
+
+BOOLEAN
+BdsLoadOptionMemMapIsSupported (
+ IN EFI_DEVICE_PATH *DevicePath
+ );
+
+EFI_STATUS
+BdsLoadOptionPxeList (
+ IN OUT LIST_ENTRY* BdsLoadOptionList
+ );
+
+EFI_STATUS
+BdsLoadOptionPxeCreateDevicePath (
+ IN CHAR16* FileName,
+ OUT EFI_DEVICE_PATH_PROTOCOL **DevicePathNodes,
+ OUT BOOLEAN *RequestBootType
+ );
+
+EFI_STATUS
+BdsLoadOptionPxeUpdateDevicePath (
+ IN EFI_DEVICE_PATH *OldDevicePath,
+ IN CHAR16* FileName,
+ OUT EFI_DEVICE_PATH_PROTOCOL **NewDevicePath,
+ OUT BOOLEAN *RequestBootType
+ );
+
+BOOLEAN
+BdsLoadOptionPxeIsSupported (
+ IN EFI_DEVICE_PATH *DevicePath
+ );
+
+EFI_STATUS
+BdsLoadOptionTftpList (
+ IN OUT LIST_ENTRY* BdsLoadOptionList
+ );
+
+EFI_STATUS
+BdsLoadOptionTftpCreateDevicePath (
+ IN CHAR16* FileName,
+ OUT EFI_DEVICE_PATH_PROTOCOL **DevicePathNodes,
+ OUT BOOLEAN *RequestBootType
+ );
+
+EFI_STATUS
+BdsLoadOptionTftpUpdateDevicePath (
+ IN EFI_DEVICE_PATH *OldDevicePath,
+ IN CHAR16* FileName,
+ OUT EFI_DEVICE_PATH_PROTOCOL **NewDevicePath,
+ OUT BOOLEAN *RequestBootType
+ );
+
+BOOLEAN
+BdsLoadOptionTftpIsSupported (
+ IN EFI_DEVICE_PATH *DevicePath
+ );
+
+BDS_LOAD_OPTION_SUPPORT BdsLoadOptionSupportList[] = {
+ {
+ BDS_DEVICE_FILESYSTEM,
+ BdsLoadOptionFileSystemList,
+ BdsLoadOptionFileSystemIsSupported,
+ BdsLoadOptionFileSystemCreateDevicePath,
+ BdsLoadOptionFileSystemUpdateDevicePath
+ },
+ {
+ BDS_DEVICE_MEMMAP,
+ BdsLoadOptionMemMapList,
+ BdsLoadOptionMemMapIsSupported,
+ BdsLoadOptionMemMapCreateDevicePath,
+ BdsLoadOptionMemMapUpdateDevicePath
+ },
+ {
+ BDS_DEVICE_PXE,
+ BdsLoadOptionPxeList,
+ BdsLoadOptionPxeIsSupported,
+ BdsLoadOptionPxeCreateDevicePath,
+ BdsLoadOptionPxeUpdateDevicePath
+ },
+ {
+ BDS_DEVICE_TFTP,
+ BdsLoadOptionTftpList,
+ BdsLoadOptionTftpIsSupported,
+ BdsLoadOptionTftpCreateDevicePath,
+ BdsLoadOptionTftpUpdateDevicePath
+ }
+};
+
+EFI_STATUS
+BootDeviceListSupportedInit (
+ IN OUT LIST_ENTRY *SupportedDeviceList
+ )
+{
+ UINTN Index;
+
+ // Initialize list of supported devices
+ InitializeListHead (SupportedDeviceList);
+
+ for (Index = 0; Index < BDS_DEVICE_MAX; Index++) {
+ BdsLoadOptionSupportList[Index].ListDevices (SupportedDeviceList);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+BootDeviceListSupportedFree (
+ IN LIST_ENTRY *SupportedDeviceList,
+ IN BDS_SUPPORTED_DEVICE *Except
+ )
+{
+ LIST_ENTRY *Entry;
+ BDS_SUPPORTED_DEVICE* SupportedDevice;
+
+ Entry = GetFirstNode (SupportedDeviceList);
+ while (Entry != SupportedDeviceList) {
+ SupportedDevice = SUPPORTED_BOOT_DEVICE_FROM_LINK(Entry);
+ Entry = RemoveEntryList (Entry);
+ if (SupportedDevice != Except) {
+ FreePool (SupportedDevice);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+BootDeviceGetDeviceSupport (
+ IN EFI_DEVICE_PATH *DevicePath,
+ OUT BDS_LOAD_OPTION_SUPPORT **DeviceSupport
+ )
+{
+ UINTN Index;
+
+ // Find which supported device is the most appropriate
+ for (Index = 0; Index < BDS_DEVICE_MAX; Index++) {
+ if (BdsLoadOptionSupportList[Index].IsSupported (DevicePath)) {
+ *DeviceSupport = &BdsLoadOptionSupportList[Index];
+ return EFI_SUCCESS;
+ }
+ }
+
+ return EFI_UNSUPPORTED;
+}
+
+EFI_STATUS
+BootDeviceGetType (
+ IN EFI_DEVICE_PATH* DevicePath,
+ OUT ARM_BDS_LOADER_TYPE *BootType,
+ OUT UINT32 *Attributes
+ )
+{
+ EFI_STATUS Status;
+ BOOLEAN IsEfiApp;
+ BOOLEAN IsBootLoader;
+ BOOLEAN HasFDTSupport;
+ CHAR16* FileName;
+ EFI_DEVICE_PATH* PrevDevicePathNode;
+ EFI_DEVICE_PATH* DevicePathNode;
+ EFI_PHYSICAL_ADDRESS Image;
+ UINTN FileSize;
+ EFI_IMAGE_DOS_HEADER* DosHeader;
+ UINTN PeCoffHeaderOffset;
+ EFI_IMAGE_NT_HEADERS32* NtHeader;
+
+ //
+ // Check if the last node of the device path is a FilePath node
+ //
+ PrevDevicePathNode = NULL;
+ DevicePathNode = DevicePath;
+ while ((DevicePathNode != NULL) && !IsDevicePathEnd (DevicePathNode)) {
+ PrevDevicePathNode = DevicePathNode;
+ DevicePathNode = NextDevicePathNode (DevicePathNode);
+ }
+
+ if ((PrevDevicePathNode != NULL) &&
+ (PrevDevicePathNode->Type == MEDIA_DEVICE_PATH) &&
+ (PrevDevicePathNode->SubType == MEDIA_FILEPATH_DP))
+ {
+ FileName = ((FILEPATH_DEVICE_PATH*)PrevDevicePathNode)->PathName;
+ } else {
+ FileName = NULL;
+ }
+
+ if (FileName == NULL) {
+ Print(L"Is an EFI Application? ");
+ Status = GetHIInputBoolean (&IsEfiApp);
+ if (EFI_ERROR(Status)) {
+ return EFI_ABORTED;
+ }
+ } else if (HasFilePathEfiExtension(FileName)) {
+ IsEfiApp = TRUE;
+ } else {
+ // Check if the file exist
+ Status = BdsLoadImage (DevicePath, AllocateAnyPages, &Image, &FileSize);
+ if (!EFI_ERROR (Status)) {
+
+ DosHeader = (EFI_IMAGE_DOS_HEADER *)(UINTN) Image;
+ if (DosHeader->e_magic == EFI_IMAGE_DOS_SIGNATURE) {
+ //
+ // DOS image header is present,
+ // so read the PE header after the DOS image header.
+ //
+ PeCoffHeaderOffset = DosHeader->e_lfanew;
+ } else {
+ PeCoffHeaderOffset = 0;
+ }
+
+ //
+ // Check PE/COFF image.
+ //
+ NtHeader = (EFI_IMAGE_NT_HEADERS32 *)(UINTN) (Image + PeCoffHeaderOffset);
+ if (NtHeader->Signature != EFI_IMAGE_NT_SIGNATURE) {
+ IsEfiApp = FALSE;
+ } else {
+ IsEfiApp = TRUE;
+ }
+
+ // Free memory
+ gBS->FreePages (Image, EFI_SIZE_TO_PAGES(FileSize));
+ } else {
+ // If we did not manage to open it then ask for the type
+ Print(L"Is an EFI Application? ");
+ Status = GetHIInputBoolean (&IsEfiApp);
+ if (EFI_ERROR(Status)) {
+ return EFI_ABORTED;
+ }
+ }
+ }
+
+ if (IsEfiApp) {
+ Print(L"Is your application is an OS loader? ");
+ Status = GetHIInputBoolean (&IsBootLoader);
+ if (EFI_ERROR(Status)) {
+ return EFI_ABORTED;
+ }
+ if (!IsBootLoader) {
+ *Attributes |= LOAD_OPTION_CATEGORY_APP;
+ }
+ *BootType = BDS_LOADER_EFI_APPLICATION;
+ } else {
+ Print(L"Has FDT support? ");
+ Status = GetHIInputBoolean (&HasFDTSupport);
+ if (EFI_ERROR(Status)) {
+ return EFI_ABORTED;
+ }
+ if (HasFDTSupport) {
+ *BootType = BDS_LOADER_KERNEL_LINUX_FDT;
+ } else {
+ *BootType = BDS_LOADER_KERNEL_LINUX_ATAG;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+BdsLoadOptionFileSystemList (
+ IN OUT LIST_ENTRY* BdsLoadOptionList
+ )
+{
+ EFI_STATUS Status;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ UINTN Index;
+ BDS_SUPPORTED_DEVICE *SupportedDevice;
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL* FileProtocol;
+ EFI_FILE_HANDLE Fs;
+ UINTN Size;
+ EFI_FILE_SYSTEM_INFO* FsInfo;
+ EFI_DEVICE_PATH_PROTOCOL* DevicePathProtocol;
+
+ // List all the Simple File System Protocols
+ Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiSimpleFileSystemProtocolGuid, NULL, &HandleCount, &HandleBuffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID **)&DevicePathProtocol);
+ if (!EFI_ERROR(Status)) {
+ // Allocate BDS Supported Device structure
+ SupportedDevice = (BDS_SUPPORTED_DEVICE*)AllocatePool (sizeof(BDS_SUPPORTED_DEVICE));
+
+ FileProtocol = NULL;
+ Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiSimpleFileSystemProtocolGuid, (VOID **)&FileProtocol);
+ ASSERT_EFI_ERROR(Status);
+
+ FileProtocol->OpenVolume (FileProtocol, &Fs);
+
+ // Generate a Description from the file system
+ Size = 0;
+ FsInfo = NULL;
+ Status = Fs->GetInfo (Fs, &gEfiFileSystemInfoGuid, &Size, FsInfo);
+ if (Status == EFI_BUFFER_TOO_SMALL) {
+ FsInfo = AllocatePool (Size);
+ Status = Fs->GetInfo (Fs, &gEfiFileSystemInfoGuid, &Size, FsInfo);
+ }
+ UnicodeSPrint (SupportedDevice->Description,BOOT_DEVICE_DESCRIPTION_MAX,L"%s (%d MB)",FsInfo->VolumeLabel,(UINT32)(FsInfo->VolumeSize / (1024 * 1024)));
+ FreePool(FsInfo);
+ Fs->Close (Fs);
+
+ SupportedDevice->DevicePathProtocol = DevicePathProtocol;
+ SupportedDevice->Support = &BdsLoadOptionSupportList[BDS_DEVICE_FILESYSTEM];
+
+ InsertTailList (BdsLoadOptionList,&SupportedDevice->Link);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+BdsLoadOptionFileSystemCreateDevicePath (
+ IN CHAR16* FileName,
+ OUT EFI_DEVICE_PATH_PROTOCOL **DevicePathNodes,
+ OUT BOOLEAN *RequestBootType
+ )
+{
+ EFI_STATUS Status;
+ FILEPATH_DEVICE_PATH* FilePathDevicePath;
+ CHAR16 BootFilePath[BOOT_DEVICE_FILEPATH_MAX];
+ UINTN BootFilePathSize;
+
+ Print(L"File path of the %s: ", FileName);
+ Status = GetHIInputStr (BootFilePath, BOOT_DEVICE_FILEPATH_MAX);
+ if (EFI_ERROR(Status)) {
+ return EFI_ABORTED;
+ }
+
+ BootFilePathSize = StrSize (BootFilePath);
+ if (BootFilePathSize == 2) {
+ *DevicePathNodes = NULL;
+ return EFI_NOT_FOUND;
+ }
+
+ // Create the FilePath Device Path node
+ FilePathDevicePath = (FILEPATH_DEVICE_PATH*)AllocatePool(SIZE_OF_FILEPATH_DEVICE_PATH + BootFilePathSize + END_DEVICE_PATH_LENGTH);
+ FilePathDevicePath->Header.Type = MEDIA_DEVICE_PATH;
+ FilePathDevicePath->Header.SubType = MEDIA_FILEPATH_DP;
+ SetDevicePathNodeLength (FilePathDevicePath, SIZE_OF_FILEPATH_DEVICE_PATH + BootFilePathSize);
+ CopyMem (FilePathDevicePath->PathName, BootFilePath, BootFilePathSize);
+ SetDevicePathEndNode ((VOID*)((UINTN)FilePathDevicePath + SIZE_OF_FILEPATH_DEVICE_PATH + BootFilePathSize));
+ *DevicePathNodes = (EFI_DEVICE_PATH_PROTOCOL*)FilePathDevicePath;
+
+ return Status;
+}
+
+EFI_STATUS
+BdsLoadOptionFileSystemUpdateDevicePath (
+ IN EFI_DEVICE_PATH *OldDevicePath,
+ IN CHAR16* FileName,
+ OUT EFI_DEVICE_PATH_PROTOCOL **NewDevicePath,
+ OUT BOOLEAN *RequestBootType
+ )
+{
+ EFI_STATUS Status;
+ CHAR16 BootFilePath[BOOT_DEVICE_FILEPATH_MAX];
+ UINTN BootFilePathSize;
+ FILEPATH_DEVICE_PATH* EndingDevicePath;
+ FILEPATH_DEVICE_PATH* FilePathDevicePath;
+ EFI_DEVICE_PATH* DevicePath;
+
+ DevicePath = DuplicateDevicePath (OldDevicePath);
+
+ EndingDevicePath = (FILEPATH_DEVICE_PATH*)GetLastDevicePathNode (DevicePath);
+
+ Print(L"File path of the %s: ", FileName);
+ StrnCpy (BootFilePath, EndingDevicePath->PathName, BOOT_DEVICE_FILEPATH_MAX);
+ Status = EditHIInputStr (BootFilePath, BOOT_DEVICE_FILEPATH_MAX);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ BootFilePathSize = StrSize(BootFilePath);
+ if (BootFilePathSize == 2) {
+ *NewDevicePath = NULL;
+ return EFI_NOT_FOUND;
+ }
+
+ // Create the FilePath Device Path node
+ FilePathDevicePath = (FILEPATH_DEVICE_PATH*)AllocatePool(SIZE_OF_FILEPATH_DEVICE_PATH + BootFilePathSize);
+ FilePathDevicePath->Header.Type = MEDIA_DEVICE_PATH;
+ FilePathDevicePath->Header.SubType = MEDIA_FILEPATH_DP;
+ SetDevicePathNodeLength (FilePathDevicePath, SIZE_OF_FILEPATH_DEVICE_PATH + BootFilePathSize);
+ CopyMem (FilePathDevicePath->PathName, BootFilePath, BootFilePathSize);
+
+ // Generate the new Device Path by replacing the last node by the updated node
+ SetDevicePathEndNode (EndingDevicePath);
+ *NewDevicePath = AppendDevicePathNode (DevicePath, (CONST EFI_DEVICE_PATH_PROTOCOL *)FilePathDevicePath);
+ FreePool(DevicePath);
+
+ return EFI_SUCCESS;
+}
+
+BOOLEAN
+BdsLoadOptionFileSystemIsSupported (
+ IN EFI_DEVICE_PATH *DevicePath
+ )
+{
+ EFI_DEVICE_PATH* DevicePathNode;
+
+ DevicePathNode = GetLastDevicePathNode (DevicePath);
+
+ return IS_DEVICE_PATH_NODE(DevicePathNode,MEDIA_DEVICE_PATH,MEDIA_FILEPATH_DP);
+}
+
+STATIC
+BOOLEAN
+IsParentDevicePath (
+ IN EFI_DEVICE_PATH_PROTOCOL *ParentDevicePath,
+ IN EFI_DEVICE_PATH_PROTOCOL *ChildDevicePath
+ )
+{
+ UINTN ParentSize;
+ UINTN ChildSize;
+
+ ParentSize = GetDevicePathSize (ParentDevicePath);
+ ChildSize = GetDevicePathSize (ChildDevicePath);
+
+ if (ParentSize > ChildSize) {
+ return FALSE;
+ }
+
+ if (CompareMem (ParentDevicePath, ChildDevicePath, ParentSize - END_DEVICE_PATH_LENGTH) != 0) {
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
+EFI_STATUS
+BdsLoadOptionMemMapList (
+ IN OUT LIST_ENTRY* BdsLoadOptionList
+ )
+{
+ EFI_STATUS Status;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ UINTN DevicePathHandleCount;
+ EFI_HANDLE *DevicePathHandleBuffer;
+ BOOLEAN IsParent;
+ UINTN Index;
+ UINTN Index2;
+ BDS_SUPPORTED_DEVICE *SupportedDevice;
+ EFI_DEVICE_PATH_PROTOCOL* DevicePathProtocol;
+ EFI_DEVICE_PATH* DevicePath;
+
+ // List all the BlockIo Protocols
+ Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiBlockIoProtocolGuid, NULL, &HandleCount, &HandleBuffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ for (Index = 0; Index < HandleCount; Index++) {
+ // We only select the handle WITH a Device Path AND not part of Media (to avoid duplication with HardDisk, CDROM, etc)
+ Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID **)&DevicePathProtocol);
+ if (!EFI_ERROR(Status)) {
+ // BlockIo is not part of Media Device Path
+ DevicePath = DevicePathProtocol;
+ while (!IsDevicePathEndType (DevicePath) && (DevicePathType (DevicePath) != MEDIA_DEVICE_PATH)) {
+ DevicePath = NextDevicePathNode (DevicePath);
+ }
+ if (DevicePathType (DevicePath) == MEDIA_DEVICE_PATH) {
+ continue;
+ }
+
+ // Open all the handle supporting the DevicePath protocol and verify this handle has not got any child
+ Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiDevicePathProtocolGuid, NULL, &DevicePathHandleCount, &DevicePathHandleBuffer);
+ ASSERT_EFI_ERROR (Status);
+ IsParent = FALSE;
+ for (Index2 = 0; (Index2 < DevicePathHandleCount) && !IsParent; Index2++) {
+ if (HandleBuffer[Index] != DevicePathHandleBuffer[Index2]) {
+ gBS->HandleProtocol (DevicePathHandleBuffer[Index2], &gEfiDevicePathProtocolGuid, (VOID **)&DevicePath);
+ if (IsParentDevicePath (DevicePathProtocol, DevicePath)) {
+ IsParent = TRUE;
+ }
+ }
+ }
+ if (IsParent) {
+ continue;
+ }
+
+ // Allocate BDS Supported Device structure
+ SupportedDevice = (BDS_SUPPORTED_DEVICE*)AllocatePool(sizeof(BDS_SUPPORTED_DEVICE));
+
+ Status = GenerateDeviceDescriptionName (HandleBuffer[Index], SupportedDevice->Description);
+ ASSERT_EFI_ERROR (Status);
+
+ SupportedDevice->DevicePathProtocol = DevicePathProtocol;
+ SupportedDevice->Support = &BdsLoadOptionSupportList[BDS_DEVICE_MEMMAP];
+
+ InsertTailList (BdsLoadOptionList,&SupportedDevice->Link);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+BdsLoadOptionMemMapCreateDevicePath (
+ IN CHAR16* FileName,
+ OUT EFI_DEVICE_PATH_PROTOCOL **DevicePathNodes,
+ OUT BOOLEAN *RequestBootType
+ )
+{
+ EFI_STATUS Status;
+ MEMMAP_DEVICE_PATH *MemMapDevicePath;
+ CHAR16 StrStartingAddress[BOOT_DEVICE_ADDRESS_MAX];
+ CHAR16 StrEndingAddress[BOOT_DEVICE_ADDRESS_MAX];
+
+ Print(L"Starting Address of the %s: ", FileName);
+ Status = GetHIInputStr (StrStartingAddress, BOOT_DEVICE_ADDRESS_MAX);
+ if (EFI_ERROR(Status)) {
+ return EFI_ABORTED;
+ }
+
+ Print(L"Ending Address of the %s: ", FileName);
+ Status = GetHIInputStr (StrEndingAddress, BOOT_DEVICE_ADDRESS_MAX);
+ if (EFI_ERROR(Status)) {
+ return EFI_ABORTED;
+ }
+
+ // Create the MemMap Device Path Node
+ MemMapDevicePath = (MEMMAP_DEVICE_PATH*)AllocatePool (sizeof(MEMMAP_DEVICE_PATH) + END_DEVICE_PATH_LENGTH);
+ MemMapDevicePath->Header.Type = HARDWARE_DEVICE_PATH;
+ MemMapDevicePath->Header.SubType = HW_MEMMAP_DP;
+ SetDevicePathNodeLength (MemMapDevicePath, sizeof(MEMMAP_DEVICE_PATH));
+ MemMapDevicePath->MemoryType = EfiBootServicesData;
+ MemMapDevicePath->StartingAddress = StrHexToUint64 (StrStartingAddress);
+ MemMapDevicePath->EndingAddress = StrHexToUint64 (StrEndingAddress);
+
+ // Set a Device Path End Node after the Memory Map Device Path Node
+ SetDevicePathEndNode (MemMapDevicePath + 1);
+ *DevicePathNodes = (EFI_DEVICE_PATH_PROTOCOL*)MemMapDevicePath;
+
+ return Status;
+}
+
+EFI_STATUS
+BdsLoadOptionMemMapUpdateDevicePath (
+ IN EFI_DEVICE_PATH *OldDevicePath,
+ IN CHAR16* FileName,
+ OUT EFI_DEVICE_PATH_PROTOCOL **NewDevicePath,
+ OUT BOOLEAN *RequestBootType
+ )
+{
+ EFI_STATUS Status;
+ CHAR16 StrStartingAddress[BOOT_DEVICE_ADDRESS_MAX];
+ CHAR16 StrEndingAddress[BOOT_DEVICE_ADDRESS_MAX];
+ MEMMAP_DEVICE_PATH* EndingDevicePath;
+ EFI_DEVICE_PATH* DevicePath;
+
+ DevicePath = DuplicateDevicePath (OldDevicePath);
+ EndingDevicePath = (MEMMAP_DEVICE_PATH*)GetLastDevicePathNode (DevicePath);
+
+ Print(L"Starting Address of the %s: ", FileName);
+ UnicodeSPrint (StrStartingAddress, BOOT_DEVICE_ADDRESS_MAX, L"0x%X", (UINTN)EndingDevicePath->StartingAddress);
+ Status = EditHIInputStr (StrStartingAddress, BOOT_DEVICE_ADDRESS_MAX);
+ if (EFI_ERROR(Status)) {
+ return EFI_ABORTED;
+ }
+
+ Print(L"Ending Address of the %s: ", FileName);
+ UnicodeSPrint (StrEndingAddress, BOOT_DEVICE_ADDRESS_MAX, L"0x%X", (UINTN)EndingDevicePath->EndingAddress);
+ Status = EditHIInputStr (StrEndingAddress, BOOT_DEVICE_ADDRESS_MAX);
+ if (EFI_ERROR(Status)) {
+ return EFI_ABORTED;
+ }
+
+ EndingDevicePath->StartingAddress = StrHexToUint64 (StrStartingAddress);
+ EndingDevicePath->EndingAddress = StrHexToUint64 (StrEndingAddress);
+
+ if (EFI_ERROR(Status)) {
+ FreePool(DevicePath);
+ } else {
+ *NewDevicePath = DevicePath;
+ }
+
+ return Status;
+}
+
+BOOLEAN
+BdsLoadOptionMemMapIsSupported (
+ IN EFI_DEVICE_PATH *DevicePath
+ )
+{
+ EFI_DEVICE_PATH* DevicePathNode;
+
+ DevicePathNode = GetLastDevicePathNode (DevicePath);
+
+ return IS_DEVICE_PATH_NODE(DevicePathNode,HARDWARE_DEVICE_PATH,HW_MEMMAP_DP);
+}
+
+EFI_STATUS
+BdsLoadOptionPxeList (
+ IN OUT LIST_ENTRY* BdsLoadOptionList
+ )
+{
+ EFI_STATUS Status;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ UINTN Index;
+ BDS_SUPPORTED_DEVICE *SupportedDevice;
+ EFI_DEVICE_PATH_PROTOCOL* DevicePathProtocol;
+ EFI_SIMPLE_NETWORK_PROTOCOL* SimpleNet;
+ CHAR16 DeviceDescription[BOOT_DEVICE_DESCRIPTION_MAX];
+ EFI_MAC_ADDRESS *Mac;
+
+ // List all the PXE Protocols
+ Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiPxeBaseCodeProtocolGuid, NULL, &HandleCount, &HandleBuffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ for (Index = 0; Index < HandleCount; Index++) {
+ // We only select the handle WITH a Device Path AND the PXE Protocol
+ Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID **)&DevicePathProtocol);
+ if (!EFI_ERROR(Status)) {
+ // Allocate BDS Supported Device structure
+ SupportedDevice = (BDS_SUPPORTED_DEVICE*)AllocatePool(sizeof(BDS_SUPPORTED_DEVICE));
+
+ Status = gBS->LocateProtocol (&gEfiSimpleNetworkProtocolGuid, NULL, (VOID **)&SimpleNet);
+ if (!EFI_ERROR(Status)) {
+ Mac = &SimpleNet->Mode->CurrentAddress;
+ UnicodeSPrint (DeviceDescription,BOOT_DEVICE_DESCRIPTION_MAX,L"MAC Address: %02x:%02x:%02x:%02x:%02x:%02x", Mac->Addr[0], Mac->Addr[1], Mac->Addr[2], Mac->Addr[3], Mac->Addr[4], Mac->Addr[5]);
+ } else {
+ Status = GenerateDeviceDescriptionName (HandleBuffer[Index], DeviceDescription);
+ ASSERT_EFI_ERROR (Status);
+ }
+ UnicodeSPrint (SupportedDevice->Description,BOOT_DEVICE_DESCRIPTION_MAX,L"PXE on %s",DeviceDescription);
+
+ SupportedDevice->DevicePathProtocol = DevicePathProtocol;
+ SupportedDevice->Support = &BdsLoadOptionSupportList[BDS_DEVICE_PXE];
+
+ InsertTailList (BdsLoadOptionList,&SupportedDevice->Link);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+BdsLoadOptionPxeCreateDevicePath (
+ IN CHAR16* FileName,
+ OUT EFI_DEVICE_PATH_PROTOCOL **DevicePathNodes,
+ OUT BOOLEAN *RequestBootType
+ )
+{
+ *DevicePathNodes = (EFI_DEVICE_PATH_PROTOCOL *) AllocatePool (END_DEVICE_PATH_LENGTH);
+ SetDevicePathEndNode (*DevicePathNodes);
+
+ if (RequestBootType) {
+ *RequestBootType = FALSE;
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+BdsLoadOptionPxeUpdateDevicePath (
+ IN EFI_DEVICE_PATH *OldDevicePath,
+ IN CHAR16* FileName,
+ OUT EFI_DEVICE_PATH_PROTOCOL **NewDevicePath,
+ OUT BOOLEAN *RequestBootType
+ )
+{
+ ASSERT (0);
+ return EFI_UNSUPPORTED;
+}
+
+BOOLEAN
+BdsLoadOptionPxeIsSupported (
+ IN EFI_DEVICE_PATH *DevicePath
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath;
+ EFI_PXE_BASE_CODE_PROTOCOL *PxeBcProtocol;
+
+ Status = BdsConnectDevicePath (DevicePath, &Handle, &RemainingDevicePath);
+ if (EFI_ERROR(Status)) {
+ return FALSE;
+ }
+
+ if (!IsDevicePathEnd(RemainingDevicePath)) {
+ return FALSE;
+ }
+
+ Status = gBS->HandleProtocol (Handle, &gEfiPxeBaseCodeProtocolGuid, (VOID **)&PxeBcProtocol);
+ if (EFI_ERROR (Status)) {
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+}
+
+EFI_STATUS
+BdsLoadOptionTftpList (
+ IN OUT LIST_ENTRY* BdsLoadOptionList
+ )
+{
+ EFI_STATUS Status;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ UINTN Index;
+ BDS_SUPPORTED_DEVICE *SupportedDevice;
+ EFI_DEVICE_PATH_PROTOCOL* DevicePathProtocol;
+ EFI_SIMPLE_NETWORK_PROTOCOL* SimpleNet;
+ CHAR16 DeviceDescription[BOOT_DEVICE_DESCRIPTION_MAX];
+ EFI_MAC_ADDRESS *Mac;
+
+ // List all the PXE Protocols
+ Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiPxeBaseCodeProtocolGuid, NULL, &HandleCount, &HandleBuffer);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ for (Index = 0; Index < HandleCount; Index++) {
+ // We only select the handle WITH a Device Path AND the PXE Protocol AND the TFTP Protocol (the TFTP protocol is required to start PXE)
+ Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID **)&DevicePathProtocol);
+ if (!EFI_ERROR(Status)) {
+ // Allocate BDS Supported Device structure
+ SupportedDevice = (BDS_SUPPORTED_DEVICE*)AllocatePool(sizeof(BDS_SUPPORTED_DEVICE));
+
+ Status = gBS->LocateProtocol (&gEfiSimpleNetworkProtocolGuid, NULL, (VOID **)&SimpleNet);
+ if (!EFI_ERROR(Status)) {
+ Mac = &SimpleNet->Mode->CurrentAddress;
+ UnicodeSPrint (DeviceDescription,BOOT_DEVICE_DESCRIPTION_MAX,L"MAC Address: %02x:%02x:%02x:%02x:%02x:%02x", Mac->Addr[0], Mac->Addr[1], Mac->Addr[2], Mac->Addr[3], Mac->Addr[4], Mac->Addr[5]);
+ } else {
+ Status = GenerateDeviceDescriptionName (HandleBuffer[Index], DeviceDescription);
+ ASSERT_EFI_ERROR (Status);
+ }
+ UnicodeSPrint (SupportedDevice->Description,BOOT_DEVICE_DESCRIPTION_MAX,L"TFTP on %s",DeviceDescription);
+
+ SupportedDevice->DevicePathProtocol = DevicePathProtocol;
+ SupportedDevice->Support = &BdsLoadOptionSupportList[BDS_DEVICE_TFTP];
+
+ InsertTailList (BdsLoadOptionList,&SupportedDevice->Link);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+BdsLoadOptionTftpCreateDevicePath (
+ IN CHAR16* FileName,
+ OUT EFI_DEVICE_PATH_PROTOCOL **DevicePathNodes,
+ OUT BOOLEAN *RequestBootType
+ )
+{
+ EFI_STATUS Status;
+ BOOLEAN IsDHCP;
+ EFI_IP_ADDRESS LocalIp;
+ EFI_IP_ADDRESS RemoteIp;
+ IPv4_DEVICE_PATH* IPv4DevicePathNode;
+ FILEPATH_DEVICE_PATH* FilePathDevicePath;
+ CHAR16 BootFilePath[BOOT_DEVICE_FILEPATH_MAX];
+ UINTN BootFilePathSize;
+
+ Print(L"Get the IP address from DHCP: ");
+ Status = GetHIInputBoolean (&IsDHCP);
+ if (EFI_ERROR(Status)) {
+ return EFI_ABORTED;
+ }
+
+ if (!IsDHCP) {
+ Print(L"Get the static IP address: ");
+ Status = GetHIInputIP (&LocalIp);
+ if (EFI_ERROR(Status)) {
+ return EFI_ABORTED;
+ }
+ }
+
+ Print(L"Get the TFTP server IP address: ");
+ Status = GetHIInputIP (&RemoteIp);
+ if (EFI_ERROR(Status)) {
+ return EFI_ABORTED;
+ }
+
+ Print(L"File path of the %s : ", FileName);
+ Status = GetHIInputStr (BootFilePath, BOOT_DEVICE_FILEPATH_MAX);
+ if (EFI_ERROR(Status)) {
+ return EFI_ABORTED;
+ }
+
+ BootFilePathSize = StrSize(BootFilePath);
+ if (BootFilePathSize == 2) {
+ return EFI_NOT_FOUND;
+ }
+
+ // Allocate the memory for the IPv4 + File Path Device Path Nodes
+ IPv4DevicePathNode = (IPv4_DEVICE_PATH*)AllocatePool(sizeof(IPv4_DEVICE_PATH) + SIZE_OF_FILEPATH_DEVICE_PATH + BootFilePathSize + END_DEVICE_PATH_LENGTH);
+
+ // Create the IPv4 Device Path
+ IPv4DevicePathNode->Header.Type = MESSAGING_DEVICE_PATH;
+ IPv4DevicePathNode->Header.SubType = MSG_IPv4_DP;
+ SetDevicePathNodeLength (&IPv4DevicePathNode->Header, sizeof(IPv4_DEVICE_PATH));
+ CopyMem (&IPv4DevicePathNode->LocalIpAddress, &LocalIp.v4, sizeof (EFI_IPv4_ADDRESS));
+ CopyMem (&IPv4DevicePathNode->RemoteIpAddress, &RemoteIp.v4, sizeof (EFI_IPv4_ADDRESS));
+ IPv4DevicePathNode->LocalPort = 0;
+ IPv4DevicePathNode->RemotePort = 0;
+ IPv4DevicePathNode->Protocol = EFI_IP_PROTO_TCP;
+ IPv4DevicePathNode->StaticIpAddress = (IsDHCP != TRUE);
+
+ // Create the FilePath Device Path node
+ FilePathDevicePath = (FILEPATH_DEVICE_PATH*)(IPv4DevicePathNode + 1);
+ FilePathDevicePath->Header.Type = MEDIA_DEVICE_PATH;
+ FilePathDevicePath->Header.SubType = MEDIA_FILEPATH_DP;
+ SetDevicePathNodeLength (FilePathDevicePath, SIZE_OF_FILEPATH_DEVICE_PATH + BootFilePathSize);
+ CopyMem (FilePathDevicePath->PathName, BootFilePath, BootFilePathSize);
+
+ // Set the End Device Path Node
+ SetDevicePathEndNode ((VOID*)((UINTN)FilePathDevicePath + SIZE_OF_FILEPATH_DEVICE_PATH + BootFilePathSize));
+ *DevicePathNodes = (EFI_DEVICE_PATH_PROTOCOL*)IPv4DevicePathNode;
+
+ return Status;
+}
+
+EFI_STATUS
+BdsLoadOptionTftpUpdateDevicePath (
+ IN EFI_DEVICE_PATH *OldDevicePath,
+ IN CHAR16* FileName,
+ OUT EFI_DEVICE_PATH_PROTOCOL **NewDevicePath,
+ OUT BOOLEAN *RequestBootType
+ )
+{
+ ASSERT (0);
+ return EFI_UNSUPPORTED;
+}
+
+BOOLEAN
+BdsLoadOptionTftpIsSupported (
+ IN EFI_DEVICE_PATH *DevicePath
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ EFI_DEVICE_PATH *RemainingDevicePath;
+ EFI_DEVICE_PATH *NextDevicePath;
+ EFI_PXE_BASE_CODE_PROTOCOL *PxeBcProtocol;
+
+ Status = BdsConnectDevicePath (DevicePath, &Handle, &RemainingDevicePath);
+ if (EFI_ERROR(Status)) {
+ return FALSE;
+ }
+
+ // Validate the Remaining Device Path
+ if (IsDevicePathEnd(RemainingDevicePath)) {
+ return FALSE;
+ }
+ if (!IS_DEVICE_PATH_NODE(RemainingDevicePath,MESSAGING_DEVICE_PATH,MSG_IPv4_DP) &&
+ !IS_DEVICE_PATH_NODE(RemainingDevicePath,MESSAGING_DEVICE_PATH,MSG_IPv6_DP)) {
+ return FALSE;
+ }
+ NextDevicePath = NextDevicePathNode (RemainingDevicePath);
+ if (IsDevicePathEnd(NextDevicePath)) {
+ return FALSE;
+ }
+ if (!IS_DEVICE_PATH_NODE(NextDevicePath,MEDIA_DEVICE_PATH,MEDIA_FILEPATH_DP)) {
+ return FALSE;
+ }
+
+ Status = gBS->HandleProtocol (Handle, &gEfiPxeBaseCodeProtocolGuid, (VOID **)&PxeBcProtocol);
+ if (EFI_ERROR (Status)) {
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+}
diff --git a/HisiPkg/D01BoardPkg/D01BoardPkg.dsc b/HisiPkg/D01BoardPkg/D01BoardPkg.dsc new file mode 100644 index 000000000..fcf09d0a6 --- /dev/null +++ b/HisiPkg/D01BoardPkg/D01BoardPkg.dsc @@ -0,0 +1,333 @@ +#
+# Copyright (c) 2011-2012, Hisilicon Limited. All rights reserved.
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = D01-A15_MPCore
+ PLATFORM_GUID = 3a91a0f8-3af4-409d-a71d-a199dc134357
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/D01
+ SUPPORTED_ARCHITECTURES = ARM
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = HisiPkg/D01BoardPkg/D01BoardPkg.fdf
+
+!include HisiPkg/D01BoardPkg/D01BoardPkg.dsc.inc
+
+[LibraryClasses.common]
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
+ ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf
+ ArmPlatformLib|HisiPkg/D01BoardPkg/Library/D01LibRTSM/D01Lib.inf
+
+ ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
+ NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
+
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+
+
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+[LibraryClasses.common.SEC]
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
+ ArmPlatformSecLib|HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/D01SecLib.inf
+ ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf
+
+[BuildOptions]
+
+ RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 --fpu=softvfp -I$(WORKSPACE)/HisiPkg/Include/Platform
+
+ GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -I$(WORKSPACE)/HisiPkg/Include/Platform
+
+ XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 -I$(WORKSPACE)/HisiPkg/Include/Platform
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+!ifdef $(EDK2_SKIP_PEICORE)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
+ gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
+!endif
+
+ ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+ # It could be set FALSE to save size.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|FALSE
+
+[PcdsFixedAtBuild.common]
+
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM D01"
+
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D01"
+
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|2
+
+ #
+ # NV Storage PCDs. Use base of 0x0C000000 for NOR1
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0xf10C0000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0xf10D0000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0xf10E0000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000
+
+ gArmTokenSpaceGuid.PcdVFPEnabled|0
+
+ # Stacks for MPCores in Secure World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x40000000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x8000
+
+ # Stacks for MPCores in Monitor Mode
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x40028000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x8000
+
+ gHwTokenSpaceGuid.PcdEmbeddedBiosVersion|"Linaro_BIOS_V1.9"
+
+
+ # System Memory (1GB)
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x10000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x60000000
+
+ # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x60000000
+
+ #
+ # ARM Pcds
+ #
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
+ #
+ # ARM PrimeCell
+ #
+
+
+ ## PL011 - Serial Terminal
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xe4007000
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000
+
+
+ #
+ # ARM PL390 General Interrupt Controller
+ #
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0xe0C01000
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xe0C02000
+
+ #
+ # ARM OS Loader
+ #
+ # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
+ gArmTokenSpaceGuid.PcdArmMachineType|0xffffffff
+ #gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"SemiHosting"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Ramdisk"
+ #gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/zImage"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenMsg(06ED4DD0-FF78-11D3-BDC4-00A0C94053D1,0000000000000000)/uImage"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenMsg(06ED4DD0-FF78-11D3-BDC4-00A0C94053D1,0000000000000000)/initrd"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"mem=256M console=ttyAMA0,115200"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|1
+
+ # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+ #gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
+ #gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+ #gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|10
+
+ #
+ # ARM L2x0 PCDs
+ #
+ gArmTokenSpaceGuid.PcdL2x0ControllerBase|0xeE00A000
+
+ #
+ # ARM Architectual Timer Frequency
+ #
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|168750000
+
+ gHwTokenSpaceGuid.PcdNorFlashBase|0xf0000000
+
+ gHwTokenSpaceGuid.PcdGPIO0Base|0xe4000000
+ gArmTokenSpaceGuid.PcdSysCtrlBase|0xe3e00000
+ gArmTokenSpaceGuid.PcdTimerBase|0xe3000000
+ gArmTokenSpaceGuid.PcdTimer0InterruptNum|130
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"EVB_SECURE_UEFI_BIOS"
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+ #
+ # SEC
+ #
+ HisiPkg/D01BoardPkg/Sec/Sec/Sec.inf {
+ <LibraryClasses>
+ # Use the implementation which set the Secure bits
+ #ArmGicLib|HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicSecLib.inf
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+ }
+
+ #
+ # PEI Phase modules
+ #
+!ifndef $(EDK2_SKIP_PEICORE)
+ ArmPlatformPkg/PrePi/PeiMPCore.inf{
+ <LibraryClasses>
+ ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
+ ArmPlatformLib|HisiPkg/D01BoardPkg/Library/D01LibRTSM/D01Lib.inf
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf
+ }
+!else
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {
+ <LibraryClasses>
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf
+ }
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ #ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ Nt32Pkg/BootModePei/BootModePei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+!endif
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ #MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ EmbeddedPkg/SerialDxe/SerialDxe.inf
+
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicDxe.inf
+ #ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+
+ #ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
+ #ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ HisiPkg/Drivers/TimerDxe/TimerDxe.inf
+ #ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
+ #ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ #HisiPkg/Drivers/WatchDogDriver/WatchDogDriver.inf
+ #
+
+ #
+ # Semi-hosting filesystem
+ #
+ #ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ # RamDisk filesystem
+ #
+ HisiPkg/Drivers/ramdisk/ramdisk.inf
+
+ #HisiPkg/Drivers/FlashDriver/FlashDriver.inf
+
+ #HisiPkg/Drivers/NandFlash/NandFlashDxe.inf
+
+ #
+ # Multimedia Card Interface
+ #
+ #EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+ #ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ #FatPkg/EnhancedFatDxe/Fat.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # network
+ #
+ #HisiPkg/D01BoardPkg/Drivers/SnpPV600Dxe/SnpPV600Dxe.inf
+ MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+
+ #
+ # Application
+ #
+ #EmbeddedPkg/Ebl/Ebl.inf
+ #HisiPkg/D01BoardPkg/Application/Ebl/Ebl.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ HisiPkg/D01BoardPkg/Bds/Bds.inf
+
+ HisiPkg/Drivers/LinuxAtagList/LinuxAtagList.inf
+
+ #HisiPkg/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
diff --git a/HisiPkg/D01BoardPkg/D01BoardPkg.dsc.inc b/HisiPkg/D01BoardPkg/D01BoardPkg.dsc.inc new file mode 100644 index 000000000..3a23a44c4 --- /dev/null +++ b/HisiPkg/D01BoardPkg/D01BoardPkg.dsc.inc @@ -0,0 +1,350 @@ +#
+# Copyright (c) 2011-2012, Hisilicon Limited. All rights reserved.
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+[LibraryClasses.common]
+!if $(TARGET) == RELEASE
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+ UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+
+ #
+ # Assume everything is fixed at build
+ #
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+ # 1/123 faster than Stm or Vstm version
+ BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf
+
+ # ARM Architectural Libraries
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+ CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+
+ #ArmGicLib|HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicLib.inf
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+
+ ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+
+ # Versatile Express Specific Libraries
+ EfiResetSystemLib|ArmPlatformPkg/ArmVExpressPkg/Library/ResetSystemLib/ResetSystemLib.inf
+ # ARM PL031 RTC Driver
+ #RealTimeClockLib|ArmPlatformPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+ RealTimeClockLib|HisiPkg/D01BoardPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf
+ # ARM PL354 SMC Driver
+ PL35xSmcLib|ArmPlatformPkg/Drivers/PL35xSmc/PL35xSmc.inf
+ # ARM PL011 UART Driver
+
+
+ SerialPortLib|HisiPkg/Library/SerialPortLib/SerialPortLib.inf
+ SerialPortExtLib|HisiPkg/Library/SerialPortLib/SerialPortLib.inf
+
+ SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+ #SerialPortLib|ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf
+ #SerialPortExtLib|EmbeddedPkg/Library/TemplateSerialPortExtLib/TemplateSerialPortExtLib.inf
+
+ #PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
+ #SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+ #SerialPortExtLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortExtLib.inf
+ ResetWdtLib|HisiPkg/D01BoardPkg/Library/ResetWdtLib/ResetWdtLib.inf
+ BspUartLib|HisiPkg/Library/BspUartLib/BspUartLib.inf
+ PinIoLib|HisiPkg/Library/PinIoLib/PinIoLib.inf
+
+ # ARM SP804 Dual Timer Driver
+ TimerLib|ArmPlatformPkg/Library/SP804TimerLib/SP804TimerLib.inf
+
+ UefiDevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+
+ # EBL Related Libraries
+ EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf
+ EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf
+ EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf
+ EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf
+
+ PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+
+ # BDS Libraries
+ BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+
+[LibraryClasses.common.SEC]
+ ArmPlatformSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Sec/SecArmPlatformGlobalVariableLib.inf
+
+ DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
+
+#!ifdef $(EDK2_SKIP_PEICORE)
+ PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+ ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+ LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+ HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+ PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+ MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+#!endif
+
+ # Trustzone Support
+ ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf
+
+[LibraryClasses.common.PEI_CORE]
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf
+ PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.PEIM]
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Pei/PeiArmPlatformGlobalVariableLib.inf
+ PeiServicesTablePointerLib|ArmPlatformPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Dxe/DxeArmPlatformGlobalVariableLib.inf
+
+ GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+
+[LibraryClasses.ARM]
+ #
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+ # This library provides the instrinsic functions generate by a given compiler.
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+ #
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+[BuildOptions]
+ RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+
+ XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+ #
+ # Control what commands are supported from the UI
+ # Turn these on and off to add features or save size
+ #
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
+
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+[PcdsFixedAtBuild.common]
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM D01"
+
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D01"
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+ # DEBUG_ASSERT_ENABLED 0x01
+ # DEBUG_PRINT_ENABLED 0x02
+ # DEBUG_CODE_ENABLED 0x04
+ # CLEAR_MEMORY_ENABLED 0x08
+ # ASSERT_BREAKPOINT_ENABLED 0x10
+ # ASSERT_DEADLOOP_ENABLED 0x20
+!if $(TARGET) == RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+!endif
+
+ # DEBUG_INIT 0x00000001 // Initialization
+ # DEBUG_WARN 0x00000002 // Warnings
+ # DEBUG_LOAD 0x00000004 // Load events
+ # DEBUG_FS 0x00000008 // EFI File system
+ # DEBUG_POOL 0x00000010 // Alloc & Free's
+ # DEBUG_PAGE 0x00000020 // Alloc & Free's
+ # DEBUG_INFO 0x00000040 // Verbose
+ # DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers
+ # DEBUG_VARIABLE 0x00000100 // Variable
+ # DEBUG_BM 0x00000400 // Boot Manager
+ # DEBUG_BLKIO 0x00001000 // BlkIo Driver
+ # DEBUG_NET 0x00004000 // SNI Driver
+ # DEBUG_UNDI 0x00010000 // UNDI Driver
+ # DEBUG_LOADFILE 0x00020000 // UNDI Driver
+ # DEBUG_EVENT 0x00080000 // Event messages
+ # DEBUG_ERROR 0x80000000 // Error
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
+
+ #
+ # Optional feature to help prevent EFI memory map fragments
+ # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+ # Values are in EFI Pages (4K). DXE Core will make sure that
+ # at least this much of each type of memory can be allocated
+ # from a single memory range. This way you only end up with
+ # maximum of two fragements for each type in the memory map
+ # (the memory used, and the free memory that was prereserved
+ # but not used).
+ #
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|50
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|20
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+ #
+ # ARM Pcds
+ #
+ gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000000000000
+
+ #
+ # ARM PrimeCell
+ #
+
+ #
+ # ARM OS Loader
+ #
+ # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
+ gArmTokenSpaceGuid.PcdArmMachineType|2272
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from NorFlash"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/MemoryMapped(0x0,0xED000000,0xED400000)"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|1
+
+ # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+ gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|10
+
diff --git a/HisiPkg/D01BoardPkg/D01BoardPkg.fdf b/HisiPkg/D01BoardPkg/D01BoardPkg.fdf new file mode 100644 index 000000000..f191849e7 --- /dev/null +++ b/HisiPkg/D01BoardPkg/D01BoardPkg.fdf @@ -0,0 +1,369 @@ +# FLASH layout file for ARM VE.
+#
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+
+[FD.D01]
+BaseAddress = 0xf0100000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00100000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0x100
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00020000
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
+FV = FVMAIN_SEC
+
+0x00020000|0x000e0000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FVMAIN_SEC]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF HisiPkg/D01BoardPkg/Sec/Sec/Sec.inf
+
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 8 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ #INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+ #INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ #INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ #INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ INF EmbeddedPkg/SerialDxe/SerialDxe.inf
+
+ INF HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicDxe.inf
+ #INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF HisiPkg/Drivers/TimerDxe/TimerDxe.inf
+
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ INF HisiPkg/Drivers/WatchDogDriver/WatchDogDriver.inf
+
+ INF HisiPkg/Drivers/LinuxAtagList/LinuxAtagList.inf
+
+ #
+ # Semi-hosting filesystem
+ #
+ #INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
+
+ # RamDisk filesystem
+ INF HisiPkg/Drivers/ramdisk/ramdisk.inf
+
+ #NorFlash Driver
+ INF HisiPkg/Drivers/FlashDriver/FlashDriver.inf
+
+
+ INF HisiPkg/Drivers/NandFlash/NandFlashDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ #INF FatPkg/EnhancedFatDxe/Fat.inf
+ INF RuleOverride = BINARY FatBinPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+
+ INF HisiPkg/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+ #
+ # Multimedia Card Interface
+ #
+ #INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
+ #INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
+
+ #
+ # network
+ #
+ INF HisiPkg/D01BoardPkg/Drivers/SnpPV600Dxe/SnpPV600Dxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4ConfigDxe/Ip4ConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF HisiPkg/D01BoardPkg/Application/Ebl/Ebl.inf
+ INF ShellBinPkg/UefiShell/UefiShell.inf
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF HisiPkg/D01BoardPkg/Bds/Bds.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+#!if $(EDK2_SKIP_PEICORE) == 1
+ INF ArmPlatformPkg/PrePi/PeiMPCore.inf
+#!else
+# INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+# INF MdeModulePkg/Core/Pei/PeiMain.inf
+# INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+# INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+# INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+# INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+# INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+# INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+# INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+#!endif
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.SEC.BINARY]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
+ TE TE Align = 32 |.efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) {
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+[Rule.Common.DXE_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+}
+
+[Rule.Common.USER_DEFINED]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI Optional |.acpi
+ RAW ASL Optional |.aml
+ }
diff --git a/HisiPkg/D01BoardPkg/Drivers/SnpPV600Dxe/SnpPV600Dxe.efi b/HisiPkg/D01BoardPkg/Drivers/SnpPV600Dxe/SnpPV600Dxe.efi Binary files differnew file mode 100644 index 000000000..69b7ef7c2 --- /dev/null +++ b/HisiPkg/D01BoardPkg/Drivers/SnpPV600Dxe/SnpPV600Dxe.efi diff --git a/HisiPkg/D01BoardPkg/Drivers/SnpPV600Dxe/SnpPV600Dxe.inf b/HisiPkg/D01BoardPkg/Drivers/SnpPV600Dxe/SnpPV600Dxe.inf new file mode 100644 index 000000000..aa2b6004e --- /dev/null +++ b/HisiPkg/D01BoardPkg/Drivers/SnpPV600Dxe/SnpPV600Dxe.inf @@ -0,0 +1,32 @@ +## @file
+# Component name for module SnpPV600Dxe
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SnpPV600Dxe
+ FILE_GUID = 3247F15F-3612-4803-BD4E-4104D7EF944A
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeSnpPV600Driver
+ UNLOAD_IMAGE = SnpPV600Unload
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+[Binaries.common]
+ PE32|SnpPV600Dxe.efi|*
+
diff --git a/HisiPkg/D01BoardPkg/Library/D01LibRTSM/D01Lib.inf b/HisiPkg/D01BoardPkg/Library/D01LibRTSM/D01Lib.inf new file mode 100644 index 000000000..52b26cf08 --- /dev/null +++ b/HisiPkg/D01BoardPkg/Library/D01LibRTSM/D01Lib.inf @@ -0,0 +1,53 @@ +#/* @file
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = RTSMArmD01Lib
+ FILE_GUID = b98a6cb7-d472-4128-ad62-a7347f85ce13
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+ IoLib
+ ArmLib
+ MemoryAllocationLib
+ SerialPortLib
+
+[Sources.common]
+ RTSM.c
+ RTSMMem.c
+ RTSMHelper.asm | RVCT
+ RTSMHelper.S | GCC
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable
+ gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+ gArmPlatformTokenSpaceGuid.PcdStandalone
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
diff --git a/HisiPkg/D01BoardPkg/Library/D01LibRTSM/D01LibSec.inf b/HisiPkg/D01BoardPkg/Library/D01LibRTSM/D01LibSec.inf new file mode 100644 index 000000000..68cdbc933 --- /dev/null +++ b/HisiPkg/D01BoardPkg/Library/D01LibRTSM/D01LibSec.inf @@ -0,0 +1,51 @@ +#/* @file
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = RTSMArmD01LibSec
+ FILE_GUID = a79eed97-4b98-4974-9690-37b32d6a5b56
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+ IoLib
+ ArmLib
+ SerialPortLib
+
+[Sources.common]
+ RTSM.c
+ RTSMHelper.asm | RVCT
+ RTSMHelper.S | GCC
+
+[FeaturePcd]
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable
+ gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping
+ gArmPlatformTokenSpaceGuid.PcdStandalone
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
diff --git a/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSM.c b/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSM.c new file mode 100644 index 000000000..eaaf5ab64 --- /dev/null +++ b/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSM.c @@ -0,0 +1,212 @@ +/** @file
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+#include <ArmPlatform.h>
+
+UINTN
+ArmGetCpuCountPerCluster (
+ VOID
+ );
+
+ARM_CORE_INFO mVersatileExpressMpCoreInfoTable[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 0, Core 1
+ 0x0, 0x1,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 0, Core 2
+ 0x0, 0x2,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 0, Core 3
+ 0x0, 0x3,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 1, Core 0
+ 0x1, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 1, Core 1
+ 0x1, 0x1,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 1, Core 2
+ 0x1, 0x2,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 1, Core 3
+ 0x1, 0x3,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ }
+};
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+ @return Return the current Boot Mode of the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Initialize controllers that must setup in the normal world
+
+ This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
+ in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ if (!(((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))) {
+ return RETURN_SUCCESS;
+ }
+
+ // Disable memory remapping and return to normal mapping
+ MmioOr32 (SP810_CTRL_BASE, BIT8);
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Initialize the system (or sometimes called permanent) memory
+
+ This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+ VOID
+ )
+{
+ // Nothing to do here
+}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+#if 0
+ UINT32 ProcType;
+
+ ProcType = MmioRead32 (ARM_VE_SYS_PROCID0_REG) & ARM_VE_SYS_PROC_ID_MASK;
+ if ((ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A9) || (ProcType == ARM_VE_SYS_PROC_ID_CORTEX_A15)) {
+ // Only support one cluster
+ *CoreCount = ArmGetCpuCountPerCluster ();
+ *ArmCoreTable = mVersatileExpressMpCoreInfoTable;
+ return EFI_SUCCESS;
+ } else {
+ return EFI_UNSUPPORTED;
+ }
+#else
+
+ *CoreCount = 2 * ArmGetCpuCountPerCluster ();
+ *ArmCoreTable = mVersatileExpressMpCoreInfoTable;
+
+ return EFI_SUCCESS;
+#endif
+}
+
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &mArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ *PpiListSize = sizeof(gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+}
diff --git a/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSMHelper.S b/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSMHelper.S new file mode 100644 index 000000000..ee5ce30aa --- /dev/null +++ b/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSMHelper.S @@ -0,0 +1,117 @@ +#
+# Copyright (c) 2011, ARM Limited. All rights reserved.
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <AutoGen.h>
+#include "AsmMacroIoLib.inc"
+
+#include <Chipset/ArmCortexA9.h>
+
+.text
+.align 2
+
+GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
+GCC_ASM_EXPORT(ArmGetCpuCountPerCluster)
+GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
+GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
+GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
+
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)
+GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)
+
+ASM_PFX(ArmPlatformPeiBootAction):
+ bx lr
+
+# IN None
+# OUT r0 = SCU Base Address
+ASM_PFX(ArmGetScuBaseAddress):
+ # Read Configuration Base Address Register. ArmCBar cannot be called to get
+ # the Configuration BAR as a stack is not necessary setup. The SCU is at the
+ # offset 0x0000 from the Private Memory Region.
+ mrc p15, 4, r0, c15, c0, 0
+ bx lr
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)
+ ldr r0, [r0]
+ bx lr
+
+# IN None
+# OUT r0 = number of cores present in the system
+ASM_PFX(ArmGetCpuCountPerCluster):
+ stmfd SP!, {r1-r2}
+
+ # Read CP15 MIDR
+ mrc p15, 0, r1, c0, c0, 0
+
+ # Check if the CPU is A15
+ mov r1, r1, LSR #4
+ LoadConstantToReg (ARM_CPU_TYPE_MASK, r0)
+ and r1, r1, r0
+
+ LoadConstantToReg (ARM_CPU_TYPE_A15, r0)
+ cmp r1, r0
+ beq _Read_cp15_reg
+
+_CPU_is_not_A15:
+ mov r2, lr @ Save link register
+ bl ArmGetScuBaseAddress @ Read SCU Base Address
+ mov lr, r2 @ Restore link register val
+ ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count
+ b _Return
+
+_Read_cp15_reg:
+ mrc p15, 1, r0, c9, c0, 2 @ Read C9 register of CP15 to get CPU count
+ lsr r0, #24
+
+_Return:
+ and r0, r0, #3
+ # Add '1' to the number of CPU on the Cluster
+ add r0, r0, #1
+ ldmfd SP!, {r1-r2}
+ bx lr
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_PFX(ArmPlatformIsPrimaryCore):
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)
+ ldr r1, [r1]
+ and r0, r0, r1
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)
+ ldr r1, [r1]
+ cmp r0, r1
+ moveq r0, #1
+ movne r0, #0
+ bx lr
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+ASM_PFX(ArmPlatformGetCorePosition):
+ and r1, r0, #ARM_CORE_MASK
+ and r0, r0, #ARM_CLUSTER_MASK
+ add r0, r1, r0, LSR #7
+ bx lr
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSMHelper.asm b/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSMHelper.asm new file mode 100644 index 000000000..d1d386342 --- /dev/null +++ b/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSMHelper.asm @@ -0,0 +1,125 @@ +//
+// Copyright (c) 2011, ARM Limited. All rights reserved.
+// Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AsmMacroIoLib.h>
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include <Chipset/ArmCortexA9.h>
+
+#include <AutoGen.h>
+
+ INCLUDE AsmMacroIoLib.inc
+
+ EXPORT ArmPlatformPeiBootAction
+ EXPORT ArmGetCpuCountPerCluster
+ EXPORT ArmPlatformIsPrimaryCore
+ EXPORT ArmPlatformGetPrimaryCoreMpId
+ EXPORT ArmPlatformGetCorePosition
+
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCore
+ IMPORT _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask
+
+ AREA RTSMHelper, CODE, READONLY
+
+ArmPlatformPeiBootAction FUNCTION
+ bx lr
+ ENDFUNC
+
+// IN None
+// OUT r0 = SCU Base Address
+ArmGetScuBaseAddress FUNCTION
+ // Read Configuration Base Address Register. ArmCBar cannot be called to get
+ // the Configuration BAR as a stack is not necessary setup. The SCU is at the
+ // offset 0x0000 from the Private Memory Region.
+ mrc p15, 4, r0, c15, c0, 0
+ bx lr
+ ENDFUNC
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ArmPlatformGetPrimaryCoreMpId FUNCTION
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0)
+ ldr r0, [r0]
+ bx lr
+ ENDFUNC
+
+// IN None
+// OUT r0 = number of cores present in the system
+ArmGetCpuCountPerCluster FUNCTION
+ stmfd SP!, {r1-r2}
+
+ // Read CP15 MIDR
+ mrc p15, 0, r1, c0, c0, 0
+
+ // Check if the CPU is A15
+ mov r1, r1, LSR #4
+ mov r0, #ARM_CPU_TYPE_MASK
+ and r1, r1, r0
+
+ mov r0, #ARM_CPU_TYPE_A15
+ cmp r1, r0
+ beq _Read_cp15_reg
+
+_CPU_is_not_A15
+ mov r2, lr ; Save link register
+ bl ArmGetScuBaseAddress ; Read SCU Base Address
+ mov lr, r2 ; Restore link register val
+ ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count
+ b _Return
+
+_Read_cp15_reg
+ mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count
+ lsr r0, #24
+
+
+_Return
+ and r0, r0, #3
+ // Add '1' to the number of CPU on the Cluster
+ add r0, r0, #1
+ ldmfd SP!, {r1-r2}
+ bx lr
+ ENDFUNC
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ArmPlatformIsPrimaryCore FUNCTION
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)
+ ldr r1, [r1]
+ and r0, r0, r1
+ LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)
+ ldr r1, [r1]
+ cmp r0, r1
+ moveq r0, #1
+ movne r0, #0
+ bx lr
+ ENDFUNC
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+ArmPlatformGetCorePosition FUNCTION
+ and r1, r0, #ARM_CORE_MASK
+ and r0, r0, #ARM_CLUSTER_MASK
+ add r0, r1, r0, LSR #7
+ bx lr
+ ENDFUNC
+
+ END
diff --git a/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSMMem.c b/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSMMem.c new file mode 100644 index 000000000..93f856f82 --- /dev/null +++ b/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSMMem.c @@ -0,0 +1,86 @@ +/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <ArmPlatform.h>
+
+// Number of Virtual Memory Map Descriptors without a Logic Tile
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 8
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+ )
+{
+ ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
+ UINTN Index = 0;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ ASSERT(VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+
+ if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
+ CacheAttributes = DDR_ATTRIBUTES_CACHED;
+ } else {
+ CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
+ }
+ // memory
+ VirtualMemoryTable[Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0xe0000000;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
+
+ // register
+ VirtualMemoryTable[++Index].PhysicalBase = 0xe0000000;
+ VirtualMemoryTable[Index].VirtualBase = 0xe0000000;
+ VirtualMemoryTable[Index].Length = 0x0e000000;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // flash
+ VirtualMemoryTable[++Index].PhysicalBase = 0xf0000000;
+ VirtualMemoryTable[Index].VirtualBase = 0xf0000000;
+ VirtualMemoryTable[Index].Length = 0x10000000;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/D01SecLib.inf b/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/D01SecLib.inf new file mode 100644 index 000000000..2a88d3959 --- /dev/null +++ b/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/D01SecLib.inf @@ -0,0 +1,24 @@ +#/* @file
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = RTSMArmD01SecLib
+ FILE_GUID = 1fdaabb0-ab7d-480c-91ff-428dc1546f3a
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformSecLib
+
+[binaries.common]
+ LIB|RTSMArmD01SecLib.lib
diff --git a/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/RTSMArmD01SecLib.lib b/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/RTSMArmD01SecLib.lib Binary files differnew file mode 100644 index 000000000..a6b5ba005 --- /dev/null +++ b/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/RTSMArmD01SecLib.lib diff --git a/HisiPkg/D01BoardPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c b/HisiPkg/D01BoardPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c new file mode 100644 index 000000000..82221cf9a --- /dev/null +++ b/HisiPkg/D01BoardPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.c @@ -0,0 +1,649 @@ +/** @file
+ Implement EFI RealTimeClock runtime services via RTC Lib.
+
+ Currently this driver does not support runtime virtual calling.
+
+ Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/IoLib.h>
+#include <Library/RealTimeClockLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/ArmPlatformSysConfigLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Protocol/RealTimeClock.h>
+#include <Guid/GlobalVariable.h>
+#include <Drivers/PL031RealTimeClock.h>
+#include <Library/ArmArchTimerLib.h>
+#include <ArmPlatform.h>
+
+STATIC CONST CHAR16 mTimeZoneVariableName[] = L"PL031RtcTimeZone";
+STATIC CONST CHAR16 mDaylightVariableName[] = L"PL031RtcDaylight";
+STATIC BOOLEAN mPL031Initialized = FALSE;
+
+EFI_STATUS
+IdentifyPL031 (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ // Check if this is a PrimeCell Peripheral
+ if ( (MmioRead8 (PL031_RTC_PCELL_ID0) != 0x0D)
+ || (MmioRead8 (PL031_RTC_PCELL_ID1) != 0xF0)
+ || (MmioRead8 (PL031_RTC_PCELL_ID2) != 0x05)
+ || (MmioRead8 (PL031_RTC_PCELL_ID3) != 0xB1)) {
+ Status = EFI_NOT_FOUND;
+ goto EXIT;
+ }
+
+ // Check if this PrimeCell Peripheral is the PL031 Real Time Clock
+ if ( (MmioRead8 (PL031_RTC_PERIPH_ID0) != 0x31)
+ || (MmioRead8 (PL031_RTC_PERIPH_ID1) != 0x10)
+ || ((MmioRead8 (PL031_RTC_PERIPH_ID2) & 0xF) != 0x04)
+ || (MmioRead8 (PL031_RTC_PERIPH_ID3) != 0x00)) {
+ Status = EFI_NOT_FOUND;
+ goto EXIT;
+ }
+
+ Status = EFI_SUCCESS;
+
+ EXIT:
+ return Status;
+}
+
+EFI_STATUS
+InitializePL031 (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ // Prepare the hardware
+ Status = IdentifyPL031();
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+
+ // Ensure interrupts are masked. We do not want RTC interrupts in UEFI
+ if ((MmioRead32 (PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER) & PL031_SET_IRQ_MASK) != PL031_SET_IRQ_MASK) {
+ MmioOr32 (PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER, PL031_SET_IRQ_MASK);
+ }
+
+ // Clear any existing interrupts
+ if ((MmioRead32 (PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER) & PL031_IRQ_TRIGGERED) == PL031_IRQ_TRIGGERED) {
+ MmioOr32 (PL031_RTC_ICR_IRQ_CLEAR_REGISTER, PL031_CLEAR_IRQ);
+ }
+
+ // Start the clock counter
+ if ((MmioRead32 (PL031_RTC_CR_CONTROL_REGISTER) & PL031_RTC_ENABLED) != PL031_RTC_ENABLED) {
+ MmioOr32 (PL031_RTC_CR_CONTROL_REGISTER, PL031_RTC_ENABLED);
+ }
+
+ mPL031Initialized = TRUE;
+
+ EXIT:
+ return Status;
+}
+
+/**
+ Converts Epoch seconds (elapsed since 1970 JANUARY 01, 00:00:00 UTC) to EFI_TIME
+ **/
+VOID
+EpochToEfiTime (
+ IN UINTN EpochSeconds,
+ OUT EFI_TIME *Time
+ )
+{
+ UINTN a;
+ UINTN b;
+ UINTN c;
+ UINTN d;
+ UINTN g;
+ UINTN j;
+ UINTN m;
+ UINTN y;
+ UINTN da;
+ UINTN db;
+ UINTN dc;
+ UINTN dg;
+ UINTN hh;
+ UINTN mm;
+ UINTN ss;
+ UINTN J;
+
+ J = (EpochSeconds / 86400) + 2440588;
+ j = J + 32044;
+ g = j / 146097;
+ dg = j % 146097;
+ c = (((dg / 36524) + 1) * 3) / 4;
+ dc = dg - (c * 36524);
+ b = dc / 1461;
+ db = dc % 1461;
+ a = (((db / 365) + 1) * 3) / 4;
+ da = db - (a * 365);
+ y = (g * 400) + (c * 100) + (b * 4) + a;
+ m = (((da * 5) + 308) / 153) - 2;
+ d = da - (((m + 4) * 153) / 5) + 122;
+
+ Time->Year = y - 4800 + ((m + 2) / 12);
+ Time->Month = ((m + 2) % 12) + 1;
+ Time->Day = d + 1;
+
+ ss = EpochSeconds % 60;
+ a = (EpochSeconds - ss) / 60;
+ mm = a % 60;
+ b = (a - mm) / 60;
+ hh = b % 24;
+
+ Time->Hour = hh;
+ Time->Minute = mm;
+ Time->Second = ss;
+ Time->Nanosecond = 0;
+
+}
+
+/**
+ Converts EFI_TIME to Epoch seconds (elapsed since 1970 JANUARY 01, 00:00:00 UTC)
+ **/
+UINTN
+EfiTimeToEpoch (
+ IN EFI_TIME *Time
+ )
+{
+ UINTN a;
+ UINTN y;
+ UINTN m;
+ UINTN JulianDate; // Absolute Julian Date representation of the supplied Time
+ UINTN EpochDays; // Number of days elapsed since EPOCH_JULIAN_DAY
+ UINTN EpochSeconds;
+
+ a = (14 - Time->Month) / 12 ;
+ y = Time->Year + 4800 - a;
+ m = Time->Month + (12*a) - 3;
+
+ JulianDate = Time->Day + ((153*m + 2)/5) + (365*y) + (y/4) - (y/100) + (y/400) - 32045;
+
+ ASSERT (JulianDate >= EPOCH_JULIAN_DATE);
+ EpochDays = JulianDate - EPOCH_JULIAN_DATE;
+
+ EpochSeconds = (EpochDays * SEC_PER_DAY) + ((UINTN)Time->Hour * SEC_PER_HOUR) + (Time->Minute * SEC_PER_MIN) + Time->Second;
+
+ return EpochSeconds;
+}
+
+BOOLEAN
+IsLeapYear (
+ IN EFI_TIME *Time
+ )
+{
+ if (Time->Year % 4 == 0) {
+ if (Time->Year % 100 == 0) {
+ if (Time->Year % 400 == 0) {
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+ } else {
+ return TRUE;
+ }
+ } else {
+ return FALSE;
+ }
+}
+
+BOOLEAN
+DayValid (
+ IN EFI_TIME *Time
+ )
+{
+ INTN DayOfMonth[12] = { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+
+ if (Time->Day < 1 ||
+ Time->Day > DayOfMonth[Time->Month - 1] ||
+ (Time->Month == 2 && (!IsLeapYear (Time) && Time->Day > 28))
+ ) {
+ return FALSE;
+ }
+
+ return TRUE;
+}
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+ @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an authentication failure.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINT64 Temp;
+ UINT32 EpochSeconds;
+ INT16 TimeZone = 0;
+ UINT8 Daylight = 0;
+ UINTN Size;
+
+#if 0
+ // Initialize the hardware if not already done
+ if (!mPL031Initialized) {
+ Status = InitializePL031 ();
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+ }
+#endif
+ // Snapshot the time as early in the function call as possible
+ // On some platforms we may have access to a battery backed up hardware clock.
+ // If such RTC exists try to use it first.
+ Status = ArmPlatformSysConfigGet (SYS_CFG_RTC, &EpochSeconds);
+ if (Status == EFI_UNSUPPORTED) {
+ // Battery backed up hardware RTC does not exist, revert to PL031
+ ArmArchTimerReadReg(CntPct,&Temp);
+ EpochSeconds = Temp / PcdGet32(PcdArmArchTimerFreqInHz);
+ //EpochSeconds = MmioRead32 (PL031_RTC_DR_DATA_REGISTER);
+
+ Status = EFI_SUCCESS;
+ } else if (EFI_ERROR (Status)) {
+ // Battery backed up hardware RTC exists but could not be read due to error. Abort.
+ goto EXIT;
+ } else {
+ // Battery backed up hardware RTC exists and we read the time correctly from it.
+ // Now sync the PL031 to the new time.
+ MmioWrite32 (PL031_RTC_LR_LOAD_REGISTER, EpochSeconds);
+ }
+
+ // Ensure Time is a valid pointer
+ if (Time == NULL) {
+ Status = EFI_INVALID_PARAMETER;
+ goto EXIT;
+ }
+
+ // Get the current time zone information from non-volatile storage
+ Size = sizeof (TimeZone);
+ Status = gRT->GetVariable (
+ (CHAR16 *)mTimeZoneVariableName,
+ &gEfiCallerIdGuid,
+ NULL,
+ &Size,
+ (VOID *)&TimeZone
+ );
+
+ if (EFI_ERROR (Status)) {
+ ASSERT(Status != EFI_INVALID_PARAMETER);
+ ASSERT(Status != EFI_BUFFER_TOO_SMALL);
+
+ if (Status != EFI_NOT_FOUND)
+ goto EXIT;
+
+ // The time zone variable does not exist in non-volatile storage, so create it.
+ Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE;
+ // Store it
+ Status = gRT->SetVariable (
+ (CHAR16 *)mTimeZoneVariableName,
+ &gEfiCallerIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ Size,
+ (VOID *)&(Time->TimeZone)
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ EFI_D_ERROR,
+ "LibGetTime: Failed to save %s variable to non-volatile storage, Status = %r\n",
+ mTimeZoneVariableName,
+ Status
+ ));
+ goto EXIT;
+ }
+ } else {
+ // Got the time zone
+ Time->TimeZone = TimeZone;
+
+ // Check TimeZone bounds: -1440 to 1440 or 2047
+ if (((Time->TimeZone < -1440) || (Time->TimeZone > 1440))
+ && (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE)) {
+ Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE;
+ }
+
+ // Adjust for the correct time zone
+ if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) {
+ EpochSeconds += Time->TimeZone * SEC_PER_MIN;
+ }
+ }
+
+ // Get the current daylight information from non-volatile storage
+ Size = sizeof (Daylight);
+ Status = gRT->GetVariable (
+ (CHAR16 *)mDaylightVariableName,
+ &gEfiCallerIdGuid,
+ NULL,
+ &Size,
+ (VOID *)&Daylight
+ );
+
+ if (EFI_ERROR (Status)) {
+ ASSERT(Status != EFI_INVALID_PARAMETER);
+ ASSERT(Status != EFI_BUFFER_TOO_SMALL);
+
+ if (Status != EFI_NOT_FOUND)
+ goto EXIT;
+
+ // The daylight variable does not exist in non-volatile storage, so create it.
+ Time->Daylight = 0;
+ // Store it
+ Status = gRT->SetVariable (
+ (CHAR16 *)mDaylightVariableName,
+ &gEfiCallerIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ Size,
+ (VOID *)&(Time->Daylight)
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ EFI_D_ERROR,
+ "LibGetTime: Failed to save %s variable to non-volatile storage, Status = %r\n",
+ mDaylightVariableName,
+ Status
+ ));
+ goto EXIT;
+ }
+ } else {
+ // Got the daylight information
+ Time->Daylight = Daylight;
+
+ // Adjust for the correct period
+ if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT) {
+ // Convert to adjusted time, i.e. spring forwards one hour
+ EpochSeconds += SEC_PER_HOUR;
+ }
+ }
+
+ // Convert from internal 32-bit time to UEFI time
+ EpochToEfiTime (EpochSeconds, Time);
+
+ // Update the Capabilities info
+ if (Capabilities != NULL) {
+ // PL031 runs at frequency 1Hz
+ Capabilities->Resolution = PL031_COUNTS_PER_SECOND;
+ // Accuracy in ppm multiplied by 1,000,000, e.g. for 50ppm set 50,000,000
+ Capabilities->Accuracy = (UINT32)PcdGet32 (PcdPL031RtcPpmAccuracy);
+ // FALSE: Setting the time does not clear the values below the resolution level
+ Capabilities->SetsToZero = FALSE;
+ }
+
+ EXIT:
+ return Status;
+}
+
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+ EFI_STATUS Status;
+ UINTN EpochSeconds;
+
+ // Check the input parameters are within the range specified by UEFI
+ if ((Time->Year < 1900) ||
+ (Time->Year > 9999) ||
+ (Time->Month < 1 ) ||
+ (Time->Month > 12 ) ||
+ (!DayValid (Time) ) ||
+ (Time->Hour > 23 ) ||
+ (Time->Minute > 59 ) ||
+ (Time->Second > 59 ) ||
+ (Time->Nanosecond > 999999999) ||
+ (!((Time->TimeZone == EFI_UNSPECIFIED_TIMEZONE) || ((Time->TimeZone >= -1440) && (Time->TimeZone <= 1440)))) ||
+ (Time->Daylight & (~(EFI_TIME_ADJUST_DAYLIGHT | EFI_TIME_IN_DAYLIGHT)))
+ ) {
+ Status = EFI_INVALID_PARAMETER;
+ goto EXIT;
+ }
+
+ // Because the PL031 is a 32-bit counter counting seconds,
+ // the maximum time span is just over 136 years.
+ // Time is stored in Unix Epoch format, so it starts in 1970,
+ // Therefore it can not exceed the year 2106.
+ if ((Time->Year < 1970) || (Time->Year >= 2106)) {
+ Status = EFI_UNSUPPORTED;
+ goto EXIT;
+ }
+
+ // Initialize the hardware if not already done
+ if (!mPL031Initialized) {
+ Status = InitializePL031 ();
+ if (EFI_ERROR (Status)) {
+ goto EXIT;
+ }
+ }
+
+ EpochSeconds = EfiTimeToEpoch (Time);
+
+ // Adjust for the correct time zone, i.e. convert to UTC time zone
+ if (Time->TimeZone != EFI_UNSPECIFIED_TIMEZONE) {
+ EpochSeconds -= Time->TimeZone * SEC_PER_MIN;
+ }
+
+ // TODO: Automatic Daylight activation
+
+ // Adjust for the correct period
+ if ((Time->Daylight & EFI_TIME_IN_DAYLIGHT) == EFI_TIME_IN_DAYLIGHT) {
+ // Convert to un-adjusted time, i.e. fall back one hour
+ EpochSeconds -= SEC_PER_HOUR;
+ }
+
+ // On some platforms we may have access to a battery backed up hardware clock.
+ //
+ // If such RTC exists then it must be updated first, before the PL031,
+ // to minimise any time drift. This is important because the battery backed-up
+ // RTC maintains the master time for the platform across reboots.
+ //
+ // If such RTC does not exist then the following function returns UNSUPPORTED.
+ Status = ArmPlatformSysConfigSet (SYS_CFG_RTC, EpochSeconds);
+ if ((EFI_ERROR (Status)) && (Status != EFI_UNSUPPORTED)){
+ // Any status message except SUCCESS and UNSUPPORTED indicates a hardware failure.
+ goto EXIT;
+ }
+
+
+ // Set the PL031
+ MmioWrite32 (PL031_RTC_LR_LOAD_REGISTER, EpochSeconds);
+
+ // The accesses to Variable Services can be very slow, because we may be writing to Flash.
+ // Do this after having set the RTC.
+
+ // Save the current time zone information into non-volatile storage
+ Status = gRT->SetVariable (
+ (CHAR16 *)mTimeZoneVariableName,
+ &gEfiCallerIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof (Time->TimeZone),
+ (VOID *)&(Time->TimeZone)
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ EFI_D_ERROR,
+ "LibSetTime: Failed to save %s variable to non-volatile storage, Status = %r\n",
+ mTimeZoneVariableName,
+ Status
+ ));
+ goto EXIT;
+ }
+
+ // Save the current daylight information into non-volatile storage
+ Status = gRT->SetVariable (
+ (CHAR16 *)mDaylightVariableName,
+ &gEfiCallerIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
+ sizeof(Time->Daylight),
+ (VOID *)&(Time->Daylight)
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ EFI_D_ERROR,
+ "LibSetTime: Failed to save %s variable to non-volatile storage, Status = %r\n",
+ mDaylightVariableName,
+ Status
+ ));
+ goto EXIT;
+ }
+
+ EXIT:
+ return Status;
+}
+
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ // Setup the setters and getters
+ gRT->GetTime = LibGetTime;
+ gRT->SetTime = LibSetTime;
+ gRT->GetWakeupTime = LibGetWakeupTime;
+ gRT->SetWakeupTime = LibSetWakeupTime;
+
+ // Install the protocol
+ Handle = NULL;
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gEfiRealTimeClockArchProtocolGuid, NULL,
+ NULL
+ );
+
+ return Status;
+}
+
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+LibRtcVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ //
+ // Only needed if you are going to support the OS calling RTC functions in virtual mode.
+ // You will need to call EfiConvertPointer (). To convert any stored physical addresses
+ // to virtual address. After the OS transitions to calling in virtual mode, all future
+ // runtime calls will be made in virtual mode.
+ //
+ return;
+}
diff --git a/HisiPkg/D01BoardPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf b/HisiPkg/D01BoardPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf new file mode 100644 index 000000000..99165b79a --- /dev/null +++ b/HisiPkg/D01BoardPkg/Library/PL031RealTimeClockLib/PL031RealTimeClockLib.inf @@ -0,0 +1,45 @@ +#/** @file
+#
+# Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PL031RealTimeClockLib
+ FILE_GUID = 470DFB96-E205-4515-A75E-2E60F853E79D
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+[Sources.common]
+ PL031RealTimeClockLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+ IoLib
+ UefiLib
+ DebugLib
+ PcdLib
+ ArmPlatformSysConfigLib
+ ArmLib
+
+[Pcd]
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase
+ gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy
+
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
diff --git a/HisiPkg/D01BoardPkg/Library/ResetWdtLib/ResetWdtLib.c b/HisiPkg/D01BoardPkg/Library/ResetWdtLib/ResetWdtLib.c new file mode 100644 index 000000000..fde422e9e --- /dev/null +++ b/HisiPkg/D01BoardPkg/Library/ResetWdtLib/ResetWdtLib.c @@ -0,0 +1,37 @@ +/*******************************************************************
+#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#include <Library/ResetWdtLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SerialPortLib/SerialPortLib.h>
+
+void Delay(unsigned long ulCount)
+{
+ unsigned int ulRet, ulNumber;
+ for(ulRet = 0; ulRet < 2; ulRet++)
+ {
+ ulNumber = ulCount;
+ while ( ulNumber-- )
+ {
+ ;
+ }
+ }
+}
+void WDT_ResetWatchdog(void)
+{
+ outl_wdt((inl_wdt(GPIO3_BASE_ADDR) | GPIO_MASK(21)), GPIO3_BASE_ADDR);
+ Delay(100);
+ outl_wdt((inl_wdt(GPIO3_BASE_ADDR) & (~GPIO_MASK(21))), GPIO3_BASE_ADDR);
+ return;
+}
+
diff --git a/HisiPkg/D01BoardPkg/Library/ResetWdtLib/ResetWdtLib.inf b/HisiPkg/D01BoardPkg/Library/ResetWdtLib/ResetWdtLib.inf new file mode 100644 index 000000000..221cc008c --- /dev/null +++ b/HisiPkg/D01BoardPkg/Library/ResetWdtLib/ResetWdtLib.inf @@ -0,0 +1,41 @@ +#/** @file
+#
+# Component discription file for NorFlashDxe module
+#
+# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ResetWdtLib
+ FILE_GUID = 16D53E86-7EA6-47bd-862F-511FD9B8ABF0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ResetWdtLib
+
+
+[Sources.common]
+ ResetWdtLib.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ HisiPkg/HisiPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ DebugAgentLib
+ SerialPortLib
+
diff --git a/HisiPkg/D01BoardPkg/Sec/Sec/Arm/Arch.c b/HisiPkg/D01BoardPkg/Sec/Sec/Arm/Arch.c new file mode 100644 index 000000000..85df0816e --- /dev/null +++ b/HisiPkg/D01BoardPkg/Sec/Sec/Arm/Arch.c @@ -0,0 +1,25 @@ +/** @file
+*
+* Copyright (c) 2013, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Chipset/ArmV7.h>
+
+VOID
+EFIAPI
+ArmSecArchTrustzoneInit (
+ VOID
+ )
+{
+ // Write to CP15 Non-secure Access Control Register
+ ArmWriteNsacr (PcdGet32 (PcdArmNsacr));
+}
diff --git a/HisiPkg/D01BoardPkg/Sec/Sec/Arm/Helper.S b/HisiPkg/D01BoardPkg/Sec/Sec/Arm/Helper.S new file mode 100644 index 000000000..dd0a57275 --- /dev/null +++ b/HisiPkg/D01BoardPkg/Sec/Sec/Arm/Helper.S @@ -0,0 +1,88 @@ +#========================================================================================
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http:#opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#=======================================================================================
+
+#start of the code section
+.text
+.align 3
+
+GCC_ASM_EXPORT(return_from_exception)
+GCC_ASM_EXPORT(enter_monitor_mode)
+GCC_ASM_EXPORT(copy_cpsr_into_spsr)
+GCC_ASM_EXPORT(set_non_secure_mode)
+
+# r0: Monitor World EntryPoint
+# r1: MpId
+# r2: SecBootMode
+# r3: Secure Monitor mode stack
+ASM_PFX(enter_monitor_mode):
+ cmp r3, #0 @ If a Secure Monitor stack base has not been defined then use the Secure stack
+ moveq r3, sp
+
+ mrs r4, cpsr @ Save current mode (SVC) in r4
+ bic r5, r4, #0x1f @ Clear all mode bits
+ orr r5, r5, #0x16 @ Set bits for Monitor mode
+ msr cpsr_cxsf, r5 @ We are now in Monitor Mode
+
+ mov sp, r3 @ Set the stack of the Monitor Mode
+
+ mov lr, r0 @ Use the pass entrypoint as lr
+
+ msr spsr_cxsf, r4 @ Use saved mode for the MOVS jump to the kernel
+
+ mov r4, r0 @ Swap EntryPoint and MpId registers
+ mov r0, r1
+ mov r1, r2
+ mov r2, r3
+
+ bx r4
+
+# We cannot use the instruction 'movs pc, lr' because the caller can be written either in ARM or Thumb2 assembler.
+# When we will jump into this function, we will set the CPSR flag to ARM assembler. By copying directly 'lr' into
+# 'pc'; we will not change the CPSR flag and it will crash.
+# The way to fix this limitation is to do the movs into the ARM assmbler code and then do a 'bx'.
+ASM_PFX(return_from_exception):
+ ldr lr, returned_exception
+
+ #The following instruction breaks the code.
+ #movs pc, lr
+ mrs r2, cpsr
+ bic r2, r2, #0x1f
+ orr r2, r2, #0x13
+ msr cpsr_c, r2
+
+returned_exception: @ We are now in non-secure state
+ bx r0
+
+# Save the current Program Status Register (PSR) into the Saved PSR
+ASM_PFX(copy_cpsr_into_spsr):
+ mrs r0, cpsr
+ msr spsr_cxsf, r0
+ bx lr
+
+# Set the Non Secure Mode
+ASM_PFX(set_non_secure_mode):
+ push { r1 }
+ and r0, r0, #0x1f @ Keep only the mode bits
+ mrs r1, spsr @ Read the spsr
+ bic r1, r1, #0x1f @ Clear all mode bits
+ orr r1, r1, r0
+ msr spsr_cxsf, r1 @ write back spsr (may have caused a mode switch)
+ isb
+ pop { r1 }
+ bx lr @ return (hopefully thumb-safe!)
+
+dead:
+ b dead
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/HisiPkg/D01BoardPkg/Sec/Sec/Arm/Helper.asm b/HisiPkg/D01BoardPkg/Sec/Sec/Arm/Helper.asm new file mode 100644 index 000000000..4903e540f --- /dev/null +++ b/HisiPkg/D01BoardPkg/Sec/Sec/Arm/Helper.asm @@ -0,0 +1,80 @@ +//
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+// Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+ EXPORT return_from_exception
+ EXPORT enter_monitor_mode
+ EXPORT copy_cpsr_into_spsr
+ EXPORT set_non_secure_mode
+
+ AREA Helper, CODE, READONLY
+
+// r0: Monitor World EntryPoint
+// r1: MpId
+// r2: SecBootMode
+// r3: Secure Monitor mode stack
+enter_monitor_mode FUNCTION
+ cmp r3, #0 // If a Secure Monitor stack base has not been defined then use the Secure stack
+ moveq r3, sp
+
+ mrs r4, cpsr // Save current mode (SVC) in r4
+ bic r5, r4, #0x1f // Clear all mode bits
+ orr r5, r5, #0x16 // Set bits for Monitor mode
+ msr cpsr_cxsf, r5 // We are now in Monitor Mode
+
+ mov sp, r3 // Set the stack of the Monitor Mode
+
+ mov lr, r0 // Use the pass entrypoint as lr
+
+ msr spsr_cxsf, r4 // Use saved mode for the MOVS jump to the kernel
+
+ mov r4, r0 // Swap EntryPoint and MpId registers
+ mov r0, r1
+ mov r1, r2
+ mov r2, r3
+
+ bx r4
+ ENDFUNC
+
+// We cannot use the instruction 'movs pc, lr' because the caller can be written either in ARM or Thumb2 assembler.
+// When we will jump into this function, we will set the CPSR flag to ARM assembler. By copying directly 'lr' into
+// 'pc'; we will not change the CPSR flag and it will crash.
+// The way to fix this limitation is to do the movs into the ARM assmbler code and then do a 'bx'.
+return_from_exception
+ adr lr, returned_exception
+ movs pc, lr
+returned_exception // We are now in non-secure state
+ bx r0
+
+// Save the current Program Status Register (PSR) into the Saved PSR
+copy_cpsr_into_spsr
+ mrs r0, cpsr
+ msr spsr_cxsf, r0
+ bx lr
+
+// Set the Non Secure Mode
+set_non_secure_mode
+ push { r1 }
+ and r0, r0, #0x1f // Keep only the mode bits
+ mrs r1, spsr // Read the spsr
+ bic r1, r1, #0x1f // Clear all mode bits
+ orr r1, r1, r0
+ msr spsr_cxsf, r1 // write back spsr (may have caused a mode switch)
+ isb
+ pop { r1 }
+ bx lr // return (hopefully thumb-safe!)
+
+dead
+ B dead
+
+ END
diff --git a/HisiPkg/D01BoardPkg/Sec/Sec/Arm/SecEntryPoint.S b/HisiPkg/D01BoardPkg/Sec/Sec/Arm/SecEntryPoint.S new file mode 100644 index 000000000..85fccff95 --- /dev/null +++ b/HisiPkg/D01BoardPkg/Sec/Sec/Arm/SecEntryPoint.S @@ -0,0 +1,137 @@ +//
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+// Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AutoGen.h>
+#include <AsmMacroIoLib.h>
+#include "SecInternal.h"
+
+.text
+.align 3
+
+GCC_ASM_IMPORT(CEntryPoint)
+GCC_ASM_IMPORT(ArmPlatformSecBootAction)
+GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)
+GCC_ASM_IMPORT(ArmDisableInterrupts)
+GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
+GCC_ASM_IMPORT(ArmReadMpidr)
+GCC_ASM_IMPORT(ArmCallWFE)
+GCC_ASM_EXPORT(_ModuleEntryPoint)
+
+StartupAddr: .word ASM_PFX(CEntryPoint)
+
+// Convert the (ClusterId,CoreId) into a Core Position
+// 0x0F03 is the magic value for ARM_CORE_MASK | ARM_CLUSTER_MASK
+//Core is 0-1 bits and cluster is 8-11 bits
+#define GetCorePositionFromMpId(Pos, MpId, Tmp) \
+ ldr Tmp, =0x0F03 ; \
+ and MpId, Tmp ; \
+ lsr Pos, MpId, #6 ; \
+ and Tmp, MpId, #3 ; \
+ add Pos, Pos, Tmp
+
+ASM_PFX(_ModuleEntryPoint):
+ // First ensure all interrupts are disabled
+ bl ASM_PFX(ArmDisableInterrupts)
+
+ // Ensure that the MMU and caches are off
+ bl ASM_PFX(ArmDisableCachesAndMmu)
+
+ // By default, we are doing a cold boot
+ mov r10, #ARM_SEC_COLD_BOOT
+
+ // Jump to Platform Specific Boot Action function
+ blx ASM_PFX(ArmPlatformSecBootAction)
+
+_IdentifyCpu:
+ // Identify CPU ID
+ bl ASM_PFX(ArmReadMpidr)
+ // Get ID of this CPU in Multicore system
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
+ and r5, r0, r1
+
+ // Is it the Primary Core ?
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)
+ cmp r5, r3
+ // Only the primary core initialize the memory (SMC)
+ beq _InitMem
+
+_WaitInitMem:
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
+ // Otherwise we have to wait the Primary Core to finish the initialization
+ cmp r10, #ARM_SEC_COLD_BOOT
+ bne _SetupSecondaryCoreStack
+
+ // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)
+ bl ASM_PFX(ArmCallWFE)
+ // Now the Init Mem is initialized, we setup the secondary core stacks
+ b _SetupSecondaryCoreStack
+
+_InitMem:
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
+ cmp r10, #ARM_SEC_COLD_BOOT
+ bne _SetupPrimaryCoreStack
+
+ // Initialize Init Boot Memory
+ bl ASM_PFX(ArmPlatformSecBootMemoryInit)
+
+ // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
+
+_SetupPrimaryCoreStack:
+ // Get the top of the primary stacks (and the base of the secondary stacks)
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
+ add r1, r1, r2
+
+ LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)
+
+ // The reserved space for global variable must be 8-bytes aligned for pushing
+ // 64-bit variable on the stack
+ SetPrimaryStack (r1, r2, r3)
+ b _PrepareArguments
+
+_SetupSecondaryCoreStack:
+ // Get the top of the primary stacks (and the base of the secondary stacks)
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
+ add r1, r1, r2
+
+ // Get the Core Position (ClusterId * 4) + CoreId
+ GetCorePositionFromMpId(r0, r5, r2)
+ // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
+ add r0, r0, #1
+
+ // StackOffset = CorePos * StackSize
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
+ mul r0, r0, r2
+ // SP = StackBase + StackOffset
+ add sp, r1, r0
+
+_PrepareArguments:
+ // Move sec startup address into a data register
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)
+ ldr r3, StartupAddr
+
+ ORR r3, r3, #(0xf0 << 24)
+ ORR r3, r3, #(0x10 << 16)
+
+ // Jump to SEC C code
+ // r0 = mp_id
+ // r1 = Boot Mode
+ mov r0, r5
+ mov r1, r10
+ blx r3
+
+_NeverReturn:
+ b _NeverReturn
diff --git a/HisiPkg/D01BoardPkg/Sec/Sec/Arm/SecEntryPoint.asm b/HisiPkg/D01BoardPkg/Sec/Sec/Arm/SecEntryPoint.asm new file mode 100644 index 000000000..ff24bc5f1 --- /dev/null +++ b/HisiPkg/D01BoardPkg/Sec/Sec/Arm/SecEntryPoint.asm @@ -0,0 +1,148 @@ +//
+// Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+// Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AutoGen.h>
+#include <AsmMacroIoLib.h>
+#include "SecInternal.h"
+
+ INCLUDE AsmMacroIoLib.inc
+
+ IMPORT CEntryPoint
+ IMPORT ArmPlatformSecBootAction
+ IMPORT ArmPlatformSecBootMemoryInit
+ IMPORT ArmDisableInterrupts
+ IMPORT ArmDisableCachesAndMmu
+ IMPORT ArmReadMpidr
+ IMPORT ArmCallWFE
+ EXPORT _ModuleEntryPoint
+
+ PRESERVE8
+ AREA SecEntryPoint, CODE, READONLY
+
+StartupAddr DCD CEntryPoint
+CTRL_M_BIT EQU (1 << 0)
+CTRL_C_BIT EQU (1 << 2)
+CTRL_B_BIT EQU (1 << 7)
+CTRL_I_BIT EQU (1 << 12)
+
+_ModuleEntryPoint FUNCTION
+ // First ensure all interrupts are disabled
+ ;blx ArmDisableInterrupts
+ cpsie if
+ isb
+
+ // Ensure that the MMU and caches are off
+ ;blx ArmDisableCachesAndMmu
+ mrc p15, 0, r0, c1, c0, 0 ; Get control register
+ bic r0, r0, #CTRL_M_BIT ; Disable MMU
+ bic r0, r0, #CTRL_C_BIT ; Disable D Cache
+ bic r0, r0, #CTRL_I_BIT ; Disable I Cache
+ mcr p15, 0, r0, c1, c0, 0 ; Write control register
+ dsb
+ isb
+
+ // By default, we are doing a cold boot
+ ;mov r10, #ARM_SEC_COLD_BOOT
+
+ // Jump to Platform Specific Boot Action function
+ blx ArmPlatformSecBootAction
+
+_IdentifyCpu
+ // Identify CPU ID
+ bl ArmReadMpidr
+ // Get ID of this CPU in Multicore system
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)
+ and r5, r0, r1
+
+ // Is it the Primary Core ?
+ LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)
+ cmp r5, r3
+ // Only the primary core initialize the memory (SMC)
+ beq _InitMem
+
+_WaitInitMem
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
+ // Otherwise we have to wait the Primary Core to finish the initialization
+ cmp r10, #ARM_SEC_COLD_BOOT
+ bne _SetupSecondaryCoreStack
+
+ // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)
+ bl ArmCallWFE
+ // Now the Init Mem is initialized, we setup the secondary core stacks
+ b _SetupSecondaryCoreStack
+
+_InitMem
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
+ ;cmp r10, #ARM_SEC_COLD_BOOT
+ ;bne _SetupPrimaryCoreStack
+
+ // Initialize Init Boot Memory
+ bl ArmPlatformSecBootMemoryInit
+
+ // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)
+ ;LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)
+
+;_SetupPrimaryCoreStack
+ ;// Get the top of the primary stacks (and the base of the secondary stacks)
+ ;LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
+ ;LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
+ ;add r1, r1, r2
+
+ ;LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)
+
+ ;// The reserved space for global variable must be 8-bytes aligned for pushing
+ ;// 64-bit variable on the stack
+ ;SetPrimaryStack (r1, r2, r3)
+ b _PrepareArguments
+
+_SetupSecondaryCoreStack
+ // Get the top of the primary stacks (and the base of the secondary stacks)
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)
+ add r1, r1, r2
+
+ // Get the Core Position (ClusterId * 4) + CoreId
+ ;GetCorePositionFromMpId(r0, r5, r2)
+ lsr r0, r5, #6
+ and r2, r5, #3
+ add r0, r0, r2
+ // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
+ add r0, r0, #1
+
+ // StackOffset = CorePos * StackSize
+ LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)
+ mul r0, r0, r2
+ // SP = StackBase + StackOffset
+ add sp, r1, r0
+
+_PrepareArguments
+ // Move sec startup address into a data register
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)
+ ldr r3, StartupAddr
+
+ ORR r3, r3, #(0xf0 << 24)
+ ORR r3, r3, #(0x10 << 16)
+
+ // Jump to SEC C code
+ // r0 = mp_id
+ // r1 = Boot Mode
+ mov r0, r5
+ mov r1, r10
+
+ blx r3
+ ENDFUNC
+
+_NeverReturn
+ b _NeverReturn
+ END
diff --git a/HisiPkg/D01BoardPkg/Sec/Sec/Sec.c b/HisiPkg/D01BoardPkg/Sec/Sec/Sec.c new file mode 100644 index 000000000..31b2669f8 --- /dev/null +++ b/HisiPkg/D01BoardPkg/Sec/Sec/Sec.c @@ -0,0 +1,197 @@ +/** @file
+* Main file supporting the SEC Phase on ARM Platforms
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmTrustedMonitorLib.h>
+#include <Library/DebugAgentLib.h>
+#include <Library/PrintLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/ArmGicLib.h>
+
+#include "SecInternal.h"
+
+#define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
+VOID
+CEntryPoint (
+ IN UINTN MpId,
+ IN UINTN SecBootMode
+ )
+{
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+ UINTN JumpAddress;
+
+ // Invalidate the data cache. Doesn't have to do the Data cache clean.
+ ArmInvalidateDataCache();
+
+ // Invalidate Instruction Cache
+ ArmInvalidateInstructionCache();
+
+ // Invalidate I & D TLBs
+ ArmInvalidateInstructionAndDataTlb();
+
+ // CPU specific settings
+ ArmCpuSetup (MpId);
+
+ // Enable Floating Point Coprocessor if supported by the platform
+ if (FixedPcdGet32 (PcdVFPEnabled)) {
+ ArmEnableVFP();
+ }
+
+ // Initialize peripherals that must be done at the early stage
+ // Example: Some L2 controller, interconnect, clock, DMC, etc
+ ArmPlatformSecInitialize (MpId);
+
+ // Primary CPU clears out the SCU tag RAMs, secondaries wait
+ if ((((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore)) && (SecBootMode == ARM_SEC_COLD_BOOT)) {
+ if (ArmIsMpCore()) {
+ // Signal for the initial memory is configured (event: BOOT_MEM_INIT)
+ ArmCallSEV ();
+ }
+
+ // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
+ // In non SEC modules the init call is in autogenerated code.
+ SerialPortInitialize ();
+
+ // Start talking
+ if (FixedPcdGetBool (PcdTrustzoneSupport)) {
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Secure UEFI firmware %s built at %a on %a\n\r",
+ (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
+ } else {
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Boot firmware %s built at %a on %a\n\r",
+ (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
+ }
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+ // Initialize the Debug Agent for Source Level Debugging
+ InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
+ SaveAndSetDebugTimerInterrupt (TRUE);
+
+ // Enable the GIC distributor and CPU Interface
+ // - no other Interrupts are enabled, doesn't have to worry about the priority.
+ // - all the cores are in secure state, use secure SGI's
+ ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
+ ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+ } else {
+ // Enable the GIC CPU Interface
+ ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+ }
+
+ // Enable Full Access to CoProcessors
+ ArmWriteCpacr (CPACR_CP_FULL_ACCESS);
+
+ // Test if Trustzone is supported on this platform
+ if (FixedPcdGetBool (PcdTrustzoneSupport)) {
+ if (ArmIsMpCore()) {
+ // Setup SMP in Non Secure world
+ ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
+ }
+
+ // Either we use the Secure Stacks for Secure Monitor (in this case (Base == 0) && (Size == 0))
+ // Or we use separate Secure Monitor stacks (but (Base != 0) && (Size != 0))
+ ASSERT (((PcdGet32(PcdCPUCoresSecMonStackBase) == 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) == 0)) ||
+ ((PcdGet32(PcdCPUCoresSecMonStackBase) != 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) != 0)));
+
+ // Enter Monitor Mode
+ enter_monitor_mode ((UINTN)TrustedWorldInitialization, MpId, SecBootMode, (VOID*)(PcdGet32(PcdCPUCoresSecMonStackBase) + (PcdGet32(PcdCPUCoreSecMonStackSize) * (GET_CORE_POS(MpId) + 1))));
+ } else {
+ if (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore)) {
+ SerialPrint ("Trust Zone Configuration is disabled\n\r");
+ }
+
+ // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
+ // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
+ // Status Register as the the current one (CPSR).
+ copy_cpsr_into_spsr ();
+
+ // Call the Platform specific function to execute additional actions if required
+ JumpAddress = PcdGet32 (PcdFvBaseAddress);
+ ArmPlatformSecExtraAction (MpId, &JumpAddress);
+
+ NonTrustedWorldTransition (MpId, JumpAddress);
+ }
+ ASSERT (0); // We must never return from the above function
+}
+
+VOID
+TrustedWorldInitialization (
+ IN UINTN MpId,
+ IN UINTN SecBootMode
+ )
+{
+ UINTN JumpAddress;
+
+ //-------------------- Monitor Mode ---------------------
+
+ // Set up Monitor World (Vector Table, etc)
+ ArmSecureMonitorWorldInitialize ();
+
+ // Transfer the interrupt to Non-secure World
+ ArmGicSetupNonSecure (MpId, PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));
+
+ // Initialize platform specific security policy
+ ArmPlatformSecTrustzoneInit (MpId);
+
+ // Setup the Trustzone Chipsets
+ if (SecBootMode == ARM_SEC_COLD_BOOT) {
+ if (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore)) {
+ if (ArmIsMpCore()) {
+ // Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)
+ ArmCallSEV ();
+ }
+ } else {
+ // The secondary cores need to wait until the Trustzone chipsets configuration is done
+ // before switching to Non Secure World
+
+ // Wait for the Primary Core to finish the initialization of the Secure World (event: EVENT_SECURE_INIT)
+ ArmCallWFE ();
+ }
+ }
+
+ // Call the Platform specific function to execute additional actions if required
+ JumpAddress = PcdGet32 (PcdFvBaseAddress);
+ ArmPlatformSecExtraAction (MpId, &JumpAddress);
+
+ // Write to CP15 Non-secure Access Control Register
+ ArmWriteNsacr (PcdGet32 (PcdArmNsacr));
+
+ /* set SMP bit */
+ ArmWriteAuxCr(ArmReadAuxCr() | BIT6);
+
+ // CP15 Secure Configuration Register
+ ArmWriteScr (PcdGet32 (PcdArmScr));
+
+ NonTrustedWorldTransition (MpId, JumpAddress);
+}
+
+VOID
+NonTrustedWorldTransition (
+ IN UINTN MpId,
+ IN UINTN JumpAddress
+ )
+{
+ // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition
+ // By not set, the mode for Non Secure World is SVC
+ if (PcdGet32 (PcdArmNonSecModeTransition) != 0) {
+ set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition));
+ }
+
+ return_from_exception (JumpAddress);
+ //-------------------- Non Secure Mode ---------------------
+
+ // PEI Core should always load and never return
+ ASSERT (FALSE);
+}
diff --git a/HisiPkg/D01BoardPkg/Sec/Sec/Sec.inf b/HisiPkg/D01BoardPkg/Sec/Sec/Sec.inf new file mode 100644 index 000000000..edb3d039b --- /dev/null +++ b/HisiPkg/D01BoardPkg/Sec/Sec/Sec.inf @@ -0,0 +1,83 @@ +#/** @file
+# SEC - Reset vector code that jumps to C and loads DXE core
+#
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmPlatformSec
+ FILE_GUID = c536bbfe-c813-4e48-9f90-01fe1ecf9d54
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+
+[Sources]
+ Sec.c
+
+[Sources.ARM]
+ Arm/Arch.c
+ Arm/Helper.asm | RVCT
+ Arm/Helper.S | GCC
+ Arm/SecEntryPoint.S | GCC
+ Arm/SecEntryPoint.asm | RVCT
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+ ArmCpuLib
+ ArmLib
+ ArmPlatformSecLib
+ ArmTrustedMonitorLib
+ BaseLib
+ DebugLib
+ DebugAgentLib
+ IoLib
+ ArmGicLib
+ PrintLib
+ SerialPortLib
+
+[FeaturePcd]
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+
+ gArmTokenSpaceGuid.PcdTrustzoneSupport
+ gArmTokenSpaceGuid.PcdVFPEnabled
+
+ gArmTokenSpaceGuid.PcdArmScr
+ gArmTokenSpaceGuid.PcdArmNsacr
+ gArmTokenSpaceGuid.PcdArmNonSecModeTransition
+
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+ gArmTokenSpaceGuid.PcdSecureFvBaseAddress
+ gArmTokenSpaceGuid.PcdSecureFvSize
+
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize
+
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+ gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize
diff --git a/HisiPkg/D01BoardPkg/Sec/Sec/SecInternal.h b/HisiPkg/D01BoardPkg/Sec/Sec/SecInternal.h new file mode 100644 index 000000000..856fb0a10 --- /dev/null +++ b/HisiPkg/D01BoardPkg/Sec/Sec/SecInternal.h @@ -0,0 +1,84 @@ +/** @file
+* Main file supporting the SEC Phase on ARM PLatforms
+*
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+* Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __SEC_H__
+#define __SEC_H__
+
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/ArmCpuLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/ArmPlatformSecLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)
+
+VOID
+TrustedWorldInitialization (
+ IN UINTN MpId,
+ IN UINTN SecBootMode
+ );
+
+VOID
+NonTrustedWorldTransition (
+ IN UINTN MpId,
+ IN UINTN JumpAddress
+ );
+
+VOID
+ArmSetupGicNonSecure (
+ IN INTN GicDistributorBase,
+ IN INTN GicInterruptInterfaceBase
+);
+
+VOID
+enter_monitor_mode (
+ IN UINTN MonitorEntryPoint,
+ IN UINTN MpId,
+ IN UINTN SecBootMode,
+ IN VOID* MonitorStackBase
+ );
+
+VOID
+return_from_exception (
+ IN UINTN NonSecureBase
+ );
+
+VOID
+copy_cpsr_into_spsr (
+ VOID
+ );
+
+VOID
+set_non_secure_mode (
+ IN ARM_PROCESSOR_MODE Mode
+ );
+
+VOID
+SecCommonExceptionEntry (
+ IN UINT32 Entry,
+ IN UINTN LR
+ );
+
+VOID
+EFIAPI
+ArmSecArchTrustzoneInit (
+ VOID
+ );
+
+#endif
diff --git a/HisiPkg/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf b/HisiPkg/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf new file mode 100644 index 000000000..22ee49c09 --- /dev/null +++ b/HisiPkg/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf @@ -0,0 +1,38 @@ +##
+#/** @file
+# AtaAtapiPassThru driver to provide native IDE/AHCI mode support.
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AtaAtapiPassThruDxe
+ FILE_GUID = 5E523CB4-D397-4986-87BD-A6DD8B22F455
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InitializeAtaAtapiPassThru
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+# DRIVER_BINDING = gAtaAtapiPassThruDriverBinding
+# COMPONENT_NAME = gAtaAtapiPassThruComponentName
+# COMPONENT_NAME2 = gAtaAtapiPassThruComponentName2
+#
+#
+[Binaries.common]
+ PE32|AtaAtapiPassThruDxe.efi|*
+
+
diff --git a/HisiPkg/Drivers/AtaAtapiPassThru/AtaAtapiPassThruDxe.efi b/HisiPkg/Drivers/AtaAtapiPassThru/AtaAtapiPassThruDxe.efi Binary files differnew file mode 100755 index 000000000..258f42766 --- /dev/null +++ b/HisiPkg/Drivers/AtaAtapiPassThru/AtaAtapiPassThruDxe.efi diff --git a/HisiPkg/Drivers/FlashDriver/FlashDriver.depex b/HisiPkg/Drivers/FlashDriver/FlashDriver.depex new file mode 100644 index 000000000..2a47cc229 --- /dev/null +++ b/HisiPkg/Drivers/FlashDriver/FlashDriver.depex @@ -0,0 +1 @@ +
\ No newline at end of file diff --git a/HisiPkg/Drivers/FlashDriver/FlashDriver.efi b/HisiPkg/Drivers/FlashDriver/FlashDriver.efi Binary files differnew file mode 100644 index 000000000..85f7b47ef --- /dev/null +++ b/HisiPkg/Drivers/FlashDriver/FlashDriver.efi diff --git a/HisiPkg/Drivers/FlashDriver/FlashDriver.inf b/HisiPkg/Drivers/FlashDriver/FlashDriver.inf new file mode 100644 index 000000000..46067c9c0 --- /dev/null +++ b/HisiPkg/Drivers/FlashDriver/FlashDriver.inf @@ -0,0 +1,32 @@ +#/** @file
+# Component name for module FlashDriver
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = FlashDriver
+ FILE_GUID = E29977F9-20A4-4551-B0EC-BCE246592E72
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeFlash
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+[Binaries.common]
+ DXE_DEPEX|FlashDriver.depex
+ PE32|FlashDriver.efi|*
+
diff --git a/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01Gic.c b/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01Gic.c new file mode 100644 index 000000000..5f9025057 --- /dev/null +++ b/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01Gic.c @@ -0,0 +1,41 @@ +/** @file
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/ArmGicLib.h>
+#include <Library/PcdLib.h>
+
+UINTN
+EFIAPI
+ArmGicGetMaxNumInterrupts (
+ IN INTN GicDistributorBase
+ )
+{
+ return 32 * ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F) + 1);
+}
+
+VOID
+EFIAPI
+ArmGicSendSgiTo (
+ IN INTN GicDistributorBase,
+ IN INTN TargetListFilter,
+ IN INTN CPUTargetList,
+ IN INTN SgiId
+ )
+{
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16) | SgiId);
+}
+
diff --git a/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicDxe.c b/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicDxe.c new file mode 100644 index 000000000..a4dfa66d3 --- /dev/null +++ b/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicDxe.c @@ -0,0 +1,425 @@ +/*++
+
+Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
+Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
+Portions copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
+Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+ Gic.c
+
+Abstract:
+
+ Driver implementing the GIC interrupt controller protocol
+
+--*/
+
+#include <PiDxe.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/ArmGicLib.h>
+
+#include <Protocol/Cpu.h>
+#include <Protocol/HardwareInterrupt.h>
+
+#define ARM_GIC_DEFAULT_PRIORITY 0x80
+
+extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;
+
+//
+// Notifications
+//
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+
+// Maximum Number of Interrupts
+UINTN mGicNumInterrupts = 0;
+
+HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;
+
+/**
+ Register Handler for the specified interrupt source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+ @param Handler Callback for interrupt. NULL to unregister
+
+ @retval EFI_SUCCESS Source was updated to support Handler.
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.
+
+**/
+EFI_STATUS
+EFIAPI
+RegisterInterruptSource (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN HARDWARE_INTERRUPT_HANDLER Handler
+ )
+{
+ if (Source > mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {
+ return EFI_ALREADY_STARTED;
+ }
+
+ gRegisteredInterruptHandlers[Source] = Handler;
+
+ // If the interrupt handler is unregistered then disable the interrupt
+ if (NULL == Handler){
+ return This->DisableInterruptSource (This, Source);
+ } else {
+ return This->EnableInterruptSource (This, Source);
+ }
+}
+
+/**
+ Enable interrupt source Source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+
+ @retval EFI_SUCCESS Source interrupt enabled.
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.
+
+**/
+EFI_STATUS
+EFIAPI
+EnableInterruptSource (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
+ )
+{
+ UINT32 RegOffset;
+ UINTN RegShift;
+
+ if (Source > mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ // Calculate enable register offset and bit position
+ RegOffset = Source / 32;
+ RegShift = Source % 32;
+
+ // Write set-enable register
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Disable interrupt source Source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+
+ @retval EFI_SUCCESS Source interrupt disabled.
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.
+
+**/
+EFI_STATUS
+EFIAPI
+DisableInterruptSource (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
+ )
+{
+ UINT32 RegOffset;
+ UINTN RegShift;
+
+ if (Source > mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ // Calculate enable register offset and bit position
+ RegOffset = Source / 32;
+ RegShift = Source % 32;
+
+ // Write set-enable register
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Return current state of interrupt source Source.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+ @param InterruptState TRUE: source enabled, FALSE: source disabled.
+
+ @retval EFI_SUCCESS InterruptState is valid
+ @retval EFI_DEVICE_ERROR InterruptState is not valid
+
+**/
+EFI_STATUS
+EFIAPI
+GetInterruptSourceState (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN BOOLEAN *InterruptState
+ )
+{
+ UINT32 RegOffset;
+ UINTN RegShift;
+
+ if (Source > mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ // calculate enable register offset and bit position
+ RegOffset = Source / 32;
+ RegShift = Source % 32;
+
+ if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
+ *InterruptState = FALSE;
+ } else {
+ *InterruptState = TRUE;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Signal to the hardware that the End Of Intrrupt state
+ has been reached.
+
+ @param This Instance pointer for this protocol
+ @param Source Hardware source of the interrupt
+
+ @retval EFI_SUCCESS Source interrupt EOI'ed.
+ @retval EFI_DEVICE_ERROR Hardware could not be programmed.
+
+**/
+EFI_STATUS
+EFIAPI
+EndOfInterrupt (
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
+ )
+{
+ if (Source > mGicNumInterrupts) {
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, Source);
+ return EFI_SUCCESS;
+}
+
+/**
+ EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.
+
+ @param InterruptType Defines the type of interrupt or exception that
+ occurred on the processor.This parameter is processor architecture specific.
+ @param SystemContext A pointer to the processor context when
+ the interrupt occurred on the processor.
+
+ @return None
+
+**/
+VOID
+EFIAPI
+IrqInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ UINT32 GicInterrupt;
+ HARDWARE_INTERRUPT_HANDLER InterruptHandler;
+
+ GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR);
+
+ // Special Interrupts (ID1020-ID1023) have an Interrupt ID greater than the number of interrupt (ie: Spurious interrupt).
+ if (GicInterrupt >= mGicNumInterrupts) {
+ // The special interrupt do not need to be acknowledge
+ return;
+ }
+
+ InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
+ if (InterruptHandler != NULL) {
+ // Call the registered interrupt handler.
+ InterruptHandler (GicInterrupt, SystemContext);
+ } else {
+ DEBUG ((EFI_D_ERROR, "Spurious GIC interrupt: 0x%x\n", GicInterrupt));
+ }
+
+ EndOfInterrupt (&gHardwareInterruptProtocol, GicInterrupt);
+}
+
+//
+// Making this global saves a few bytes in image size
+//
+EFI_HANDLE gHardwareInterruptHandle = NULL;
+
+//
+// The protocol instance produced by this driver
+//
+EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {
+ RegisterInterruptSource,
+ EnableInterruptSource,
+ DisableInterruptSource,
+ GetInterruptSourceState,
+ EndOfInterrupt
+};
+
+/**
+ Shutdown our hardware
+
+ DXE Core will disable interrupts and turn off the timer and disable interrupts
+ after all the event handlers have run.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+ExitBootServicesEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ UINTN Index;
+
+ // Acknowledge all pending interrupts
+ for (Index = 0; Index < mGicNumInterrupts; Index++) {
+ DisableInterruptSource (&gHardwareInterruptProtocol, Index);
+ }
+
+ for (Index = 0; Index < mGicNumInterrupts; Index++) {
+ EndOfInterrupt (&gHardwareInterruptProtocol, Index);
+ }
+
+ // Disable Gic Interface
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0);
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0);
+
+ // Disable Gic Distributor
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0);
+}
+
+/**
+ Initialize the state information for the CPU Architectural Protocol
+
+ @param ImageHandle of the loaded driver
+ @param SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Protocol registered
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Hardware problems
+
+**/
+EFI_STATUS
+InterruptDxeInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ UINT32 RegOffset;
+ UINTN RegShift;
+ EFI_CPU_ARCH_PROTOCOL *Cpu;
+ UINT32 CpuTarget;
+
+ // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0
+ DEBUG_CODE_BEGIN();
+ if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {
+ DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));
+ }
+ DEBUG_CODE_END();
+
+ // Make sure the Interrupt Controller Protocol is not already installed in the system.
+ ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
+
+ mGicNumInterrupts = ArmGicGetMaxNumInterrupts (PcdGet32(PcdGicDistributorBase));
+
+ for (Index = 0; Index < mGicNumInterrupts; Index++) {
+ DisableInterruptSource (&gHardwareInterruptProtocol, Index);
+
+ // Set Priority
+ RegOffset = Index / 4;
+ RegShift = (Index % 4) * 8;
+ MmioAndThenOr32 (
+ PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),
+ ~(0xff << RegShift),
+ ARM_GIC_DEFAULT_PRIORITY << RegShift
+ );
+ }
+ // Configure interrupts for Primary Cpu
+ CpuTarget = (1 << PcdGet32 (PcdGicPrimaryCoreId));
+ CpuTarget |= CpuTarget << 16;
+ for (Index = 0; Index < (mGicNumInterrupts / 2); Index++) {
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), CpuTarget);
+ }
+
+ // Set binary point reg to 0x7 (no preemption)
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);
+
+ // Set priority mask reg to 0xff to allow all priorities through
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);
+
+ // Enable gic cpu interface
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);
+
+ // Enable gic distributor
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);
+
+ // Initialize the array for the Interrupt Handlers
+ gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &gHardwareInterruptHandle,
+ &gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Get the CPU protocol that this driver requires.
+ //
+ Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
+ ASSERT_EFI_ERROR(Status);
+
+ //
+ // Unregister the default exception handler.
+ //
+ Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);
+ ASSERT_EFI_ERROR(Status);
+
+ //
+ // Register to receive interrupts
+ //
+ Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);
+ ASSERT_EFI_ERROR(Status);
+
+ // Register for an ExitBootServicesEvent
+ Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicDxe.inf b/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicDxe.inf new file mode 100644 index 000000000..6ade9e63a --- /dev/null +++ b/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicDxe.inf @@ -0,0 +1,59 @@ +#/** @file
+#
+# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>
+# Copyright Huawei Technologies Co., Ltd. 1998-2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = HisiliconD01GicDxe
+ FILE_GUID = DE371F7C-DEC4-4D21-ADF1-593ABCC15882
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InterruptDxeInitialize
+
+
+[Sources.common]
+ HisiliconD01Gic.c
+ HisiliconD01GicDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ HisiPkg/HisiPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ UefiLib
+ UefiBootServicesTableLib
+ DebugLib
+ PrintLib
+ MemoryAllocationLib
+ UefiDriverEntryPoint
+ IoLib
+
+[Protocols]
+ gHardwareInterruptProtocolGuid
+ gEfiCpuArchProtocolGuid
+
+[FixedPcd.common]
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+ gHwTokenSpaceGuid.PcdGicPrimaryCoreId
+
+[Depex]
+ gEfiCpuArchProtocolGuid
diff --git a/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicLib.inf b/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicLib.inf new file mode 100644 index 000000000..6d6c66fdc --- /dev/null +++ b/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicLib.inf @@ -0,0 +1,32 @@ +#/* @file
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = HisiliconD01GicLib
+ FILE_GUID = 03d05ee4-cdeb-458c-9dfc-993f09bdf405
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmGicLib
+
+[Sources]
+ HisiliconD01Gic.c
+ HisiliconD01GicNonSec.c
+
+[LibraryClasses]
+ IoLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdePkg/MdePkg.dec
diff --git a/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicNonSec.c b/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicNonSec.c new file mode 100644 index 000000000..17a2cd1cb --- /dev/null +++ b/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicNonSec.c @@ -0,0 +1,45 @@ +/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/ArmGicLib.h>
+
+
+VOID
+EFIAPI
+ArmGicEnableInterruptInterface (
+ IN INTN GicInterruptInterfaceBase
+ )
+{
+ /*
+ * Enable the CPU interface in Non-Secure world
+ * Note: The ICCICR register is banked when Security extensions are implemented
+ */
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);
+}
+
+VOID
+EFIAPI
+ArmGicEnableDistributor (
+ IN INTN GicDistributorBase
+ )
+{
+ /*
+ * Enable GIC distributor in Non-Secure world.
+ * Note: The ICDDCR register is banked when Security extensions are implemented
+ */
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
+}
diff --git a/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicSec.c b/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicSec.c new file mode 100644 index 000000000..d097b8a45 --- /dev/null +++ b/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicSec.c @@ -0,0 +1,132 @@ +/** @file
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/ArmGicLib.h>
+
+/*
+ * This function configures the all interrupts to be Non-secure.
+ *
+ */
+VOID
+EFIAPI
+ArmGicSetupNonSecure (
+ IN UINTN MpId,
+ IN INTN GicDistributorBase,
+ IN INTN GicInterruptInterfaceBase
+ )
+{
+ UINTN InterruptId;
+ UINTN CachedPriorityMask;
+ UINTN Index;
+
+ CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
+
+ // Set priority Mask so that no interrupts get through to CPU
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
+
+ // Check if there are any pending interrupts
+ //TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.
+ while(0 != (MmioRead32 (GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
+ // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
+ InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
+
+ // Write to End of interrupt signal
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
+ }
+
+ // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).
+ if (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore)) {
+ // Ensure all GIC interrupts are Non-Secure
+ for (Index = 0; Index < (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32); Index++) {
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
+ }
+ } else {
+ // The secondary cores only set the Non Secure bit to their banked PPIs
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);
+ }
+
+ // Ensure all interrupts can get through the priority mask
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
+}
+
+/*
+ * This function configures the interrupts set by the mask to be secure.
+ *
+ */
+VOID
+EFIAPI
+ArmGicSetSecureInterrupts (
+ IN UINTN GicDistributorBase,
+ IN UINTN* GicSecureInterruptMask,
+ IN UINTN GicSecureInterruptMaskSize
+ )
+{
+ UINTN Index;
+ UINT32 InterruptStatus;
+
+ // We must not have more interrupts defined by the mask than the number of available interrupts
+ ASSERT(GicSecureInterruptMaskSize <= (ArmGicGetMaxNumInterrupts (GicDistributorBase) / 32));
+
+ // Set all the interrupts defined by the mask as Secure
+ for (Index = 0; Index < GicSecureInterruptMaskSize; Index++) {
+ InterruptStatus = MmioRead32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4));
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), InterruptStatus & (~GicSecureInterruptMask[Index]));
+ }
+}
+
+VOID
+EFIAPI
+ArmGicEnableInterruptInterface (
+ IN INTN GicInterruptInterfaceBase
+ )
+{
+ // Set Priority Mask to allow interrupts
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
+
+ // Enable CPU interface in Secure world
+ // Enable CPU interface in Non-secure World
+ // Signal Secure Interrupts to CPU using FIQ line *
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
+ ARM_GIC_ICCICR_ENABLE_SECURE |
+ ARM_GIC_ICCICR_ENABLE_NS |
+ ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
+}
+
+VOID
+EFIAPI
+ArmGicDisableInterruptInterface (
+ IN INTN GicInterruptInterfaceBase
+ )
+{
+ UINT32 ControlValue;
+
+ // Disable CPU interface in Secure world and Non-secure World
+ ControlValue = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR);
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, ControlValue & ~(ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_NS));
+}
+
+VOID
+EFIAPI
+ArmGicEnableDistributor (
+ IN INTN GicDistributorBase
+ )
+{
+ // Turn on the GIC distributor
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
+}
diff --git a/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicSecLib.inf b/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicSecLib.inf new file mode 100644 index 000000000..07a16a415 --- /dev/null +++ b/HisiPkg/Drivers/HisiliconD01Gic/HisiliconD01GicSecLib.inf @@ -0,0 +1,41 @@ +#/* @file
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = HisiliconD01GicSecLib
+ FILE_GUID = 85f3cf80-b5f4-11df-9855-0002a5d5c51b
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmGicLib
+
+[Sources]
+ HisiliconD01Gic.c
+ HisiliconD01GicSec.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+ ArmLib
+ DebugLib
+ IoLib
+ PcdLib
+
+[FixedPcd.common]
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
diff --git a/HisiPkg/Drivers/LinuxAtagList/LinuxAtagList.c b/HisiPkg/Drivers/LinuxAtagList/LinuxAtagList.c new file mode 100644 index 000000000..8c526846e --- /dev/null +++ b/HisiPkg/Drivers/LinuxAtagList/LinuxAtagList.c @@ -0,0 +1,309 @@ +/** @file
+ Timer Architecture Protocol driver of the ARM flavor
+
+ Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include "Protocol/LinuxAtagListProtocol.h"
+#include <Library/PcdLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Protocol/NorFlashProtocol.h>
+
+#define LINUX_ATAG_FLASH_OFFSET 0x1200000
+#define LINUX_ATAG_FLASH_SIZE 0x1000
+
+#define LINUX_ATAG_MAGIC_FLAG 0x01
+#define INITRD_OFFSET 0x40
+#define INITRD_SIZE_OFFSET 0x0c
+
+typedef struct{
+ UINT32 MagicFlag;
+ UINT32 Checksum;
+ LINUX_ATAG_LIST LinuxAtagList;
+}LINUX_ATAG_FLASH_DATA;
+
+
+VOID GetDefaultLinuxAtag(
+ IN OUT LINUX_ATAG_LIST *LinuxAtagList
+)
+{
+ LinuxAtagList->core_tag.flags = PcdGet32(PcdDefaultCoreTagFlags);
+ LinuxAtagList->core_tag.pagesize = PcdGet32(PcdDefaultCoreTagPageSize);
+ LinuxAtagList->core_tag.rootdev = PcdGet32(PcdDefaultCoreTagRootdev);
+
+ LinuxAtagList->mem_tag.start = PcdGet32(PcdDefaultMemTagStart);
+ LinuxAtagList->mem_tag.size = PcdGet32(PcdDefaultMemTagSize);
+
+ LinuxAtagList->initrd2_tag.start = PcdGet32(PcdtinitrdStart) + INITRD_OFFSET;
+ LinuxAtagList->initrd2_tag.size = SwapBytes32(*(volatile UINT32*)(PcdGet32(PcdtinitrdStart) + INITRD_SIZE_OFFSET));
+
+ (VOID)AsciiStrCpy(LinuxAtagList->cmdline_tag.cmdline, (CHAR8*)PcdGetPtr(PcdDefaultCmdlineTagCmdline));
+
+ LinuxAtagList->bootcmd_tag.addr = PcdGet32(PcdBootcmdAddr);
+ LinuxAtagList->cpuinfo_tag.invalid = 0xffffffff;
+
+#if 0
+ DEBUG((EFI_D_ERROR, "core_tag.flags = 0x%08x \n", LinuxAtagList->core_tag.flags));
+ DEBUG((EFI_D_ERROR, "core_tag.pagesize = 0x%08x \n", LinuxAtagList->core_tag.pagesize));
+ DEBUG((EFI_D_ERROR, "core_tag.rootdev = 0x%08x \n", LinuxAtagList->core_tag.rootdev));
+
+ DEBUG((EFI_D_ERROR, "mem_tag.start = 0x%08x \n", LinuxAtagList->mem_tag.start));
+ DEBUG((EFI_D_ERROR, "mem_tag.size = 0x%08x \n", LinuxAtagList->mem_tag.size));
+
+ DEBUG((EFI_D_ERROR, "initrd2_tag.start = 0x%08x \n", LinuxAtagList->initrd2_tag.start));
+ //DEBUG((EFI_D_ERROR, "initrd2_tag.size = 0x%08x \n", SwapBytes32(LinuxAtagList->initrd2_tag.size)));
+ DEBUG((EFI_D_ERROR, "initrd2_tag.size come from initrd file, now can not be gotten \n"));
+
+ DEBUG((EFI_D_ERROR, "cmdline_tag.cmdline = %a \n", LinuxAtagList->cmdline_tag.cmdline));
+ DEBUG((EFI_D_ERROR, "bootcmd_tag.addr = %a \n", LinuxAtagList->bootcmd_tag.addr));
+ DEBUG((EFI_D_ERROR, "cpuinfo_tag.invalid = %a \n", LinuxAtagList->cpuinfo_tag.invalid));
+#endif
+}
+
+EFI_STATUS
+GetLinuxAtag(
+ IN LINUX_ATAG_LIST_PROTOCOL *This,
+ IN OUT LINUX_ATAG_LIST *LinuxAtagList
+ )
+{
+ EFI_STATUS Status;
+ UNI_NOR_FLASH_PROTOCOL *Flash;
+ LINUX_ATAG_FLASH_DATA *FlashData;
+
+ //load Flash Protocol
+ Status = gBS->LocateProtocol (&gUniNorFlashProtocolGuid, NULL, (VOID **) &Flash);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "Locate gOemFlashDriverProtocolGuid Error, Status = %r\n", Status));
+ goto ERROR;
+ }
+ else
+ {
+ Status = gBS->AllocatePool (
+ EfiBootServicesData,
+ LINUX_ATAG_FLASH_SIZE,
+ (VOID**) &FlashData
+ );
+ if (NULL == FlashData)
+ {
+ DEBUG((EFI_D_ERROR, "AllocatePool Error, Status = %r\n", Status));
+ goto ERROR;
+ }
+ else
+ {
+ Status = Flash->Read(Flash, LINUX_ATAG_FLASH_OFFSET, (UINT8 *)FlashData, sizeof(LINUX_ATAG_FLASH_DATA));
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "flashRead Error, Status = %r\n", Status));
+ if (NULL != FlashData)
+ {
+ (VOID)gBS->FreePool(FlashData);
+ }
+ goto ERROR;
+ }
+ else
+ {
+ #if 0
+ DEBUG((EFI_D_ERROR, "core_tag.flags = 0x%08x \n", FlashData->LinuxAtagList.core_tag.flags));
+ DEBUG((EFI_D_ERROR, "core_tag.pagesize = 0x%08x \n", FlashData->LinuxAtagList.core_tag.pagesize));
+ DEBUG((EFI_D_ERROR, "core_tag.rootdev = 0x%08x \n", FlashData->LinuxAtagList.core_tag.rootdev));
+
+ DEBUG((EFI_D_ERROR, "mem_tag.start = 0x%08x \n", FlashData->LinuxAtagList.mem_tag.start));
+ DEBUG((EFI_D_ERROR, "mem_tag.size = 0x%08x \n", FlashData->LinuxAtagList.mem_tag.size));
+
+ DEBUG((EFI_D_ERROR, "initrd2_tag.start = 0x%08x \n", FlashData->LinuxAtagList.initrd2_tag.start));
+ //DEBUG((EFI_D_ERROR, "initrd2_tag.size = 0x%08x \n", SwapBytes32(LinuxAtagList->initrd2_tag.size)));
+ DEBUG((EFI_D_ERROR, "initrd2_tag.size come from initrd file, now can not be gotten \n"));
+
+ DEBUG((EFI_D_ERROR, "cmdline_tag.cmdline = %a \n", FlashData->LinuxAtagList.cmdline_tag.cmdline));
+ #endif
+ if ((LINUX_ATAG_MAGIC_FLAG == FlashData->MagicFlag) && (FlashData->Checksum == CalculateCheckSum32((CONST UINT32*)&(FlashData->LinuxAtagList), sizeof(LINUX_ATAG_LIST))))
+ {
+ gBS->CopyMem(LinuxAtagList, &(FlashData->LinuxAtagList), sizeof(LINUX_ATAG_LIST));
+
+ #if 0
+ DEBUG((EFI_D_ERROR, "!!!!!!!!!!!!!!!!!!\n"));
+ DEBUG((EFI_D_ERROR, "core_tag.flags = 0x%08x \n", FlashData->LinuxAtagList.core_tag.flags));
+ DEBUG((EFI_D_ERROR, "core_tag.pagesize = 0x%08x \n", FlashData->LinuxAtagList.core_tag.pagesize));
+ DEBUG((EFI_D_ERROR, "core_tag.rootdev = 0x%08x \n", FlashData->LinuxAtagList.core_tag.rootdev));
+
+ DEBUG((EFI_D_ERROR, "mem_tag.start = 0x%08x \n", FlashData->LinuxAtagList.mem_tag.start));
+ DEBUG((EFI_D_ERROR, "mem_tag.size = 0x%08x \n", FlashData->LinuxAtagList.mem_tag.size));
+
+ DEBUG((EFI_D_ERROR, "initrd2_tag.start = 0x%08x \n", FlashData->LinuxAtagList.initrd2_tag.start));
+ //DEBUG((EFI_D_ERROR, "initrd2_tag.size = 0x%08x \n", SwapBytes32(LinuxAtagList->initrd2_tag.size)));
+ DEBUG((EFI_D_ERROR, "initrd2_tag.size come from initrd file, now can not be gotten \n"));
+
+ DEBUG((EFI_D_ERROR, "cmdline_tag.cmdline = %a \n", FlashData->LinuxAtagList.cmdline_tag.cmdline));
+ DEBUG((EFI_D_ERROR, "@@@@@@@@@@@@@@@@@@@@\n"));
+ #endif
+ #if 0
+ DEBUG((EFI_D_ERROR, "core_tag.flags = 0x%08x \n", LinuxAtagList->core_tag.flags));
+ DEBUG((EFI_D_ERROR, "core_tag.pagesize = 0x%08x \n", LinuxAtagList->core_tag.pagesize));
+ DEBUG((EFI_D_ERROR, "core_tag.rootdev = 0x%08x \n", LinuxAtagList->core_tag.rootdev));
+
+ DEBUG((EFI_D_ERROR, "mem_tag.start = 0x%08x \n", LinuxAtagList->mem_tag.start));
+ DEBUG((EFI_D_ERROR, "mem_tag.size = 0x%08x \n", LinuxAtagList->mem_tag.size));
+
+ DEBUG((EFI_D_ERROR, "initrd2_tag.start = 0x%08x \n", LinuxAtagList->initrd2_tag.start));
+ //DEBUG((EFI_D_ERROR, "initrd2_tag.size = 0x%08x \n", SwapBytes32(LinuxAtagList->initrd2_tag.size)));
+ DEBUG((EFI_D_ERROR, "initrd2_tag.size come from initrd file, now can not be gotten \n"));
+
+ DEBUG((EFI_D_ERROR, "cmdline_tag.cmdline = %a \n", LinuxAtagList->cmdline_tag.cmdline));
+ //DEBUG((EFI_D_ERROR, "#########################\n"));
+ #endif
+ if (NULL != FlashData)
+ {
+ (VOID)gBS->FreePool(FlashData);
+ }
+ return EFI_SUCCESS;
+ }
+ else
+ {
+ if (NULL != FlashData)
+ {
+ (VOID)gBS->FreePool(FlashData);
+ }
+ goto ERROR;
+ }
+ }
+ }
+ }
+
+ERROR:
+ DEBUG((EFI_D_ERROR, "Get default linux atag list\n"));
+ GetDefaultLinuxAtag(LinuxAtagList);
+ DEBUG((EFI_D_ERROR, "Get default linux atag list ok!\n"));
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+SetLinuxAtag(
+ IN LINUX_ATAG_LIST_PROTOCOL *This,
+ IN LINUX_ATAG_LIST *LinuxAtagList
+ )
+{
+ EFI_STATUS Status;
+ UNI_NOR_FLASH_PROTOCOL *Flash;
+ LINUX_ATAG_FLASH_DATA *FlashData;
+
+ //load Flash Protocol
+ Status = gBS->LocateProtocol (&gUniNorFlashProtocolGuid, NULL, (VOID **) &Flash);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "Locate gUniNorFlashProtocolGuid Error, Status = %r\n", Status));
+ return Status;
+ }
+ else
+ {
+
+ Status = gBS->AllocatePool (
+ EfiBootServicesData,
+ LINUX_ATAG_FLASH_SIZE,
+ (VOID**) &FlashData
+ );
+ if (NULL == FlashData)
+ {
+ DEBUG((EFI_D_ERROR, "AllocatePool Error, Status = %r\n", Status));
+ return Status;
+ }
+ else
+ {
+ (VOID)ZeroMem(FlashData, LINUX_ATAG_FLASH_SIZE);
+
+ FlashData->MagicFlag = LINUX_ATAG_MAGIC_FLAG;
+ FlashData->Checksum = CalculateCheckSum32((CONST UINT32*)LinuxAtagList, sizeof(LINUX_ATAG_LIST));
+ gBS->CopyMem(&(FlashData->LinuxAtagList), LinuxAtagList, sizeof(LINUX_ATAG_LIST));
+
+ #if 0
+ DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+ DEBUG((EFI_D_ERROR, "core_tag.flags = 0x%08x \n", LinuxAtagList->core_tag.flags));
+ DEBUG((EFI_D_ERROR, "core_tag.pagesize = 0x%08x \n", LinuxAtagList->core_tag.pagesize));
+ DEBUG((EFI_D_ERROR, "core_tag.rootdev = 0x%08x \n", LinuxAtagList->core_tag.rootdev));
+
+ DEBUG((EFI_D_ERROR, "mem_tag.start = 0x%08x \n", LinuxAtagList->mem_tag.start));
+ DEBUG((EFI_D_ERROR, "mem_tag.size = 0x%08x \n", LinuxAtagList->mem_tag.size));
+
+ DEBUG((EFI_D_ERROR, "initrd2_tag.start = 0x%08x \n", LinuxAtagList->initrd2_tag.start));
+ //DEBUG((EFI_D_ERROR, "initrd2_tag.size = 0x%08x \n", SwapBytes32(LinuxAtagList->initrd2_tag.size)));
+ DEBUG((EFI_D_ERROR, "initrd2_tag.size come from initrd file, now can not be gotten \n"));
+
+ DEBUG((EFI_D_ERROR, "cmdline_tag.cmdline = %a \n", LinuxAtagList->cmdline_tag.cmdline));
+ #endif
+ Status = Flash->Write(Flash, LINUX_ATAG_FLASH_OFFSET, (UINT8 *)FlashData, sizeof(LINUX_ATAG_FLASH_DATA));
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((EFI_D_ERROR, "flashWrite LINUX_ATAG_LIST Error, Status = %r\n", Status));
+ }
+
+ #if 0
+ DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+ DEBUG((EFI_D_ERROR, "core_tag.flags = 0x%08x \n", FlashData->LinuxAtagList.core_tag.flags));
+ DEBUG((EFI_D_ERROR, "core_tag.pagesize = 0x%08x \n", FlashData->LinuxAtagList.core_tag.pagesize));
+ DEBUG((EFI_D_ERROR, "core_tag.rootdev = 0x%08x \n", FlashData->LinuxAtagList.core_tag.rootdev));
+
+ DEBUG((EFI_D_ERROR, "mem_tag.start = 0x%08x \n", FlashData->LinuxAtagList.mem_tag.start));
+ DEBUG((EFI_D_ERROR, "mem_tag.size = 0x%08x \n", FlashData->LinuxAtagList.mem_tag.size));
+
+ DEBUG((EFI_D_ERROR, "initrd2_tag.start = 0x%08x \n", FlashData->LinuxAtagList.initrd2_tag.start));
+ //DEBUG((EFI_D_ERROR, "initrd2_tag.size = 0x%08x \n", SwapBytes32(LinuxAtagList->initrd2_tag.size)));
+ DEBUG((EFI_D_ERROR, "initrd2_tag.size come from initrd file, now can not be gotten \n"));
+
+ DEBUG((EFI_D_ERROR, "cmdline_tag.cmdline = %a \n", FlashData->LinuxAtagList.cmdline_tag.cmdline));
+ #endif
+
+ if (NULL != FlashData)
+ {
+ (VOID)gBS->FreePool(FlashData);
+ }
+ return Status;
+ }
+ }
+}
+
+
+LINUX_ATAG_LIST_PROTOCOL mLinuxAtagListProtocol =
+{
+ GetLinuxAtag,
+ SetLinuxAtag
+};
+
+
+
+EFI_STATUS
+EFIAPI
+LinuxAtagListInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+
+ Status = gBS->InstallProtocolInterface(
+ &ImageHandle,
+ &gLinuxAtagListProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mLinuxAtagListProtocol
+ );
+ if (EFI_ERROR (Status))
+ {
+ DEBUG((EFI_D_ERROR, "Install gLinuxAtagListProtocolGuid %r \n", Status));
+ }
+
+ return Status;
+}
+
diff --git a/HisiPkg/Drivers/LinuxAtagList/LinuxAtagList.inf b/HisiPkg/Drivers/LinuxAtagList/LinuxAtagList.inf new file mode 100644 index 000000000..78293295f --- /dev/null +++ b/HisiPkg/Drivers/LinuxAtagList/LinuxAtagList.inf @@ -0,0 +1,68 @@ +#/** @file
+# Component name for module WatchdogDriver
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = LinuxAtagListInitialize
+ FILE_GUID = 49ea041e-6752-42ca-b0b1-4444333346b7
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = LinuxAtagListInitialize
+
+[Sources.common]
+ LinuxAtagList.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ HisiPkg/HisiPlatformPkg.dec
+
+[LibraryClasses]
+ ArmLib
+ BaseLib
+ UefiLib
+ UefiBootServicesTableLib
+ BaseMemoryLib
+ DebugLib
+ UefiDriverEntryPoint
+ BaseMemoryLib
+
+[Guids]
+
+[Protocols]
+ gLinuxAtagListProtocolGuid
+ gUniNorFlashProtocolGuid
+
+[Pcd]
+ gHwTokenSpaceGuid.PcdDefaultCoreTagFlags
+ gHwTokenSpaceGuid.PcdDefaultCoreTagPageSize
+ gHwTokenSpaceGuid.PcdDefaultCoreTagRootdev
+
+ gHwTokenSpaceGuid.PcdDefaultMemTagStart
+ gHwTokenSpaceGuid.PcdDefaultMemTagSize
+
+ #gHwTokenSpaceGuid.PcdDefaultInitrd2TagStart
+ #gHwTokenSpaceGuid.PcdDefaultInitrd2TagSize
+
+ gHwTokenSpaceGuid.PcduImageStart
+ gHwTokenSpaceGuid.PcdtinitrdStart
+ gHwTokenSpaceGuid.PcdBootcmdAddr
+
+ gHwTokenSpaceGuid.PcdDefaultCmdlineTagCmdline
+
+[Depex]
+ TRUE
+
diff --git a/HisiPkg/Drivers/NandFlash/NandDxe.depex b/HisiPkg/Drivers/NandFlash/NandDxe.depex new file mode 100644 index 000000000..2a47cc229 --- /dev/null +++ b/HisiPkg/Drivers/NandFlash/NandDxe.depex @@ -0,0 +1 @@ +
\ No newline at end of file diff --git a/HisiPkg/Drivers/NandFlash/NandDxe.efi b/HisiPkg/Drivers/NandFlash/NandDxe.efi Binary files differnew file mode 100644 index 000000000..d13ec8e57 --- /dev/null +++ b/HisiPkg/Drivers/NandFlash/NandDxe.efi diff --git a/HisiPkg/Drivers/NandFlash/NandFlashDxe.inf b/HisiPkg/Drivers/NandFlash/NandFlashDxe.inf new file mode 100644 index 000000000..c9faf56f0 --- /dev/null +++ b/HisiPkg/Drivers/NandFlash/NandFlashDxe.inf @@ -0,0 +1,26 @@ +#/** @file
+# Component name for module NandDxe
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = NandDxe
+ FILE_GUID = 811320E3-5B13-42a5-8EA5-6A1ED0922ADB
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeNANDFlash
+[Binaries.common]
+ DXE_DEPEX|NandDxe.depex
+ PE32|NandDxe.efi|*
+
diff --git a/HisiPkg/Drivers/TimerDxe/TimerDxe.c b/HisiPkg/Drivers/TimerDxe/TimerDxe.c new file mode 100644 index 000000000..5854a3656 --- /dev/null +++ b/HisiPkg/Drivers/TimerDxe/TimerDxe.c @@ -0,0 +1,557 @@ +/** @file
+ Timer Architecture Protocol driver of the ARM flavor
+
+ Copyright (c) 2011 ARM Ltd. All rights reserved.<BR>
+ Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#include <PiDxe.h>
+
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/ArmArchTimerLib.h>
+
+#include <Protocol/Timer.h>
+#include <Protocol/HardwareInterrupt.h>
+
+// The notification function to call on every timer interrupt.
+EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+
+// The current period of the timer interrupt
+UINT64 mTimerPeriod = 0;
+
+// Cached copy of the Hardware Interrupt protocol instance
+EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
+
+#define SRE_HITIMER_ADDR 0xe3000000
+
+#define SRE_HITIMER32_OFFSET (0x00000020)
+
+/****************** Timer32 register addresses offset start ***********************/
+#define SRE_HITIMER32_LOAD_OFFSET (0x0)
+#define SRE_HITIMER32_VALUE_OFFSET (0x4)
+#define SRE_HITIMER32_CNTL_OFFSET (0x8)
+#define SRE_HITIMER32_INTC_OFFSET (0xC)
+#define SRE_HITIMER32_RIS_OFFSET (0x10)
+#define SRE_HITIMER32_MIS_OFFSET (0x0014)
+#define SRE_HITIMER32_BGLOAD_OFFSET (0x18)
+/****************** end ******************************/
+
+#define SRE_HITIMER_NUM 48
+#define SRE_HITIMER64_START_INDEX 32
+#define SRE_HITIMER_ENCLK_SEL_BIT (1 << 7) /* Timer enable flag */
+
+
+#define SRE_HITIMER_CLK_IN_FREQ 187500000
+#define SRE_HITIMER_MICROSECOND_PER_SECOND 1000000
+
+#define SRE_HITIMER_DEFAULT_TICKS 100
+#define SRE_HITIMER_RELOAD_TICKS 1
+
+#define SRE_HITIMER_INT_CLEAR (0x01)
+#define SRE_HITIMER_CNTL_ENABLE (0x80)
+#define SRE_HITIMER_CNTL_MODE (0x40)
+#define SRE_HITIMER_CNTL_IRQ_ENABLE (0x20)
+#define SRE_HITIMER_CNTL_SIZEMODE (0x2)
+
+
+#define SRE_HITIMER_CNTL_MODE_ONCE 0
+#define SRE_HITIMER_CNTL_MODE_CYCLE 1
+#define SRE_HITIMER_CNTL_IRQ_ON 1
+#define SRE_HITIMER_CNTL_IRQ_OFF 0
+
+
+#define SRE_D01_HITIMER01_INTVEC (256)
+#define SRE_D01_HITIMER23_INTVEC (257)
+#define SRE_D01_HITIMER45_INTVEC (258)
+#define SRE_D01_HITIMER67_INTVEC (259)
+#define SRE_D01_HITIMER89_INTVEC (260)
+#define SRE_D01_HITIMER1011_INTVEC (261)
+#define SRE_D01_HITIMER1213_INTVEC (262)
+#define SRE_D01_HITIMER1415_INTVEC (263)
+#define SRE_D01_HITIMER1617_INTVEC (264)
+#define SRE_D01_HITIMER1819_INTVEC (265)
+#define SRE_D01_HITIMER2021_INTVEC (266)
+#define SRE_D01_HITIMER2223_INTVEC (267)
+#define SRE_D01_HITIMER2425_INTVEC (268)
+#define SRE_D01_HITIMER2627_INTVEC (269)
+#define SRE_D01_HITIMER2829_INTVEC (270)
+#define SRE_D01_HITIMER3031_INTVEC (271)
+#define SRE_D01_HITIMER3233_INTVEC (272)
+#define SRE_D01_HITIMER3435_INTVEC (273)
+#define SRE_D01_HITIMER3637_INTVEC (274)
+#define SRE_D01_HITIMER3839_INTVEC (275)
+#define SRE_D01_HITIMER4041_INTVEC (276)
+#define SRE_D01_HITIMER4243_INTVEC (277)
+#define SRE_D01_HITIMER4445_INTVEC (278)
+#define SRE_D01_HITIMER4647_INTVEC (279)
+
+UINT32 gRegBase = SRE_HITIMER_ADDR;
+#define SC_CTRL 0xe3e00000
+
+void HITIMER_Start()
+{
+ UINT32 ulRegAddr;
+ UINT32 ulVal = 0;
+ UINT32 ulMask;
+
+ ulVal = *(UINT32*)SC_CTRL;
+ ulVal |= BIT17 | BIT16 | BIT18 | BIT19;
+ *(UINT32*)SC_CTRL = ulVal;
+
+ /*timer mode*/
+ ulMask = SRE_HITIMER_CNTL_MODE; //BIT6
+ ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
+ ulVal = *(UINT32*)ulRegAddr;
+ ulVal = ulVal;
+ ulVal |= ulMask; /*cycle*/
+ *(UINT32*)ulRegAddr = ulVal;
+
+ /*int mode*/
+ ulMask = SRE_HITIMER_CNTL_IRQ_ENABLE; //BIT5
+ ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
+ ulVal = *(UINT32*)ulRegAddr;
+ ulVal = ulVal;
+ ulVal |= ulMask;
+ //DEBUG((EFI_D_ERROR, "int mode = %0x at %0x\n", ulVal, ulRegAddr));
+ *(UINT32*)ulRegAddr = ulVal;
+
+ /*start up*/
+ ulMask = (SRE_HITIMER_ENCLK_SEL_BIT | SRE_HITIMER_CNTL_SIZEMODE); //BIT7 | BIT1
+ ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
+ ulVal = *(UINT32*)ulRegAddr;
+ ulVal = ulVal;
+ ulVal |= ulMask;
+ //DEBUG((EFI_D_ERROR, "start up = %0x at %0x\n", ulVal, ulRegAddr));
+ *(UINT32*)ulRegAddr = ulVal;
+
+}
+
+void HITMER_ClearInt()
+{
+ UINT32 ulRegAddr;
+ UINT32 ulVal = 0;
+
+
+ ulRegAddr = gRegBase + SRE_HITIMER32_INTC_OFFSET;
+ ulVal = SRE_HITIMER_INT_CLEAR;
+ //DEBUG((EFI_D_ERROR, "HITMER_ClearInt = %0x at %0x\n", ulVal, ulRegAddr));
+ *(UINT32*)ulRegAddr = ulVal;
+
+}
+
+void DisableTimer()
+{
+ UINT32 ulRegAddr;
+ UINT32 ulVal = 0;
+ UINT32 ulMask;
+
+ /*disable*/
+ ulMask = SRE_HITIMER_ENCLK_SEL_BIT;
+ ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
+ ulVal = *(UINT32*)ulRegAddr;
+ ulVal = ulVal;
+ ulVal &= (~ulMask);
+ //DEBUG((EFI_D_ERROR, "DisableTimer = %0x at %0x\n", ulVal, ulRegAddr));
+ *(UINT32*)ulRegAddr = ulVal;
+
+}
+
+void EnableTimer()
+{
+ UINT32 ulRegAddr;
+ UINT32 ulVal = 1;
+ UINT32 ulMask;
+
+ /*disable*/
+ ulMask = SRE_HITIMER_ENCLK_SEL_BIT;
+ ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
+ ulVal = *(UINT32*)ulRegAddr;
+ ulVal = ulVal;
+ ulVal |= ulMask;
+ //DEBUG((EFI_D_ERROR, "EnableTimer = %0x at %0x\n", ulVal, ulRegAddr));
+ *(UINT32*)ulRegAddr = ulVal;
+
+}
+
+/**
+ This function registers the handler NotifyFunction so it is called every time
+ the timer interrupt fires. It also passes the amount of time since the last
+ handler call to the NotifyFunction. If NotifyFunction is NULL, then the
+ handler is unregistered. If the handler is registered, then EFI_SUCCESS is
+ returned. If the CPU does not support registering a timer interrupt handler,
+ then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
+ when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+ If an attempt is made to unregister a handler when a handler is not registered,
+ then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
+ register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+ is returned.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param NotifyFunction The function to call when a timer interrupt fires. This
+ function executes at TPL_HIGH_LEVEL. The DXE Core will
+ register a handler for the timer interrupt, so it can know
+ how much time has passed. This information is used to
+ signal timer based events. NULL will unregister the handler.
+ @retval EFI_SUCCESS The timer handler was registered.
+ @retval EFI_UNSUPPORTED The platform does not support timer interrupts.
+ @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already
+ registered.
+ @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not
+ previously registered.
+ @retval EFI_DEVICE_ERROR The timer handler could not be registered.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverRegisterHandler (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ IN EFI_TIMER_NOTIFY NotifyFunction
+ )
+{
+ if ((NotifyFunction == NULL) && (mTimerNotifyFunction == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if ((NotifyFunction != NULL) && (mTimerNotifyFunction != NULL)) {
+ return EFI_ALREADY_STARTED;
+ }
+
+ mTimerNotifyFunction = NotifyFunction;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Disable the timer
+**/
+VOID
+EFIAPI
+ExitBootServicesEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ DisableTimer ();
+}
+
+/**
+
+ This function adjusts the period of timer interrupts to the value specified
+ by TimerPeriod. If the timer period is updated, then the selected timer
+ period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+ If an error occurs while attempting to update the timer period, then the
+ timer hardware will be put back in its state prior to this call, and
+ EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
+ is disabled. This is not the same as disabling the CPU's interrupts.
+ Instead, it must either turn off the timer hardware, or it must adjust the
+ interrupt controller so that a CPU interrupt is not generated when the timer
+ interrupt fires.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is
+ returned. If the timer is programmable, then the timer period
+ will be rounded up to the nearest timer period that is supported
+ by the timer hardware. If TimerPeriod is set to 0, then the
+ timer interrupts will be disabled.
+
+
+ @retval EFI_SUCCESS The timer period was changed.
+ @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt.
+ @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverSetTimerPeriod (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ IN UINT64 TimerPeriod
+ )
+{
+ UINT64 TimerTicks;
+
+ UINT32 ulRegAddr;
+
+ // always disable the timer
+ DisableTimer ();
+
+ if (TimerPeriod != 0) {
+ // Convert TimerPeriod to micro sec units
+ #if 0
+ TimerTicks = DivU64x32 (TimerPeriod, 10);
+
+ TimerTicks = MultU64x32 (TimerTicks, (PcdGet32(PcdArmArchTimerFreqInHz)/1000000));
+ #endif
+
+ TimerTicks = DivU64x32 (TimerPeriod, 100);
+ TimerTicks = MultU64x32 (TimerTicks, (PcdGet32(PcdArmArchTimerFreqInHz)/100000));
+
+ //ArmArchTimerSetTimerVal((UINTN)TimerTicks);
+
+ ulRegAddr = gRegBase + SRE_HITIMER32_LOAD_OFFSET;
+ //DEBUG((EFI_D_ERROR, "TimerTicks1 = %0x at %0x ======\n", TimerTicks, ulRegAddr));
+ *(UINT32*)ulRegAddr = TimerTicks;
+ ulRegAddr = gRegBase + SRE_HITIMER32_BGLOAD_OFFSET;
+ //DEBUG((EFI_D_ERROR, "TimerTicks2 = %0x at %0x \n", TimerTicks, ulRegAddr));
+ *(UINT32*)ulRegAddr = TimerTicks;
+
+ // Enable the timer
+ EnableTimer ();
+ }
+
+ // Save the new timer period
+ mTimerPeriod = TimerPeriod;
+ return EFI_SUCCESS;
+}
+
+/**
+ This function retrieves the period of timer interrupts in 100 ns units,
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
+ returned, then the timer is currently disabled.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+ @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If
+ 0 is returned, then the timer is currently disabled.
+
+
+ @retval EFI_SUCCESS The timer period was returned in TimerPeriod.
+ @retval EFI_INVALID_PARAMETER TimerPeriod is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverGetTimerPeriod (
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ OUT UINT64 *TimerPeriod
+ )
+{
+ if (TimerPeriod == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *TimerPeriod = mTimerPeriod;
+ return EFI_SUCCESS;
+}
+
+/**
+ This function generates a soft timer interrupt. If the platform does not support soft
+ timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
+ If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
+ service, then a soft timer interrupt will be generated. If the timer interrupt is
+ enabled when this service is called, then the registered handler will be invoked. The
+ registered handler should not be able to distinguish a hardware-generated timer
+ interrupt from a software-generated timer interrupt.
+
+ @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+
+ @retval EFI_SUCCESS The soft timer interrupt was generated.
+ @retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts.
+
+**/
+EFI_STATUS
+EFIAPI
+TimerDriverGenerateSoftInterrupt (
+ IN EFI_TIMER_ARCH_PROTOCOL *This
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Interface structure for the Timer Architectural Protocol.
+
+ @par Protocol Description:
+ This protocol provides the services to initialize a periodic timer
+ interrupt, and to register a handler that is called each time the timer
+ interrupt fires. It may also provide a service to adjust the rate of the
+ periodic timer interrupt. When a timer interrupt occurs, the handler is
+ passed the amount of time that has passed since the previous timer
+ interrupt.
+
+ @param RegisterHandler
+ Registers a handler that will be called each time the
+ timer interrupt fires. TimerPeriod defines the minimum
+ time between timer interrupts, so TimerPeriod will also
+ be the minimum time between calls to the registered
+ handler.
+
+ @param SetTimerPeriod
+ Sets the period of the timer interrupt in 100 nS units.
+ This function is optional, and may return EFI_UNSUPPORTED.
+ If this function is supported, then the timer period will
+ be rounded up to the nearest supported timer period.
+
+
+ @param GetTimerPeriod
+ Retrieves the period of the timer interrupt in 100 nS units.
+
+ @param GenerateSoftInterrupt
+ Generates a soft timer interrupt that simulates the firing of
+ the timer interrupt. This service can be used to invoke the registered handler if the timer interrupt has been masked for
+ a period of time.
+
+**/
+EFI_TIMER_ARCH_PROTOCOL gTimer = {
+ TimerDriverRegisterHandler,
+ TimerDriverSetTimerPeriod,
+ TimerDriverGetTimerPeriod,
+ TimerDriverGenerateSoftInterrupt
+};
+
+/**
+
+ C Interrupt Handler called in the interrupt context when Source interrupt is active.
+
+
+ @param Source Source of the interrupt. Hardware routing off a specific platform defines
+ what source means.
+
+ @param SystemContext Pointer to system register context. Mostly used by debuggers and will
+ update the system context after the return from the interrupt if
+ modified. Don't change these values unless you know what you are doing
+
+**/
+VOID
+EFIAPI
+TimerInterruptHandler (
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN EFI_SYSTEM_CONTEXT SystemContext
+ )
+{
+ EFI_TPL OriginalTPL;
+
+ //
+ // DXE core uses this callback for the EFI timer tick. The DXE core uses locks
+ // that raise to TPL_HIGH and then restore back to current level. Thus we need
+ // to make sure TPL level is set to TPL_HIGH while we are handling the timer tick.
+ //
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+ OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+
+ // Check if the timer interrupt is active
+ //if ((*(UINT32*)(gRegBase + SRE_HITIMER32_RIS_OFFSET)) & BIT0) {
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+ HITMER_ClearInt();
+
+ // Signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers
+ gInterrupt->EndOfInterrupt (gInterrupt, Source);
+
+
+ if (mTimerNotifyFunction) {
+ mTimerNotifyFunction (mTimerPeriod);
+ }
+
+ // Reload the Timer
+ //TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod));
+ //}
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+
+ // Enable timer interrupts
+ //gInterrupt->EnableInterruptSource (gInterrupt, Source);
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+
+ gBS->RestoreTPL (OriginalTPL);
+}
+
+
+
+
+/**
+ Initialize the state information for the Timer Architectural Protocol and
+ the Timer Debug support protocol that allows the debugger to break into a
+ running program.
+
+ @param ImageHandle of the loaded driver
+ @param SystemTable Pointer to the System Table
+
+ @retval EFI_SUCCESS Protocol registered
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Hardware problems
+
+**/
+EFI_STATUS
+EFIAPI
+TimerInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_HANDLE Handle = NULL;
+ EFI_STATUS Status;
+
+
+ // Find the interrupt controller protocol. ASSERT if not found.
+ Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
+ ASSERT_EFI_ERROR (Status);
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+
+ // Disable the timer
+ Status = TimerDriverSetTimerPeriod (&gTimer, 0);
+ ASSERT_EFI_ERROR (Status);
+
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+ // Install secure and Non-secure interrupt handlers
+ // Note: Because it is not possible to determine the security state of the
+ // CPU dynamically, we just install interrupt handler for both sec and non-sec
+ // timer PPI
+ Status = gInterrupt->RegisterInterruptSource (gInterrupt, 256, TimerInterruptHandler);
+ ASSERT_EFI_ERROR (Status);
+
+ //Status = gInterrupt->RegisterInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerIntrNum), TimerInterruptHandler);
+ //ASSERT_EFI_ERROR (Status);
+
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+ // Unmask timer interrupts
+ HITIMER_Start();
+
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+
+ // Set up default timer
+ Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
+ ASSERT_EFI_ERROR (Status);
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+
+ // Install the Timer Architectural Protocol onto a new handle
+ Status = gBS->InstallMultipleProtocolInterfaces(
+ &Handle,
+ &gEfiTimerArchProtocolGuid, &gTimer,
+ NULL
+ );
+ ASSERT_EFI_ERROR(Status);
+ //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
+
+ // enable Secure timer interrupts
+ Status = gInterrupt->EnableInterruptSource (gInterrupt, 256);
+
+ // enable NonSecure timer interrupts
+ //Status = gInterrupt->EnableInterruptSource (gInterrupt, PcdGet32 (PcdArmArchTimerIntrNum));
+
+ // Register for an ExitBootServicesEvent
+ Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/HisiPkg/Drivers/TimerDxe/TimerDxe.inf b/HisiPkg/Drivers/TimerDxe/TimerDxe.inf new file mode 100644 index 000000000..9661cd113 --- /dev/null +++ b/HisiPkg/Drivers/TimerDxe/TimerDxe.inf @@ -0,0 +1,60 @@ +#/** @file
+#
+# Component description file for Timer DXE module
+#
+# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = ArmTimerDxe
+ FILE_GUID = 49ea041e-6752-42ca-b0b1-7344fe2546b7
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = TimerInitialize
+
+[Sources.common]
+ TimerDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+ ArmLib
+ BaseLib
+ UefiRuntimeServicesTableLib
+ UefiLib
+ UefiBootServicesTableLib
+ BaseMemoryLib
+ DebugLib
+ UefiDriverEntryPoint
+ IoLib
+
+[Guids]
+
+[Protocols]
+ gEfiTimerArchProtocolGuid
+ gHardwareInterruptProtocolGuid
+
+[Pcd.common]
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+
+[Depex]
+ gHardwareInterruptProtocolGuid
+
\ No newline at end of file diff --git a/HisiPkg/Drivers/WatchDogDriver/WatchDogDriver.inf b/HisiPkg/Drivers/WatchDogDriver/WatchDogDriver.inf new file mode 100644 index 000000000..5cb0b4c22 --- /dev/null +++ b/HisiPkg/Drivers/WatchDogDriver/WatchDogDriver.inf @@ -0,0 +1,25 @@ +#/** @file
+# Component name for module WatchdogDriver
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = WatchdogDriver
+ FILE_GUID = 93B70004-9FC5-11d4-9A4B-0090283FC14D
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = WdtClearWatchdogEntry
+[Binaries.common]
+ DXE_DEPEX|WatchdogDriver.depex
+ PE32|WatchdogDriver.efi|*
+
diff --git a/HisiPkg/Drivers/WatchDogDriver/WatchdogDriver.depex b/HisiPkg/Drivers/WatchDogDriver/WatchdogDriver.depex Binary files differnew file mode 100644 index 000000000..03d5718dd --- /dev/null +++ b/HisiPkg/Drivers/WatchDogDriver/WatchdogDriver.depex diff --git a/HisiPkg/Drivers/WatchDogDriver/WatchdogDriver.efi b/HisiPkg/Drivers/WatchDogDriver/WatchdogDriver.efi Binary files differnew file mode 100644 index 000000000..ea568027c --- /dev/null +++ b/HisiPkg/Drivers/WatchDogDriver/WatchdogDriver.efi diff --git a/HisiPkg/Drivers/ramdisk/ramdisk.c b/HisiPkg/Drivers/ramdisk/ramdisk.c new file mode 100644 index 000000000..cb64907f8 --- /dev/null +++ b/HisiPkg/Drivers/ramdisk/ramdisk.c @@ -0,0 +1,573 @@ +/*
+ * Copyright (c) 1999, 2000
+ * Intel Corporation.
+ * All rights reserved.
+ * Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. All advertising materials mentioning features or use of this software must
+ * display the following acknowledgement:
+ *
+ * This product includes software developed by Intel Corporation and its
+ * contributors.
+ *
+ * 4. Neither the name of Intel Corporation or its contributors may be used to
+ * endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <Uefi.h>
+
+#include <Protocol/BlockIo.h>
+#include <Protocol/LoadedImage.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <Library/DevicePathLib.h>
+#include "./ramdisk.h"
+
+#define DEFAULT_DISK_SIZE 30 /* in MBs */
+
+UINT32 GetDiskSize( EFI_HANDLE ImageHandle );
+
+/* Embedded version string for VERS utility */
+//static char v[] = "version_number=1.00 ";
+
+/* EFI device path definition */
+static RAM_DISK_DEVICE_PATH RamDiskDevicePath =
+{
+ { + MESSAGING_DEVICE_PATH, + MSG_VENDOR_DP, + { + sizeof(RAM_DISK_DEVICE_PATH) - END_DEVICE_PATH_LENGTH, + 0 + }, + }, + // {06ED4DD0-FF78-11d3-BDC4-00A0C94053D1}
+ { + 0x6ed4dd0, 0xff78, 0x11d3, + {0xbd, 0xc4, 0x0, 0xa0, 0xc9, 0x40, 0x53, 0xd1}, + }, + {0,0,0,0,0,0,0,0}, // ID assigned below + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + }, + }, +};
+
+/* Lookup table of total sectors vs. cluster size.
+ * Ramdisk sizes between 0x20D0 (4.1MB) and 0x100000 (512MB) sectors are valid FAT16 drive sizes.
+ */
+/* #define MIN_DISK_SIZE 5 */
+#define MIN_DISK_SIZE 1
+#define MAX_DISK_SIZE 512
+static FAT16TABLE fat16tbl[] =
+{
+ /* {0x000020D0, 0}, */
+ {0x00000800, 1}, /* 800 sectors * 1 sec/cluster * 512 bytes = 1 M */
+ {0x00001000, 1}, /* 1000 sectors * 1 sec/cluster * 512 bytes = 2 M */
+ {0x00001800, 1}, /* 1800 sectors * 1 sec/cluster * 512 bytes = 3 M */
+ {0x00007FA8, 2},
+ {0x00040000, 4},
+ {0x00080000, 8},
+ {0x00100000,16},
+ {0xFFFFFFFF, 0}
+};
+
+VOID CopyBOOTSEC(VOID* Start,BOOTSEC* bsc)
+{
+UINT32 index=0;
+UINT8* pStart=(UINT8*)Start;
+
+CopyMem(&(pStart[index]), &(bsc->BS_jmpBoot[0]), sizeof(bsc->BS_jmpBoot));
+index+=sizeof(bsc->BS_jmpBoot);
+
+CopyMem(&(pStart[index]), &(bsc->BS_OEMName[0]), sizeof(bsc->BS_OEMName));
+index+=sizeof(bsc->BS_OEMName);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_BytsPerSec), sizeof(bsc->BPB_BytsPerSec));
+index+=sizeof(bsc->BPB_BytsPerSec);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_SecPerClus), sizeof(bsc->BPB_SecPerClus));
+index+=sizeof(bsc->BPB_SecPerClus);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_RsvdSecCnt), sizeof(bsc->BPB_RsvdSecCnt));
+index+=sizeof(bsc->BPB_RsvdSecCnt);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_NumFATs), sizeof(bsc->BPB_NumFATs));
+index+=sizeof(bsc->BPB_NumFATs);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_NumFATs), sizeof(bsc->BPB_NumFATs));
+index+=sizeof(bsc->BPB_NumFATs);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_RootEntCnt), sizeof(bsc->BPB_RootEntCnt));
+index+=sizeof(bsc->BPB_RootEntCnt);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_TotSec16), sizeof(bsc->BPB_TotSec16));
+index+=sizeof(bsc->BPB_TotSec16);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_Media), sizeof(bsc->BPB_Media));
+index+=sizeof(bsc->BPB_Media);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_FATSz16), sizeof(bsc->BPB_FATSz16));
+index+=sizeof(bsc->BPB_FATSz16);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_SecPerTrk), sizeof(bsc->BPB_SecPerTrk));
+index+=sizeof(bsc->BPB_SecPerTrk);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_NumHeads), sizeof(bsc->BPB_NumHeads));
+index+=sizeof(bsc->BPB_NumHeads);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_HiddSec), sizeof(bsc->BPB_HiddSec));
+index+=sizeof(bsc->BPB_HiddSec);
+
+CopyMem(&(pStart[index]), &(bsc->BPB_TotSec32), sizeof(bsc->BPB_TotSec32));
+index+=sizeof(bsc->BPB_TotSec32);
+
+CopyMem(&(pStart[index]), &(bsc->BS_DrvNum), sizeof(bsc->BS_DrvNum));
+index+=sizeof(bsc->BS_DrvNum);
+
+CopyMem(&(pStart[index]), &(bsc->BS_Reserved1), sizeof(bsc->BS_Reserved1));
+index+=sizeof(bsc->BS_Reserved1);
+
+CopyMem(&(pStart[index]), &(bsc->BS_BootSig), sizeof(bsc->BS_BootSig));
+index+=sizeof(bsc->BS_BootSig);
+
+CopyMem(&(pStart[index]), &(bsc->BS_VolID), sizeof(bsc->BS_VolID));
+index+=sizeof(bsc->BS_VolID);
+
+CopyMem(&(pStart[index]), &(bsc->BS_VolLab[0]), sizeof(bsc->BS_VolLab));
+index+=sizeof(bsc->BS_VolLab);
+
+CopyMem(&(pStart[index]), &(bsc->BS_FilSysType[0]), sizeof(bsc->BS_FilSysType));
+index+=sizeof(bsc->BS_FilSysType);
+
+CopyMem(&(pStart[index]), &(bsc->BS_Code[0]), sizeof(bsc->BS_Code));
+index+=sizeof(bsc->BS_Code);
+
+CopyMem(&(pStart[index]), &(bsc->BS_Sig), sizeof(bsc->BS_Sig));
+
+}
+
+/*++
+
+Routine Description:
+
+ Convert hex string to uint
+
+Arguments:
+
+ Str - The string
+
+Returns:
+
+--*/
+STATIC UINTN Atoi ( CHAR16 *str)
+{
+ UINTN u;
+ CHAR16 c;
+ UINTN m;
+ UINTN n;
+
+ ASSERT (str != NULL);
+
+ m = (UINTN) -1 / 10;
+ n = (UINTN) -1 % 10;
+ //
+ // skip preceeding white space
+ //
+ while (*str && (*str == ' '))
+ {
+ str += 1;
+ }
+ //
+ // convert digits
+ //
+ u = 0;
+ c = *(str++);
+ while (c)
+ {
+ if ((c >= '0') && (c <= '9'))
+ {
+ if ((u >= m) && ((c - '0') > (INTN) n))
+ {
+ return (UINTN) -1;
+ }
+
+ u = (u * 10) + c - '0';
+ }
+ else
+ {
+ break;
+ }
+
+ c = *(str++);
+ }
+
+ return u;
+}
+
+/* Helper function to compute cluster size
+ * vs. total sectors on drive.
+ */
+STATIC UINT8 size2spc(UINT32 ts)
+{
+ int i = 0;
+
+ while(fat16tbl[i].size != 0xFFFFFFFF)
+ {
+ if(ts <= fat16tbl[i].size)
+ return fat16tbl[i].spc;
+ ++i;
+ }
+
+ return 0;
+}
+
+UINT8 TestSize(UINT32 ts)
+{
+ int i = 0;
+
+ while(fat16tbl[i].size != 0xFFFFFFFF)
+ {
+ if(ts <= fat16tbl[i].size)
+ return fat16tbl[i].spc;
+ ++i;
+ }
+
+ return 0;
+}
+
+EFI_SYSTEM_TABLE BackupSystemTable;
+
+/*
+ * Entry point for RamDisk driver.
+ */
+
+EFI_STATUS InitializeRamDiskDriver(
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable)
+{
+ EFI_STATUS Status;
+ RAM_DISK_DEV *RamDiskDev;
+ UINT32 RamDiskSize;
+ UINT32 NumPages;
+ UINT32 BlockSize;
+ UINT64 DiskId;
+
+ /*
+ * Make a copy of the system table to workaround load command bug
+ */
+ CopyMem(&BackupSystemTable,SystemTable,sizeof(BackupSystemTable));
+
+ /*
+ * Initialize EFI library
+ */
+ //InitializeLib(ImageHandle,&BackupSystemTable);
+
+ /* IA64 compiler is removing version string (unused?) so I use it */
+ //v[0] = 'v';
+
+ /*
+ * Set the disk size
+ */
+ RamDiskSize = GetDiskSize(ImageHandle);
+ BlockSize = 512;
+
+ /* Allocate storage for ramdisk device info on the heap.
+ */
+ RamDiskDev = AllocateZeroPool(sizeof(RAM_DISK_DEV));
+ if(RamDiskDev == NULL)
+ return EFI_OUT_OF_RESOURCES;
+
+ /*
+ * Compute the number of 4KB pages needed by the ramdisk and allocate the memory.
+ */
+ NumPages = RamDiskSize / EFI_PAGE_SIZE;
+ if(NumPages % RamDiskSize)
+ NumPages++;
+
+ Status = gBS->AllocatePages(AllocateAnyPages,EfiBootServicesData,NumPages,&RamDiskDev->Start);
+ if(EFI_ERROR(Status)) {
+ FreePool(RamDiskDev);
+ return Status;
+ }
+
+ /*
+ * Initialize the ramdisk's device info.
+ */
+ (void)gBS->GetNextMonotonicCount(&DiskId);
+ CopyMem(&RamDiskDevicePath.DiskId, &DiskId, sizeof(DiskId));
+
+ RamDiskDev->Signature = PBLOCK_DEVICE_SIGNATURE;
+ RamDiskDev->BlkIo.Revision = EFI_BLOCK_IO_INTERFACE_REVISION;
+ RamDiskDev->BlkIo.Media = &RamDiskDev->Media;
+ RamDiskDev->Media.RemovableMedia = FALSE;
+ RamDiskDev->Media.MediaPresent = TRUE;
+
+ RamDiskDev->Media.LastBlock = RamDiskSize/BlockSize - 1;
+ RamDiskDev->Media.BlockSize = BlockSize;
+ RamDiskDev->Media.LogicalPartition = TRUE;
+ RamDiskDev->Media.ReadOnly = FALSE;
+ RamDiskDev->Media.WriteCaching = TRUE;
+
+ RamDiskDev->BlkIo.ReadBlocks = RamDiskReadBlocks;
+ RamDiskDev->BlkIo.WriteBlocks = RamDiskWriteBlocks;
+ RamDiskDev->BlkIo.FlushBlocks = RamDiskFlushBlocks;
+
+ RamDiskDev->DevicePath = DuplicateDevicePath((EFI_DEVICE_PATH*)&RamDiskDevicePath);
+
+ /*
+ * Build a FAT16 file system on the ramdisk.
+ */
+ FormatRamdisk((VOID*)(UINTN)RamDiskDev->Start,RamDiskSize);
+
+ /*
+ * Install the device.
+ */
+
+ Status = gBS->InstallMultipleProtocolInterfaces(
+ &ImageHandle,
+ &gEfiBlockIoProtocolGuid,
+ &RamDiskDev->BlkIo,
+ &gEfiDevicePathProtocolGuid,
+ RamDiskDev->DevicePath,
+ NULL);
+
+DEBUG((EFI_D_ERROR,"ramdisk:blckio install. Status=%r\n",Status));
+ return Status;
+}
+
+UINT32
+GetDiskSize( EFI_HANDLE ImageHandle )
+{
+ EFI_STATUS Status;
+ EFI_LOADED_IMAGE *Image;
+ UINT32 DiskSize = DEFAULT_DISK_SIZE;
+
+ /*
+ * Check load options to see if they want to specify disk size in MBs
+ */
+ Status = gBS->HandleProtocol(ImageHandle, &gEfiLoadedImageProtocolGuid, (void**)&Image);
+ if (!EFI_ERROR(Status)) {
+ if (Image->LoadOptions && Image->LoadOptionsSize) {
+#define MAX_ARG_SIZE 32
+ CHAR16 Size[ MAX_ARG_SIZE ];
+ CHAR16 *CmdLine = Image->LoadOptions;
+ INT32 CmdLen = (INT32)Image->LoadOptionsSize;
+
+ /*
+ * Get past program name
+ */
+ while( CmdLen > 0 && *CmdLine != L' ' ) {
+ CmdLen -= sizeof(CHAR16);
+ CmdLine++;
+ }
+
+ if ( CmdLen > 0 ) {
+ /*
+ * Make sure we're null terminated
+ */
+ CopyMem( Size, CmdLine, MIN(CmdLen, sizeof(Size)));
+ Size[MAX_ARG_SIZE - 1] = 0;
+
+ /*
+ * Atoi() will skip any leading white space
+ */
+ DiskSize = (UINT32)Atoi(Size);
+ if (DiskSize == 0)
+ DiskSize = DEFAULT_DISK_SIZE;
+ DiskSize = MAX(DiskSize, MIN_DISK_SIZE);
+ DiskSize = MIN(DiskSize, MAX_DISK_SIZE);
+ }
+ }
+ }
+
+ return (DiskSize * 1024 * 1024);
+}
+
+/* Given a block of memory representing a ramdisk, build a pseudo-boot sector
+ * and initialize the drive.
+ *
+ * Assumes the global boot sector structure g_bs has been filled out with the
+ * static information the boot sector requires. Also assumes the ramdisk size
+ * is between 4.1MB and 512MB as appropriate for FAT16 file system.
+ */
+STATIC VOID FormatRamdisk(
+ IN VOID* pStart,
+ IN UINT32 Size)
+{
+ UINT32 TotalSectors,RootDirSectors,FatSz,tmp1,tmp2;
+ UINT8 *Fat1,*Fat2;
+ BOOTSEC g_bs={
+ /* BS_jmpBoot */ {0xeb,0x0,0x90},
+ /* BS_OEMName */ {'E','F','I','R','D','I','S','K'},
+ /* BPB_BytsPerSec */ 512,
+ /* BPB_SecPerClus */ 0,
+ /* BPB_RsvdSecCnt */ 1,
+ /* BPB_NumFATs */ 2,
+ /* BPB_RootEntCnt */ 512,
+ /* BPB_TotSec16 */ 0,
+ /* BPB_Media */ 0xF8,
+ /* BPB_FATSz16 */ 0,
+ /* BPB_SecPerTrk */ 0,
+ /* BPB_NumHeads */ 0,
+ /* BPB_HiddSec */ 0,
+ /* BPB_TotSec32 */ 0,
+ /* BS_DrvNum */ 0,
+ /* BS_Reserved1 */ 0,
+ /* BS_BootSig */ 0x29,
+ /* BS_VolID */ 0,
+ /* BS_VolLab */ {'N','O',' ','N','A','M','E',' ',' ',' '},
+ /* BS_FilSysType */ {'F','A','T','1','6',' ',' ',' '}
+};
+
+ /* The boot signature needs to be filled out */
+ g_bs.BS_Sig = 0xAA55;
+
+ /* Compute the total sectors and appropriate cluster size */
+ TotalSectors = Size / g_bs.BPB_BytsPerSec;
+ g_bs.BPB_SecPerClus = size2spc(TotalSectors);
+ ASSERT(g_bs.BPB_SecPerClus != 0);
+
+ /* Compute how many root directory sectors are needed */
+ RootDirSectors = (g_bs.BPB_RootEntCnt * 32 + g_bs.BPB_BytsPerSec - 1) / g_bs.BPB_BytsPerSec;
+
+ /* Compute how many sectors are required per FAT */
+ tmp1 = TotalSectors - (g_bs.BPB_RsvdSecCnt + RootDirSectors);
+ tmp2 = 256 * g_bs.BPB_SecPerClus + g_bs.BPB_NumFATs;
+ FatSz = (tmp1 + tmp2 - 1) / tmp2;
+ ASSERT(FatSz <= 0xFFFF);
+
+ /* Store the total sectors and fat size values */
+ if(TotalSectors > 0xFFFF)
+ g_bs.BPB_TotSec32 = TotalSectors;
+ else
+ g_bs.BPB_TotSec16 = (UINT16)TotalSectors;
+
+ g_bs.BPB_FATSz16 = (UINT16)FatSz;
+
+ /* The FAT table and root directory need to be all zeroes.
+ * We'll zero the whole drive.
+ */
+ ZeroMem(pStart,Size);
+
+ /* Write the completed boot sector to the ramdisk */
+ CopyMem(pStart,&g_bs,512);
+
+ /* Compute the starting offsets of the two FATs */
+ Fat1 = (UINT8*)pStart + g_bs.BPB_RsvdSecCnt * 512;
+ Fat2 = (UINT8*)pStart + (g_bs.BPB_RsvdSecCnt + FatSz) * 512;
+
+ /* Initialize FAT1 */
+ Fat1[0] = g_bs.BPB_Media;
+ Fat1[1] = 0xFF;
+ Fat1[2] = 0xFF;
+ Fat1[3] = 0xFF;
+
+ /* Initialize FAT2 */
+ Fat2[0] = g_bs.BPB_Media;
+ Fat2[1] = 0xFF;
+ Fat2[2] = 0xFF;
+ Fat2[3] = 0xFF;
+}
+
+/* Implementation of block I/O read */
+STATIC EFI_STATUS RamDiskReadBlocks(
+ IN EFI_BLOCK_IO *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA LBA,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer)
+{
+ EFI_BLOCK_IO_MEDIA *Media;
+ RAM_DISK_DEV *RamDiskDev;
+ EFI_PHYSICAL_ADDRESS RamDiskLBA;
+
+ Media = This->Media;
+
+ if(BufferSize % Media->BlockSize != 0)
+ return EFI_BAD_BUFFER_SIZE;
+
+ if(LBA > Media->LastBlock)
+ return EFI_DEVICE_ERROR;
+
+ if(LBA + BufferSize / Media->BlockSize - 1 > Media->LastBlock)
+ return EFI_DEVICE_ERROR;
+
+ RamDiskDev = RAM_DISK_FROM_THIS(This);
+ RamDiskLBA = RamDiskDev->Start + MultU64x32(LBA,Media->BlockSize);
+ CopyMem(Buffer,(VOID*)(UINTN)RamDiskLBA,BufferSize);
+
+ return EFI_SUCCESS;
+}
+
+
+/* Implementation of block I/O write */
+STATIC EFI_STATUS RamDiskWriteBlocks(
+ IN EFI_BLOCK_IO *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA LBA,
+ IN UINTN BufferSize,
+ IN VOID *Buffer)
+{
+ EFI_BLOCK_IO_MEDIA *Media;
+ RAM_DISK_DEV *RamDiskDev;
+ EFI_PHYSICAL_ADDRESS RamDiskLBA;
+
+ Media = This->Media;
+ if(Media->ReadOnly)
+ return EFI_WRITE_PROTECTED;
+
+ if(BufferSize % Media->BlockSize != 0)
+ return EFI_BAD_BUFFER_SIZE;
+
+ if(LBA > Media->LastBlock)
+ return EFI_DEVICE_ERROR;
+
+ if(LBA + BufferSize / Media->BlockSize - 1 > Media->LastBlock)
+ return EFI_DEVICE_ERROR;
+
+ RamDiskDev = RAM_DISK_FROM_THIS(This);
+ RamDiskLBA = RamDiskDev->Start + MultU64x32(LBA,Media->BlockSize);
+ CopyMem((VOID*)(UINTN)RamDiskLBA,Buffer,BufferSize);
+
+ return EFI_SUCCESS;
+}
+
+/* Implementation of block I/O flush */
+STATIC EFI_STATUS RamDiskFlushBlocks(
+ IN EFI_BLOCK_IO *This)
+{
+ return EFI_SUCCESS;
+}
diff --git a/HisiPkg/Drivers/ramdisk/ramdisk.h b/HisiPkg/Drivers/ramdisk/ramdisk.h new file mode 100644 index 000000000..ff816c7b1 --- /dev/null +++ b/HisiPkg/Drivers/ramdisk/ramdisk.h @@ -0,0 +1,134 @@ +/*
+ * Copyright (c) 1999, 2000
+ * Intel Corporation.
+ * All rights reserved.
+ * Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. All advertising materials mentioning features or use of this software must
+ * display the following acknowledgement:
+ *
+ * This product includes software developed by Intel Corporation and its
+ * contributors.
+ *
+ * 4. Neither the name of Intel Corporation or its contributors may be used to
+ * endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _FATFILESYSTEM_H_
+#define _FATFILESYSTEM_H_
+
+#pragma pack(1)
+/* RAM disk device path structure.
+ * Will use Vendor Messaging Device Path.
+ */
+typedef struct sRAM_DISK_DEVICE_PATH
+{
+ EFI_DEVICE_PATH Header;
+ EFI_GUID Guid;
+ UINT8 DiskId[8];
+ EFI_DEVICE_PATH EndDevicePath;
+} RAM_DISK_DEVICE_PATH;
+
+/* FAT16 boot sector definition */
+typedef struct sBOOTSEC
+{
+ UINT8 BS_jmpBoot[3];
+ UINT8 BS_OEMName[8];
+ UINT16 BPB_BytsPerSec;
+ UINT8 BPB_SecPerClus;
+ UINT16 BPB_RsvdSecCnt;
+ UINT8 BPB_NumFATs;
+ UINT16 BPB_RootEntCnt;
+ UINT16 BPB_TotSec16;
+ UINT8 BPB_Media;
+ UINT16 BPB_FATSz16;
+ UINT16 BPB_SecPerTrk;
+ UINT16 BPB_NumHeads;
+ UINT32 BPB_HiddSec;
+ UINT32 BPB_TotSec32;
+ UINT8 BS_DrvNum;
+ UINT8 BS_Reserved1;
+ UINT8 BS_BootSig;
+ UINT32 BS_VolID;
+ UINT8 BS_VolLab[11];
+ UINT8 BS_FilSysType[8];
+ UINT8 BS_Code[448];
+ UINT16 BS_Sig;
+} BOOTSEC;
+
+#pragma pack()
+
+/* structure for total sectors to cluster size lookup */
+typedef struct sFAT16TABLE
+{
+ UINTN size;
+ UINT8 spc;
+} FAT16TABLE;
+
+#define PBLOCK_DEVICE_SIGNATURE SIGNATURE_32('r', 'd', 's', 'k')
+
+/* Ramdisk device info structure */
+typedef struct sRAM_DISKDEV
+{
+ UINTN Signature;
+ EFI_HANDLE Handle;
+ EFI_PHYSICAL_ADDRESS Start;
+ EFI_BLOCK_IO BlkIo;
+ EFI_BLOCK_IO_MEDIA Media;
+ EFI_DEVICE_PATH *DevicePath;
+} RAM_DISK_DEV;
+
+/* Macro finds the device info structure given a ramdisk BlkIo interface */
+#define RAM_DISK_FROM_THIS(a) CR(a,RAM_DISK_DEV,BlkIo,PBLOCK_DEVICE_SIGNATURE)
+
+/* Prototypes */
+EFI_STATUS InitializeRamDiskDriver(
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable);
+
+STATIC VOID FormatRamdisk(
+ IN VOID* pStart,
+ IN UINT32 Size);
+
+STATIC EFI_STATUS RamDiskReadBlocks(
+ IN EFI_BLOCK_IO *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA LBA,
+ IN UINTN BufferSize,
+ OUT VOID *Buffer);
+
+STATIC EFI_STATUS RamDiskWriteBlocks(
+ IN EFI_BLOCK_IO *This,
+ IN UINT32 MediaId,
+ IN EFI_LBA LBA,
+ IN UINTN BufferSize,
+ IN VOID *Buffer);
+
+STATIC EFI_STATUS RamDiskFlushBlocks(
+ IN EFI_BLOCK_IO *This);
+
+#endif
+
diff --git a/HisiPkg/Drivers/ramdisk/ramdisk.inf b/HisiPkg/Drivers/ramdisk/ramdisk.inf new file mode 100644 index 000000000..964fc49d1 --- /dev/null +++ b/HisiPkg/Drivers/ramdisk/ramdisk.inf @@ -0,0 +1,58 @@ +#/*++
+#
+# Copyright (c) 2004, Intel Corporation
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+# Module Name:
+#
+#
+#Mem.c
+#
+# Abstract:
+#
+# Component description file for set cmd reg module.
+#
+#--*/
+[Defines]
+
+INF_VERSION = 0x00010005
+BASE_NAME = ramdisk
+FILE_GUID = A8D2D6E6-D256-4c7a-B835-D6D1422212DB
+MODULE_TYPE = UEFI_DRIVER
+VERSION_STRING = 1.0
+ENTRY_POINT = InitializeRamDiskDriver
+
+[Sources]
+ramdisk.c
+ramdisk.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+# PV600Pkg/PV600Pkg.dec
+
+[LibraryClasses]
+ MemoryAllocationLib
+ BaseLib
+ UefiLib
+ UefiDriverEntryPoint
+
+ BaseMemoryLib
+ #DebugLib
+ #PcdLib
+ #UefiRuntimeServicesTableLib
+ #UefiBootServicesTableLib
+
+[Protocols]
+ gEfiBlockIoProtocolGuid
+ gEfiLoadedImageProtocolGuid
+
+
+
diff --git a/HisiPkg/HisiPlatformPkg.dec b/HisiPkg/HisiPlatformPkg.dec new file mode 100644 index 000000000..d49acd7e6 --- /dev/null +++ b/HisiPkg/HisiPlatformPkg.dec @@ -0,0 +1,80 @@ +#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+ DEC_SPECIFICATION = 0x00010005
+ PACKAGE_NAME = HisiPlatformPkg
+ PACKAGE_GUID = c6013a10-758c-4c0d-bd07-e601e6721f86
+ PACKAGE_VERSION = 0.1
+
+[Includes]
+ Include
+ Include/Protocol
+ Include/Ppi
+ Include/Library
+ Include/Guid
+
+[Ppis]
+
+
+
+[Protocols]
+ gWatchDogProtocolGuid = {0x707ac059, 0xf335, 0x4643, 0xa6, 0x99, 0x5e, 0x3b, 0x9b, 0x82, 0x60, 0x74}
+ gLinuxAtagListProtocolGuid = {0x46f1ef63, 0x24d3, 0x423b, {0x9d, 0x9, 0x8f, 0xc6, 0x77, 0xd0, 0x24, 0x9d}}
+ gUniNorFlashProtocolGuid = {0x86F305EA, 0xDFAC, 0x4A6B, {0x92, 0x77, 0x47, 0x31, 0x2E, 0xCE, 0x42, 0xA}}
+ gNANDDriverProtocolGuid = {0xf355bcc3, 0x252d, 0x4dee, {0xad, 0x05,0x94, 0xbb, 0x29, 0xc8, 0x4d, 0x46}} +
+[Guids]
+ gHwTokenSpaceGuid = { 0x99999999, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
+
+[PcdsFixedAtBuild]
+ gHwTokenSpaceGuid.PcdDefaultCoreTagFlags|1|UINT32|0x010000006
+ gHwTokenSpaceGuid.PcdDefaultCoreTagPageSize|0x00001000|UINT32|0x01000024
+ gHwTokenSpaceGuid.PcdDefaultCoreTagRootdev|0|UINT32|0x01000002
+
+ gHwTokenSpaceGuid.PcdDefaultMemTagStart|0x0|UINT32|0x01000003
+ gHwTokenSpaceGuid.PcdDefaultMemTagSize|0x10000000|UINT32|0x01000004
+
+ gHwTokenSpaceGuid.PcdNorFlashBase|0x30000000|UINT32|0x01000008
+
+ gHwTokenSpaceGuid.PcduImageStart|0x03300000|UINT32|0x01000005
+ gHwTokenSpaceGuid.PcdtinitrdStart|0x03800000|UINT32|0x01000007
+ gHwTokenSpaceGuid.PcdBootcmdAddr|0x00a01000|UINT32|0x010000c
+
+ gHwTokenSpaceGuid.PcdDefaultCmdlineTagCmdline|"mem=256M console=ttyAMA0,115200 quiet"|VOID*|0x010000F
+
+
+ gHwTokenSpaceGuid.PcdNANDCRegBase|0xe4020000|UINT32|0x0030000b
+ gHwTokenSpaceGuid.PcdNANDBufBase|0xe5000000|UINT32|0x0030000c
+
+
+ gHwTokenSpaceGuid.PcdGPIO0Base|0x14000000|UINT32|0x00300001
+ gHwTokenSpaceGuid.PcdGPIO1Base|0x14001000|UINT32|0x00300002
+ gHwTokenSpaceGuid.PcdGPIO2Base|0x14002000|UINT32|0x00300003
+ gHwTokenSpaceGuid.PcdGPIO3Base|0x14003000|UINT32|0x00300004
+ gHwTokenSpaceGuid.PcdGPIO4Base|0x14004000|UINT32|0x00300005
+
+ gArmTokenSpaceGuid.PcdSysCtrlBase|0x00000000|UINT32|0x01000009
+ gArmTokenSpaceGuid.PcdTimerBase|0x00000000|UINT32|0x0100000a
+ gArmTokenSpaceGuid.PcdTimer0InterruptNum|0x00000000|UINT32|0x0100000b
+
+ gHwTokenSpaceGuid.PcdEmbeddedBiosVersion|"ARM Platform"|VOID*|0x00000088
+
+ gHwTokenSpaceGuid.PcdGicPrimaryCoreId|0|UINT32|0x00000043
+
+
+[PcdsFeatureFlag]
+
+
+
diff --git a/HisiPkg/Include/Guid/.gitignore b/HisiPkg/Include/Guid/.gitignore new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/HisiPkg/Include/Guid/.gitignore diff --git a/HisiPkg/Include/Library/BrdCommon.h b/HisiPkg/Include/Library/BrdCommon.h new file mode 100644 index 000000000..87973a455 --- /dev/null +++ b/HisiPkg/Include/Library/BrdCommon.h @@ -0,0 +1,358 @@ +/*******************************************************************
+#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+#ifndef __BRDCOMMON_H
+#define __BRDCOMMON_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+#define HDF_FIRST_BOOTROM_FLAG 0x0
+#define HDF_SECOND_BOOTROM_FLAG 0x1
+
+#define DEFAULT_FIRST_BOOTROM_SPACE_SIZE (0x200000)
+#define DEFAULT_SECOND_BOOTROM_SPACE_SIZE (0x700000)
+#define DEFAULT_BSP_PARA_SPACE_SIZE (0x300000)
+
+
+#define DEFAULT_FIRST_BOOTROM_BINDFILE_SIZE (0x200000)
+#define DEFAULT_SECOND_BOOTROM_BINDFILE_SIZE (0x200000)
+
+#define DEFAULT_BOOTLINE_OFFSET_IN_PARA (0x20000+0x2000)
+
+#define FLASH_BASE_ADDR 0xf0000000
+
+#define FLASH_FIRST_HDF_ADDR (0)
+#define FLASH_FIRST_HDF_SIZE (0x20000)
+#define FLASH_FIRST_HDF_RSV_SIZE (0x60000)
+
+#define FLASH_SECOND_HDF_ADDR (FLASH_FIRST_HDF_ADDR + FLASH_FIRST_HDF_SIZE + FLASH_FIRST_HDF_RSV_SIZE)
+#define FLASH_SECOND_HDF_SIZE (FLASH_FIRST_HDF_SIZE)
+#define FLASH_SECOND_HDF_RSV_SIZE (FLASH_FIRST_HDF_RSV_SIZE)
+
+#define FIRST_BOOTROM_ADRS (0x100000)//(FLASH_SECOND_HDF_ADDR + FLASH_SECOND_HDF_SIZE + FLASH_SECOND_HDF_RSV_SIZE)
+
+#define FIRST_BOOTROM_SIZE 0x200000
+
+#define FLASH_PROTECT_BLOCK0 (0x0)
+#define FLASH_PROTECT_BLOCK8 (0x8)
+#define FLASH_PROTECT_BLOCK9 (0x9)
+#define FLASH_PROTECT_BLOCK10 (0xa)
+#define FLASH_PROTECT_BLOCK11 (0xb)
+
+#define RESERVE_AFTER_FIRST_BOOTROM_SIZE (0x200000)
+#define DDR_DIAGNOSE_START_ADRS ((FIRST_BOOTROM_ADRS) + (FIRST_BOOTROM_SIZE) + RESERVE_AFTER_FIRST_BOOTROM_SIZE)
+#define DDR_DIAGNOSE_LENGTH_ADRS (DDR_DIAGNOSE_START_ADRS + (0x4))
+
+#define SECOND_BOOTROM_ADRS ((FIRST_BOOTROM_ADRS) + (FIRST_BOOTROM_SIZE))
+#define SECOND_BOOTROM_SIZE 0x700000 //size of L2 BIOS
+#define BOARD_WORK_INFO_ADRS ((SECOND_BOOTROM_ADRS) + (SECOND_BOOTROM_SIZE))
+#define BOARD_WORK_INFO_SIZE (0x20000) /* 128K byte*/
+
+#define BOARD_HARD_INFO_ADRS ((BOARD_WORK_INFO_ADRS)+(BOARD_WORK_INFO_SIZE))
+#define BOARD_HARD_INFO_SIZE (0x20000) /* 128K byte*/
+
+#define BOARD_AGING_INFO_ADRS ((BOARD_HARD_INFO_ADRS)+(BOARD_HARD_INFO_SIZE))
+#define BOARD_AGING_INFO_SIZE (0x18000) /* 96K byte */
+
+#define BOARD_AGING_LOG_ADRS ((BOARD_AGING_INFO_ADRS)+(BOARD_AGING_INFO_SIZE))
+#define BOARD_AGING_LOG_SIZE (0x8000) /* 32K byte */
+#define BOARD_AGING_CHIP_LOG_SIZE (0x800)
+
+#define APPLICATION_INFO_ADRS ((BOARD_AGING_LOG_ADRS)+(BOARD_AGING_LOG_SIZE))
+#define APPLICATION_INFO_SIZE (0x60000) /* 128*3K byte */
+
+#define FLASH_BLOCK_RSV_ADDRS (APPLICATION_INFO_ADRS + APPLICATION_INFO_SIZE)
+#define FLASH_BLOCK_RSV_SIZE (0xc0000) /*128*6K byte*/
+
+#define BOARD_DRV_MEND_INFO_ADDRS (FLASH_BLOCK_RSV_ADDRS + FLASH_BLOCK_RSV_SIZE)
+#define BOARD_DRV_MEND_INFO_SIZE (0x80000) /*128*4K byte*/
+
+#define SECOND_BOOTROM_VALID_FLAG_ADDR (BOARD_WORK_INFO_ADRS + 0)
+#define SECOND_BOOTROM_VALID_FLAG_SIZE (0x04)
+#define SECOND_BOOTROM_VALID_FLAG_VALUE (0x5A5A5A5A)
+
+#define FLASH_BSP_PARA_START ((BOARD_WORK_INFO_ADRS) + 0x2000) //a00000+0xe0000
+#define FLASH_BSP_PARA_SIZE (0x2000)
+
+#define FAST_STARTUP_VALID_FLAG_ADDR (FLASH_BSP_PARA_START + FLASH_BSP_PARA_SIZE)
+#define FAST_STARTUP_VALID_FLAG_SIZE (0x04)
+#define FAST_STARTUP_VALID_FLAG_VALUE (0x5A5A5A5A)
+#define FAST_STARTUP_FILE_START_BLOCK_ADDR (FAST_STARTUP_VALID_FLAG_ADDR + FAST_STARTUP_VALID_FLAG_SIZE)
+#define FAST_STARTUP_FILE_START_BLOCK_SIZE (0x04)
+#define FAST_STARTUP_FILE_LENGTH_ADDR (FAST_STARTUP_FILE_START_BLOCK_ADDR + FAST_STARTUP_FILE_START_BLOCK_SIZE)
+#define FAST_STARTUP_FILE_LENGTH_SIZE (0x04)
+
+#define FLASH_UET_PARA_START (BOARD_HARD_INFO_ADRS) /*BOARD_HARD_INFO_ADRS*/
+
+#define FLASH_UET_PARA_SIZE 0x2000
+
+#define SIZE_4KB 0x00001000
+#define SIZE_2KB 0x00000800
+#define FLASH_TELNET_USER (FLASH_UET_PARA_START + FLASH_UET_PARA_SIZE -SIZE_4KB)
+#define FLASH_TELNET_USER_SIZE SIZE_2KB
+#define FLASH_TELNET_USER_SET_FLAG (FLASH_TELNET_USER +FLASH_TELNET_USER_SIZE)
+#define FLASH_TELNET_USER_SIZE SIZE_2KB
+#define FLASH_TELNET_FLAG 0x5a5aa6a6
+
+#define FLASH_CLOCK_PARA_START (APPLICATION_INFO_ADRS + 0x0)
+#define FLASH_CLOCK_PARA_SIZE 0x1000
+
+#define FLASH_NET_PARA_START (APPLICATION_INFO_ADRS + 0x20000)
+#define FLASH_NET_PARA_SIZE 0x1000
+
+#define FLASH_BSPLOG_PARA_START (FLASH_NET_PARA_START + 0x20000)
+#define FLASH_BSPLOG_PARA_SIZE 0x1000
+
+#define FLASH_UPPER_PARA_START (BOARD_DRV_MEND_INFO_ADDRS + BOARD_DRV_MEND_INFO_SIZE)
+#define FLASH_UPPER_PARA_SIZE 0x200000
+
+#define SECOND_BTRM_TEXT_START (FIRST_BOOTROM_ADRS + FIRST_BOOTROM_SIZE)
+
+#define STA_SRAM_MEM_BASE 0xe0000000//HDFINF_CpuBaseAddrAutoMatch(4) /*4=SRAM*/ /* 0x2ff00000 */
+#define STA_SRAM_MEM_SIZE (0x40000) /* 256K */
+
+#define CPU_RAM_USED_TOTAL_SIZE (0x200)
+#define CPU_RAM_USED_START_ADRS (STA_SRAM_MEM_BASE)
+
+#define CPU_RAM_START_TYPE_ADRS (CPU_RAM_USED_START_ADRS) /*addr : 0x2ff00000*/
+#define CPU_RAM_START_TYPE_SIZE (0x04)
+#define BOOTROM_LEVEL1_START_VALUE (1)
+#define BOOTROM_LEVEL2_START_VALUE (2)
+#define SAFE_VERSION_START_VALUE (0)
+#define FAST_VERSION_START_VALUE (3)
+
+#define CPU_RAM_RESET_FLAG_ADRS (CPU_RAM_START_TYPE_ADRS + CPU_RAM_START_TYPE_SIZE)/*addr : 0x2ff00004*/
+#define CPU_RAM_RESET_FLAG_SIZE (0x04)
+#define CPU_RAM_RESET_FLAG_VALUE (0x5A5A5A5A)
+#define CPU_PWR_RESET_FLAG_VALUE (0x4B4B)
+
+#define CPU_RAM_LOAD_IMAGE_ADRS (CPU_RAM_RESET_FLAG_ADRS + CPU_RAM_RESET_FLAG_SIZE) /*addr : 0x2ff00008*/
+#define CPU_RAM_LOAD_IMAGE_SIZE (0x04)
+
+#define CPU_RAM_EXAM_RESULT_ADRS (CPU_RAM_LOAD_IMAGE_ADRS + CPU_RAM_LOAD_IMAGE_SIZE)/*addr : 0x2ff0000c*/
+#define CPU_RAM_EXAM_RESULT_SIZE (40)
+
+#define CPU_RAM_SEC_BTRM_FAIL_FLAG_ADRS (CPU_RAM_EXAM_RESULT_ADRS + CPU_RAM_EXAM_RESULT_SIZE)
+#define CPU_RAM_SEC_BTRM_FAIL_FLAG_SIZE (0x04)
+#define CPU_RAM_SEC_BTRM_FAIL_FLAG_VALUE (0x5A5A5A5A)
+#define CPU_RAM_SEC_BTRM_FIRST_RUN_VALUE (0xb0aec7e9)
+
+#define CPU_RAM_SEC_BTRM_FAIL_COUNTER_ADRS ((CPU_RAM_SEC_BTRM_FAIL_FLAG_ADRS)+(CPU_RAM_SEC_BTRM_FAIL_FLAG_SIZE))
+#define CPU_RAM_SEC_BTRM_FAIL_COUNTER_SIZE (0x04)
+
+#define CPU_RAM_AGING_INFO_ADRS ((CPU_RAM_SEC_BTRM_FAIL_COUNTER_ADRS)+(CPU_RAM_SEC_BTRM_FAIL_COUNTER_SIZE))
+#define CPU_RAM_AGING_INFO_SIZE (0x48)
+
+#define CPU_AGING_STAT_ADRS ((CPU_RAM_AGING_INFO_ADRS)+(CPU_RAM_AGING_INFO_SIZE))/*addr : 0x2ff00084*/
+#define CPU_AGING_STAT_SIZE (0x4)
+#define CPU_AGING_STAT_VAL (0x5a5a5a5a)
+#define CPU_AGING_STAT_NO_VAL (0x00000000)
+
+#define CPU_HDF_VER_SELECT_ADRS ((CPU_AGING_STAT_ADRS)+(CPU_AGING_STAT_SIZE))/*addr : 0x2ff00088*/
+#define CPU_HDF_VER_SELECT_SIZE (0x4)
+
+#define CPU_RAM_DEC_WDT_TIME_ADDR ((CPU_HDF_VER_SELECT_ADRS) + CPU_HDF_VER_SELECT_SIZE)/*addr : 0x2ff0008c*/
+#define CPU_RAM_DEC_WDT_TIME_SIZE (0x4)
+
+#define CPU_RAM_UART_ADDR (CPU_RAM_DEC_WDT_TIME_ADDR + CPU_RAM_DEC_WDT_TIME_SIZE)/*addr : 0x2ff00090*/
+#define CPU_RAM_UART_SIZE (0x4)
+
+#define CPU_MBIST_AGING_INFO_ADRS (CPU_RAM_UART_ADDR + CPU_RAM_UART_SIZE) /*addr : 0xaff00094*/
+#define CPU_MBIST_AGING_INFO_SIZE (64)
+#define MEM_MANAGE_ADDR (CPU_RAM_UART_ADDR + CPU_RAM_UART_SIZE)/*addr : 0xaff00094*/
+#define MEM_MANAGE_SIZE (4*8)
+
+#define CPU_RAM_TEST_FAIL_COUNT_ADDR (MEM_MANAGE_ADDR+MEM_MANAGE_SIZE)/*0x2ff000b4*/
+#define CPU_RAM_TEST_FAIL_COUNT_SIZE (4)
+
+#define FAST_STARTUP_PROCESS_FLAG_ADDR (CPU_RAM_TEST_FAIL_COUNT_ADDR + CPU_RAM_TEST_FAIL_COUNT_SIZE)/*0x2ff000b8*/
+#define FAST_STARTUP_PROCESS_FLAG_SIZE (0x4)
+#define FAST_STARTUP_SUCCESS_FLAG (0x5a5a5a5a)
+#define FAST_STARTUP_FAIL_FLAG (0x4b4b4b4b)
+
+#define CPU_RAM_HDF_CURRENT_VERSION_ADDR (FAST_STARTUP_PROCESS_FLAG_ADDR + FAST_STARTUP_PROCESS_FLAG_SIZE) /*0x2ff000bc*/
+#define CPU_RAM_HDF_CURRENT_VERSION_SIZE (4)
+#define CPU_RAM_HDF_BAK_VERSION_MAGIC_FLAG (0xb5a4b5a4)
+
+#define CPU_RAM_HDF_RESOLVE_FAIL_COUNT_ADDR (CPU_RAM_HDF_CURRENT_VERSION_ADDR + CPU_RAM_HDF_CURRENT_VERSION_SIZE) /*0x2ff000c0*/
+#define CPU_RAM_HDF_RESOLVE_FAIL_COUNT_SIZE (4)
+
+
+
+
+
+#define MCLOAD_INFO_ADDR 0xaff000c4 /*addr : 0xaff000c4*/
+#define MClOAD_INFO_SIZE (12*8)
+
+
+#define CONTROL_SLAVE_STATUS_INFO 0xaff00124 /*addr : 0xaff00124*/
+#define CONTROL_SLAVE_STATUS_INFO_SIZE (4*8)
+
+#define CPU_RAM_WFI_STATUS_ADDR (CONTROL_SLAVE_STATUS_INFO + CONTROL_SLAVE_STATUS_INFO_SIZE)/*addr : 0xaff00144*/
+#define CPU_RAM_WFI_STATUS_SIZE (4*8)
+
+#define CPU_RAM_CONTROL_SLAVE_HART_BEAT_ADDR (CPU_RAM_WFI_STATUS_ADDR + CPU_RAM_WFI_STATUS_SIZE) /*addr : 0xaff00164*/
+#define CPU_RAM_CONTROL_SLAVE_HART_BEAT_SIZE (4*8)
+
+#define CPU_RAM_SLAVE_CORE_TYPE_ADDR (CPU_RAM_CONTROL_SLAVE_HART_BEAT_ADDR + CPU_RAM_CONTROL_SLAVE_HART_BEAT_SIZE)/*addr : 0xaff00184*/
+#define CPU_RAM_SLAVE_CORE_TYPE_SIZE (4)
+
+#define CPU_RAM_CLUSTER0_SCU_EN_FLAG_ADDR (CPU_RAM_SLAVE_CORE_TYPE_ADDR + CPU_RAM_SLAVE_CORE_TYPE_SIZE)/*0xaff00188*/
+#define CPU_RAM_CLUSTER0_SCU_EN_FLAG_SIZE (4)
+#define CPU_RAM_CLUSTER1_SCU_EN_FLAG_ADDR (CPU_RAM_CLUSTER0_SCU_EN_FLAG_ADDR + CPU_RAM_CLUSTER0_SCU_EN_FLAG_SIZE)/*0xaff0018c*/
+#define CPU_RAM_CLUSTER1_SCU_EN_FLAG_SIZE (4)
+
+#define CPU_RAM_SCU_EN_FLAG (0xaaaaaaaa)
+#define CPU_RAM_SCU_UNEN_FLAG (0xbbbbbbbb)
+
+#define CPU_RAM_SLAVE_CORE_RUN_COUNT_ADDR (CPU_RAM_CLUSTER1_SCU_EN_FLAG_ADDR+CPU_RAM_CLUSTER1_SCU_EN_FLAG_SIZE)/*0xaff00190*/
+#define CPU_RAM_SLAVE_CORE_RUN_COUNT_SIZE (4)
+
+#define CPU_RAM_CPU1_RST_SRC_ADDR (CPU_RAM_SLAVE_CORE_RUN_COUNT_ADDR+CPU_RAM_SLAVE_CORE_RUN_COUNT_SIZE)/*0xaff00194*/
+#define CPU_RAM_CPU1_RST_SRC_SIZE (4)
+
+#define CPU_RAM_SAVE_HIMEM_FLAG ((CPU_RAM_CPU1_RST_SRC_ADDR)+(CPU_RAM_CPU1_RST_SRC_SIZE)) /*0xaff00198*/
+#define CPU_RAM_SAVE_HIMEM_FLAG_SIZE (4)
+
+#define CPU_RAM_DDR_WRITE_LEVELING_FLAG ((CPU_RAM_SAVE_HIMEM_FLAG) + (CPU_RAM_SAVE_HIMEM_FLAG_SIZE)) /*0xaff0019c*/
+#define CPU_RAM_DDR_WRITE_LEVELING_SIZE 4
+
+#define CPU_RAM_IPI_BASE_ADDR (CPU_RAM_DDR_WRITE_LEVELING_FLAG + CPU_RAM_DDR_WRITE_LEVELING_SIZE) /* 0xAFF001A0 */
+#define CPU_RAM_IPI_SIZE (4* 8 * 8)
+
+#define CPU_RAM_STACK_ADRS (STA_SRAM_MEM_BASE + STA_SRAM_MEM_SIZE-0x100)
+
+#define FLASH_CPU_CHIP_INDEX 0
+#define FLASH_MAX_CHIP_INDEX FLASH_CPU_CHIP_INDEX
+
+
+
+/******************************************************************************
+Memory configuration
+*******************************************************************************/
+#define HDF_COPY_TO_DRAM_ADRS (0x900000)
+
+/*** RAM Information ***/
+#define BSP_LOG_SIZE (0x00080000)
+
+#define BSP_REPORT_MAX_SIZE (0x00010000)
+
+#define BSP_REALTIME_REPORT_ADDR (0x00020000)
+#define BSP_LASTWORD_REPORT_ADDR (0x00040000)
+
+#define BSP_FILESYS_RESERVED_ADDR (0x00030000)
+
+#define TASK_SWITCH_TRACE_BASEADDR (0x00050000+0x10)/*Addr=0x50000*/
+
+
+#define BSP_WARM_RESET_TABLE_ADRS (IMAGE_LOW_ADRS - 0x200)
+#define BSP_WARM_RESET_TABLE_SIZE 0X04
+#define BSP_WARM_RESET_TABLE_VALUE 0x3C5AA5C3
+
+#define BSP_SOFT_RESET_TABLE_ADRS (BSP_WARM_RESET_TABLE_ADRS + BSP_WARM_RESET_TABLE_SIZE)
+#define BSP_SOFT_RESET_TABLE_SIZE 0x04
+#define BSP_SOFT_RESET_TABLE_VALUE0 0xa5a5a5a5
+#define BSP_SOFT_RESET_TABLE_VALUE1 0x4b4b4b4b
+#define BSP_SOFT_RESET_TABLE_VALUE2 0
+
+#define BSP_1588_RESERVED_BEGIN (0x5ff800)
+#define BSP_1588_RESERVED_SIZE (2048)
+#define BSP_1588_RESERVED_END (0x600000)
+
+#define BSP_VECTOR_SAVE_BASEADDR (0)
+#define BSP_VECTOR_SAVE_SIZE (0)
+#define BSP_MEM_RECORD_BASEADDR (0x600000)
+#define BSP_MEM_RECORD_MAX_LEN (0x300000)
+#define BSP_MEM_RECORD_BAK_BASEADDR (0)
+#define BSP_MEM_RECORD_BAK_MAX_LEN (0)
+#define DEDICATED_TASKTCB_INFO_BASEADDR (0)
+#define DEDICATED_TASKTCB_INFO_MAX_LEN (0)
+#define ISR_STACK_INFO_BASEADDR (0)
+#define ISR_STACK_INFO_MAX_LEN (0)
+#define BOARD_REALTIME_RECORD_BASEADDR (0)
+#define BOARD_REALTIME_RECORD_MAX_LEN (0)
+
+#define HDF_RAM_MAPAREA_ADDR (0x900000)
+#define HDF_RAM_MAPAREA_SIZE (0x20000) /* 128K */
+
+#define FIQ_TASK_INFO_ADDR (0x920000)
+#define FIQ_STACK_ADDR (FIQ_TASK_INFO_ADDR + 0x4000)
+#define BOARD_NAME "MPTXb"
+#define SYS_CLK_FREQ (13000000)
+
+#define PENDING (0x0)
+#define RST_HANDLE (0x1)
+#define SYS_INIT (0x2)
+#define USR_INIT (0x3)
+#define USR_ROOT (0x4)
+#define RUNNING (0x5)
+#define INIT_START (0x1)
+#define RUN_NORMAL (0x2)
+#define INIT_FAIL (0x3)
+#define RUN_ABNORMAL (0x4)
+#define RUN_LOOP (0x5)
+#define STATUS_NULL (0x0)
+
+#define FE_ELE_NET_ID 0
+#define FE_DDI_NET_ID 1
+#define CBUS_NET_ID 2
+#define BACK_NET_ID 3
+#define MAX_NET_ID 4
+
+#define GE_IPADDR_ID 0
+#define TARGET_IPADDR_ID 1
+#define HOST_IPADDR_ID 2
+
+#define PORT_TYPE_DEBUG 0
+#define PORT_TYPE_CAN 1
+#define PORT_TYPE_TRAFFIC 2
+#define PORT_TYPE_BACK 3
+#define PORT_TYPE_MAX_NUM 3
+
+#define PORT_DEBUG_ID 0
+#define PORT_CAN_ID 0
+#define PORT_TRAFFIC_ID_0 0
+#define PORT_TRAFFIC_ID_1 1
+#define PORT_CAN_DEBUG_ID 0
+
+#define SC_SYSSTAT15 (HDFINF_CpuBaseAddrAutoMatch(CPU_SYSCTRL) + 0x444)
+#define SC_MSCPU_BIT (20)
+#define SC_MSCPU_MASK (0x1)
+#define PORT_INTERLINK_ID 0
+#define BSP_SLAVE_CPU_START_FLAG_ADDR 0x91b00000
+#define BSP_SLAVE_CPU_START_FLAG 0x5A6A7A8A
+#define BSP_MS_CPU_SHARE_ADDR 0x91b00004
+#define BSP_CPU1_FILELOAD_MEM_ADDR (0x92A00000)
+#define BSP_CPU1_FILELOAD_MEM_LEN (0x2400000)
+#define BSP_MAX_FILE_LENS_FOR_ONE_FILE (BSP_CPU1_FILELOAD_MEM_ADDR - BSP_MS_CPU_SHARE_ADDR)
+
+#define BSP_CPU1_FILELOAD_OK_FLAG 0x5A576767
+#define HDF_DDR_Addr (0x900000)
+#define L1_CACHE_MBIST_End 0xA5A5A5A5
+#define L1_CACHE_MBIST_FLAG 0x12345678
+#define L1_CACHE_MBIST_FLAG_B 0x87654321
+#define MBIST_CTRL_ADDR 0x2FF3FCC0
+#define MBIST_STRL_ADDR 0x2FF3FD00
+#define SRAM_HDF_WDT_FLAG1 0x2ff3fc00
+#define SRAM_HDF_WDT_FLAG2 0x2ff3fc04
+#define SRAM_HDF_WDT_FLAG3 0x2ff3fc08
+#ifdef __cplusplus
+}
+#endif
+#endif /* __BRDCOMMON_H */
+
diff --git a/HisiPkg/Include/Library/BspUartLib.h b/HisiPkg/Include/Library/BspUartLib.h new file mode 100644 index 000000000..3faca886d --- /dev/null +++ b/HisiPkg/Include/Library/BspUartLib.h @@ -0,0 +1,95 @@ +/*******************************************************************
+#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+
+#ifndef __BSP_UART_H
+#define __BSP_UART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+#include "Std.h"
+#define UART_SEND_DELAY (500000)
+
+#define SERIAL_0_BASE_ADR 0xe4007000
+#define UART_THR_REG (SERIAL_0_BASE_ADR + UART_RBR)
+#define UART_RBR_REG (SERIAL_0_BASE_ADR + UART_THR)
+#define UART_DLL_REG (SERIAL_0_BASE_ADR + UART_DLL)
+#define UART_DLH_REG (SERIAL_0_BASE_ADR + UART_DLH)
+#define UART_IEL_REG (SERIAL_0_BASE_ADR + UART_IEL)
+#define UART_IIR_REG (SERIAL_0_BASE_ADR + UART_IIR)
+#define UART_FCR_REG (SERIAL_0_BASE_ADR + UART_FCR)
+#define UART_LCR_REG (SERIAL_0_BASE_ADR + UART_LCR)
+#define UART_LSR_REG (SERIAL_0_BASE_ADR + UART_LSR)
+#define UART_USR_REG (SERIAL_0_BASE_ADR + UART_USR)
+
+#define UART_RBR 0x00
+#define UART_THR 0x00
+#define UART_DLL 0x00
+#define UART_DLH 0x04
+#define UART_IEL 0x04
+#define UART_IIR 0x08
+#define UART_FCR 0x08
+#define UART_LCR 0x0C
+#define UART_MCR 0x10
+#define UART_LSR 0x14
+#define UART_USR 0x7C
+
+/* register definitions */
+#define UART_FCR_EN 0x01
+#define UART_FCR_RXCLR 0x02
+#define UART_FCR_TXCLR 0x04
+#define UART_FCR_CLEARFIFO 0x00
+
+#define UART_LCR_DLAB 0x80
+#define UART_LCR_EPS 0x10
+#define UART_LCR_PEN 0x08
+#define UART_LCR_STOP 0x04
+#define UART_LCR_DLS8 0x03
+#define UART_LCR_DLS7 0x02
+#define UART_LCR_DLS6 0x01
+#define UART_LCR_DLS5 0x00
+
+#define UART_LSR_TEMT 0x40
+#define UART_LSR_THRE 0x20
+#define UART_LSR_BI 0x10
+#define UART_LSR_FE 0x08
+#define UART_LSR_PE 0x04
+#define UART_LSR_R 0x02
+#define UART_LSR_DR 0x01
+
+#define UART_USR_BUSY 0x01
+#define UART_USR_TFNF 0x02
+#define UART_USR_TFE 0x04
+#define UART_USR_RFNE 0x08
+#define UART_USR_RFF 0x10
+
+#define HI1210_SC_PRECTRL3 0x34
+#define HI1380_SC_PRECTRL1 0x20
+#define HI1380_SC_PRECTRL9 0x50
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+extern void BspSendChar(char scShowChar);
+extern char BspGetChar(U32 ulTimeout);
+
+#ifdef __cplusplus
+ }
+#endif /* __cplusplus */
+
+#endif /* __BSP_UART_H */
diff --git a/HisiPkg/Include/Library/EblProvisionLib.h b/HisiPkg/Include/Library/EblProvisionLib.h new file mode 100644 index 000000000..8dcc7ba18 --- /dev/null +++ b/HisiPkg/Include/Library/EblProvisionLib.h @@ -0,0 +1,59 @@ +/**********************************************************************
+#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#ifndef _PROVISION_PATH_H
+#define _PROVISION_PATH_H
+
+#include <Protocol/DevicePath.h>
+#include <Protocol/DevicePathToText.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Uefi/UefiBaseType.h>
+#include <Protocol/SimpleFileSystem.h>
+#include <Protocol/SimpleNetwork.h>
+
+typedef struct {
+ CHAR16 *Str;
+ UINTN Length;
+ UINTN Capacity;
+} POOL_PRINT;
+
+EFI_FILE_HANDLE
+LibOpenRoot (
+ IN EFI_HANDLE DeviceHandle
+ );
+
+EFI_STATUS
+EditHIInputStr (
+ IN OUT CHAR16 *CmdLine,
+ IN UINTN MaxCmdLine
+ );
+
+EFI_STATUS
+EditHIInputAscii (
+ IN OUT CHAR8 *CmdLine,
+ IN UINTN MaxCmdLine
+ );
+
+EFI_STATUS
+GetHIInputAscii (
+ IN OUT CHAR8 *CmdLine,
+ IN UINTN MaxCmdLine
+ );
+
+EFI_STATUS
+GetHIInputInteger (
+ OUT UINTN *Integer
+ );
+
+#endif
diff --git a/HisiPkg/Include/Library/PinIo_Api.h b/HisiPkg/Include/Library/PinIo_Api.h new file mode 100644 index 000000000..c11ba0c28 --- /dev/null +++ b/HisiPkg/Include/Library/PinIo_Api.h @@ -0,0 +1,60 @@ +#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#ifndef __PINIO_H__
+#define __PINIO_H__
+
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C"{
+#endif
+#endif /* __cplusplus */
+
+#include "Std.h"
+#ifndef INPUT_PIN
+#define INPUT_PIN 0
+#endif
+
+#ifndef OUTPUT_PIN
+#define OUTPUT_PIN 1
+#endif
+#ifndef OPEN_DRAIN
+#define OPEN_DRAIN 1
+#endif
+
+#ifndef NO_OPEN_DRAIN
+#define NO_OPEN_DRAIN 0
+#endif
+
+#ifndef LOW_LEVEL
+#define LOW_LEVEL 0
+#endif
+
+#ifndef HIGH_LEVEL
+#define HIGH_LEVEL 1
+#endif
+
+
+extern U32 GetPortLevel( U32 port, U32 pin );
+extern void PortInit( U32 port, U32 pin, U32 dir, U32 openDrain );
+extern void SetPortLevel( U32 port, U32 pin, U32 level );
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif
+#endif /* __cplusplus */
+
+
+#endif /* __PINIO_H__ */
diff --git a/HisiPkg/Include/Library/ResetWdtLib.h b/HisiPkg/Include/Library/ResetWdtLib.h new file mode 100644 index 000000000..6b157ad90 --- /dev/null +++ b/HisiPkg/Include/Library/ResetWdtLib.h @@ -0,0 +1,34 @@ +/*******************************************************************************
+#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#ifndef __WATCHDOG_RESET__
+#define __WATCHDOG_RESET__
+extern void Delay(unsigned long ulCount);
+extern void WDT_ResetWatchdog(void);
+
+#define GPIO_MASK(index) (0x1UL << index)
+
+#define GPIO3_BASE_ADDR 0xe4003000
+
+#define HIP04_IOPAD_REG 0xe400c000
+#define HIP04_WDOG_PORT 0x1A0 //GPIO98
+#define HIP04_SGMI_PORT 0x1AC //GPIO101
+#define HIP04_MII_PORT 0x1B0 //GPIO102
+#define HIP04_RST_PORT 0x1B4 //GPIO103
+
+#define writel_wdt(val,addr) ((*(volatile unsigned int *)(addr)) = (val))
+#define outl_wdt(val,addr) ((void) writel_wdt ((val),addr))
+#define readl_wdt(addr) (*(volatile unsigned int *)(addr))
+#define inl_wdt(addr) (readl_wdt(addr))
+
+#endif
diff --git a/HisiPkg/Include/Library/Std.h b/HisiPkg/Include/Library/Std.h new file mode 100644 index 000000000..60648477c --- /dev/null +++ b/HisiPkg/Include/Library/Std.h @@ -0,0 +1,147 @@ +/*******************************************************************
+#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+
+
+
+#ifndef __std_H
+#define __std_H
+
+
+#ifndef _ASMLANGUAGE
+
+typedef int STATUS;
+typedef int INT;
+typedef unsigned int size_t;
+
+typedef signed char S8;
+typedef signed short S16;
+typedef signed int S32;
+
+#ifndef VC_DEBUG_MODE
+typedef long long S64;
+#else
+typedef __int64 S64;
+#endif
+
+#ifndef U8
+typedef unsigned char U8;
+#endif
+
+#ifndef U16
+typedef unsigned short U16;
+#endif
+
+#ifndef U32
+typedef unsigned int U32;
+#endif
+
+#ifndef VC_DEBUG_MODE
+typedef unsigned long long U64;
+#else
+typedef unsigned __int64 U64;
+#endif
+
+#ifndef LONG
+typedef long LONG;
+#endif
+#ifndef CHAR
+typedef char CHAR;
+#endif
+
+typedef volatile unsigned char V8;
+typedef volatile unsigned short V16;
+typedef volatile unsigned int V32;
+
+#ifndef VC_DEBUG_MODE
+typedef volatile unsigned long long V64;
+#else
+typedef volatile unsigned __int64 V64;
+#endif
+
+#ifndef VC_DEBUG_MODE
+typedef char BYTE;
+#endif
+
+typedef unsigned char UBYTE;
+typedef short HWORD;
+typedef unsigned short UHWORD;
+
+#ifndef VC_DEBUG_MODE
+/*typedef long WORD;*/
+typedef unsigned long UWORD;
+#endif
+
+
+
+
+typedef volatile char VBYTE;
+typedef volatile unsigned char VUBYTE;
+typedef volatile short VHWORD;
+typedef volatile unsigned short VUHWORD;
+typedef volatile long VWORD;
+typedef volatile unsigned long VUWORD;
+
+#ifndef ERROR
+#define ERROR -1
+#endif
+
+#ifndef OK
+#define OK 0
+#endif
+#ifndef BOOL
+#define BOOL int
+#endif
+#ifndef BYTE_SWAP32
+#define BYTE_SWAP32(x) ((((unsigned)(x) & 0x000000ff) << 24) | \
+ (((x) & 0x0000ff00) << 8) | \
+ (((x) & 0x00ff0000) >> 8) | \
+ (((x) & 0xff000000) >> 24))
+#endif
+
+#ifndef BYTE_SWAP16
+#define BYTE_SWAP16(x) ((((x) & 0x00ff) <<8) | \
+ (((x) & 0xff00) >> 8))
+#endif
+#define CPU_RAM_HDF_BAK_VERSION_FLAG (0)
+#define CPU_RAM_HDF_MAIN_VERSION_FLAG (1)
+#define REG_WRITE(addr,data) (*(volatile UINT32 *)(addr) = (data))
+#define REG_READ(addr,data) ((data) = *(volatile UINT32 *)(addr))
+
+#define SYS_CTRL_REG_WRITE(offset,data) (REG_WRITE((offset), (data)))
+#define SYS_CTRL_REG_READ(offset,data) do \
+ { \
+ (REG_READ((offset), (data))); \
+ }while(0)
+#ifndef MEM_MMU_OFFSET
+//#define MEM_MMU_OFFSET 0x80000000
+#define MEM_MMU_OFFSET 0x00
+#endif
+#define NELEMENTS(array) (sizeof (array) / sizeof ((array) [0]))
+
+
+#define REG64(Addr) (*(volatile unsigned long long *)(Addr))
+#define REG32(Addr) (*(volatile unsigned int *)(Addr))
+#define REG16(Addr) (*(volatile unsigned short *)(Addr))
+#define REG8(Addr) (*(volatile unsigned char *)(Addr))
+
+U32 vxImmrGet (void);
+
+#endif
+
+#define SIZE_1 1
+#define SIZE_4 4
+#define SIZE_59 59
+#endif /* __std_H */
diff --git a/HisiPkg/Include/Library/SysUtilLib.h b/HisiPkg/Include/Library/SysUtilLib.h new file mode 100644 index 000000000..bf778f48f --- /dev/null +++ b/HisiPkg/Include/Library/SysUtilLib.h @@ -0,0 +1,41 @@ +/*************************************************************
+#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+#ifndef __SYS_UTIL_LIB__
+#define __SYS_UTIL_LIB__
+
+#include "Std.h"
+
+#define SC_PCB_BIT (16)
+#define SC_PCB_MASK (0xF)
+
+
+extern U32 GET_ClkFreq(U32* psysClkReg);
+extern U32 GET_InterTimerRefPreq(void);
+extern U32 BSP_GetStartBootNo(void);
+
+extern void TMBInit (void);
+extern void sysUsDelay(U32 delay);
+extern void delayUSec(U32 delay);
+extern U32 BSP_GetTimeBaseVal(U32 *pulTimeL, U32 *pulTimeH );
+extern U32 BSP_GetTimeBase(U32 *pulTimeL, U32 *pulTimeH );
+extern void TMB_Read(U32* pulValueHigh, U32* pulValueLow);
+extern int bUnzipPlus(
+ long lInputLen,
+ void* pInputBuf,
+ void* pOutputBuf,
+ long* plOutputLen,
+ long lCheckLen ,
+ char compresstype
+ );
+#endif
diff --git a/HisiPkg/Include/Library/config.h b/HisiPkg/Include/Library/config.h new file mode 100644 index 000000000..3911e236c --- /dev/null +++ b/HisiPkg/Include/Library/config.h @@ -0,0 +1,436 @@ +/* config.h - Mistral OMAP35xx configuration header */
+
+/*
+ * Copyright (c) 2008-2009 Wind River Systems, Inc.
+ * Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+ *
+ * The right to copy, distribute, modify or otherwise make use
+ * of this software may be licensed only pursuant to the terms
+ * of an applicable Wind River license agreement.
+ */
+
+/*
+modification history
+--------------------
+01f,25mar09,m_h add support for copyback cache & RTP
+01e,19mar09,m_h Cache is writethrough not copyback
+01d,19feb09,m_h cleanup
+01c,22jan09,m_h OneNand Flash Support
+01b,24nov08,m_h Configure to add networking
+01a,16jun08,m_h created.
+*/
+
+/*
+DESCRIPTION
+This module contains the configuration parameters for the Mistral OMAP35xx BSP.
+*/
+
+#ifndef __INCconfigh
+#define __INCconfigh
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* BSP version/revision identification, before configAll.h */
+
+#define BSP_VER_1_1 1 /* 1.2 is backwards compatible with 1.1 */
+#define BSP_VER_1_2 1
+#define BSP_VERSION "2.0"
+#define BSP_REV "/0" /* 0 for first revision */
+
+//#include <configAll.h>
+/*
+ * vxbus support
+ */
+#ifdef _BSP_BUILD_VXWORKS
+#define INCLUDE_VXBUS
+#else
+#undef INCLUDE_VXBUS
+#endif
+#ifdef INCLUDE_VXBUS
+#define INCLUDE_HWMEM_ALLOC
+#define INCLUDE_VXB_CMDLINE
+
+#define HWMEM_POOL_SIZE 50000
+
+#endif /* INCLUDE_VXBUS */
+
+/*
+ * SYS_MODEL define
+ *
+ */
+
+#define SYS_MODEL "HISILICON - CortexA9 (ARM)"
+
+
+/* Support network devices */
+#define INCLUDE_NET_DAEMON
+#undef INCLUDE_APPL_LOG_UTIL
+#undef INCLUDE_END2_LINKBUFPOOL
+
+#define DEFAULT_BOOT_LINE \
+ "HiFE(0,0)OMC:vxWorks.bin h=192.168.0.200 e=192.168.0.100 u=aa pw=123"
+
+
+
+#ifndef HDF_MASTER_CORE_FLAG
+#define HDF_MASTER_CORE_FLAG 0
+#define HDF_SLAVE_CORE_FLAG 1
+#define HDF_BOOTROM_COMPILE_FLAG 0
+#define HDF_VXWORKS_COMPILE_FLAG 1
+#endif
+
+
+
+
+
+/* Memory configuration */
+#undef LOCAL_MEM_AUTOSIZE /* run-time memory sizing */
+
+#ifndef _BSP_BUILD_VXWORKS
+#ifdef _CONTROL_SLAVE_CORE_IMG
+#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_SLAVE_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
+#else
+#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_MASTER_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
+#endif
+#else
+#ifdef _CONTROL_SLAVE_CORE_IMG
+#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_SLAVE_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
+#else
+#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_MASTER_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
+#endif
+#endif
+
+#define LOCAL_MEM_LOCAL_ADRS (0x0)
+
+
+
+#ifndef _BSP_BUILD_VXWORKS
+#ifdef _CONTROL_SLAVE_CORE_IMG
+#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_SLAVE_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
+#else
+#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_MASTER_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
+#endif
+#else
+#ifdef _CONTROL_SLAVE_CORE_IMG
+#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_SLAVE_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
+#else
+#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_MASTER_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
+#endif
+
+#endif
+#define LOCAL_MEM_END_ADRS (LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE)
+
+
+/*
+ * Boot ROM is an image written into Flash. Part of the Flash can be
+ * reserved for boot parameters etc. (see the Flash section below).
+ *
+ * The following parameters are defined here and in the Makefile.
+ * They must be kept synchronized; effectively config.h depends on Makefile.
+ * Any changes made here must be made in the Makefile and vice versa.
+ *
+ * ROM_BASE_ADRS is the base of the Flash ROM/EPROM.
+ * ROM_TEXT_ADRS is the entry point of the VxWorks image
+ * ROM_SIZE is the size of the part of the Flash ROM/EPROM allocated to
+ * the VxWorks image (block size - size of headers)
+ *
+ * Two other constants are used:
+ * ROM_COPY_SIZE is the size of the part of the ROM to be copied into RAM
+ * (e.g. in uncompressed boot ROM)
+ * ROM_SIZE_TOTAL is the size of the entire Flash ROM (used in sysPhysMemDesc)
+ *
+ * The values are given as literals here to make it easier to ensure
+ * that they are the same as those in the Makefile.
+ */
+
+#undef RAM_LOW_ADRS
+#undef RAM_HIGH_ADRS
+
+#define IMAGE_LOW_ADRS 0x00a00000
+
+/* VxWorks entry link address */
+#define VXWORKS_ENTRY IMAGE_LOW_ADRS
+
+#ifdef _CONTROL_SLAVE_CORE_IMG
+#define RAM_LOW_ADRS 0x00200000 /* VxWorks image entry point */
+#define RAM_HIGH_ADRS 0x03000000 /* RAM address for ROM boot */
+
+#else
+
+#ifndef _BSP_BUILD_VXWORKS
+#define ROM_BASE_ADRS (HDFINF_GetTextBase())
+#define ROM_TEXT_ADRS (HDFINF_GetTextBase())
+#define RAM_LOW_ADRS 0x05000000 /* VxWorks image entry point */
+#define RAM_HIGH_ADRS 0x06000000 /* RAM address for ROM boot */
+#else
+#define ROM_BASE_ADRS 0x40200000 /* base of Flash/EPROM */
+#define ROM_TEXT_ADRS 0x40200000 /* code start addr in ROM */
+#define RAM_LOW_ADRS IMAGE_LOW_ADRS /* VxWorks image entry point */
+#define RAM_HIGH_ADRS 0x05000000 /* RAM address for ROM boot */
+#endif
+
+#endif
+
+#undef ROM_SIZE
+#define ROM_SIZE 0x00200000 /* size of ROM holding VxWorks*/
+
+
+/*
+ * Flash/NVRAM memory configuration
+ *
+ * A block of the Flash memory (FLASH_SIZE bytes at FLASH_ADRS) is
+ * reserved for non-volatile storage of data.
+ *
+ */
+
+#undef INCLUDE_FLASH
+
+/* Serial port configuration */
+
+#define N_SIO_CHANNELS 3
+
+#undef NUM_TTY
+#define NUM_TTY N_SIO_CHANNELS
+
+#define DEFAULT_BAUD (HDF_GetUartBaudRate())
+
+/* Console baud rate reconfiguration. */
+#undef CONSOLE_BAUD_RATE
+#define CONSOLE_BAUD_RATE DEFAULT_BAUD /* Reconfigure default baud rate */
+
+/*
+ * Define SERIAL_DEBUG to enable debugging
+ * via the serial ports
+ */
+
+#undef SERIAL_DEBUG
+#undef INCLUDE_BOOT_WDB
+
+#undef INCLUDE_WDB
+
+
+
+#if defined(INCLUDE_WDB) || defined (INCLUDE_BOOT_WDB)
+# undef WDB_COMM_TYPE
+# undef WDB_TTY_BAUD
+# undef WDB_TTY_CHANNEL
+# undef WDB_TTY_DEV_NAME
+# ifdef SERIAL_DEBUG
+# define WDB_NO_BAUD_AUTO_CONFIG
+# define WDB_COMM_TYPE WDB_COMM_SERIAL /* WDB in Serial mode */
+# define WDB_TTY_BAUD 38400 /* Baud rate for WDB Connctn */
+# define WDB_TTY_CHANNEL 1 /* COM PORT #2 */
+# define WDB_TTY_DEV_NAME "/tyCo/1" /* deflt TYCODRV_5_2 dev name */
+# else /* SERIAL_DEBUG */
+# define WDB_COMM_TYPE WDB_COMM_END
+# define WDB_TTY_BAUD DEFAULT_BAUD /* Baud rate for WDB Connctn */
+# define WDB_TTY_CHANNEL 0 /* COM PORT #1 */
+# define WDB_TTY_DEV_NAME "/tyCo/0" /* deflt TYCODRV_5_2 dev name */
+# endif /* SERIAL_DEBUG */
+#endif /* INCLUDE_WDB || INCLUDE_BOOT_WDB */
+
+
+/*
+ * We use the generic architecture libraries, with caches/MMUs present. A
+ * call to sysHwInit0() is needed from within usrInit before
+ * cacheLibInit() is called.
+ */
+
+/*
+ * Cache/MMU configuration
+ *
+ * Note that when MMU is enabled, cache modes are controlled by
+ * the MMU table entries in sysPhysMemDesc[], not the cache mode
+ * macros defined here.
+ */
+#define SYS_CACHE_UNCACHED_ADRS 0xffffffff/*OMAP35XX_L4_MPU_INTC*/
+
+# undef USER_I_CACHE_MODE
+# define USER_I_CACHE_MODE CACHE_COPYBACK
+
+# undef USER_D_CACHE_MODE
+# define USER_D_CACHE_MODE CACHE_COPYBACK
+
+
+/* Include MMU BASIC and CACHE support for command line and project builds */
+
+# define INCLUDE_MMU_BASIC
+# define INCLUDE_BOOT_MMU_BASIC
+# define INCLUDE_CACHE_SUPPORT
+
+#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
+# define INCLUDE_MMU
+#endif /* INCLUDE_MMU_BASIC || INCLUDE_MMU_FULL */
+
+/* Include MMU BASIC and CACHE support for command line and project builds */
+
+# define INCLUDE_MMU_BASIC
+# define INCLUDE_BOOT_MMU_BASIC
+# define INCLUDE_CACHE_SUPPORT
+
+#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
+# define INCLUDE_MMU
+#endif /* INCLUDE_MMU_BASIC || INCLUDE_MMU_FULL */
+
+#ifndef MEM_MMU_OFFSET
+#define MEM_MMU_OFFSET 0x00
+#endif
+
+/*
+ * Network driver configuration.
+ *
+ * De-select unused (default) network drivers selected in configAll.h.
+ */
+
+#undef INCLUDE_ENP /* include CMC Ethernet interface*/
+#undef INCLUDE_EX /* include Excelan Ethernet interface */
+#undef INCLUDE_SM_NET /* include backplane net interface */
+#undef INCLUDE_SM_SEQ_ADDR /* shared memory network auto address setup */
+
+#define INCLUDE_IPCOM_USE_AUTH_RADIUS
+
+
+/* Enhanced Network Driver (END) Support */
+
+#define INCLUDE_END
+
+#ifdef INCLUDE_END
+# ifndef SERIAL_DEBUG
+# define WBD_AGENT_END
+# else
+# undef WBD_AGENT_END
+# endif /* SERIAL_DEBUG */
+
+#endif /* INCLUDE_END */
+
+#ifdef _BSP_BUILD_VXWORKS
+#ifndef _CONTROL_SLAVE_CORE_IMG
+#if 1
+#define INCLUDE_USB
+#define INCLUDE_USB_INIT
+
+/*ehci*/
+#define INCLUDE_EHCI
+#define INCLUDE_EHCI_INIT
+#define INCLUDE_EHCI_BUS
+
+/*ohci*/
+#define INCLUDE_OHCI
+#define INCLUDE_OHCI_INIT
+#define INCLUDE_OHCI_BUS
+
+/*MASS STORGY device*/
+#define INCLUDE_USB_MS_BULKONLY
+#define INCLUDE_USB_MS_BULKONLY_INIT
+#define INCLUDE_USB_MS_CBI
+#define INCLUDE_USB_MS_CBI_INIT
+#define INCLUDE_NOR_FILESYS
+#endif
+#endif
+#endif
+
+#define INCLUDE_BSP_WATCHDOG
+
+#ifdef _CONTROL_SLAVE_CORE_IMG
+#undef _INCLUDE_FILESYS
+#else
+#define _INCLUDE_FILESYS
+#endif
+
+#undef INCLUDE_TFFS
+
+#ifdef _CONTROL_SLAVE_CORE_IMG
+#undef INCLUDE_DOSFS
+#else
+/*define for FS*/
+#define INCLUDE_DOSFS
+#endif
+
+#define INCLUDE_XBD_RAMDRV /*ramDisk*/
+
+#ifdef INCLUDE_DOSFS
+#define INCLUDE_ERF
+#define INCLUDE_DEVICE_MANAGER
+#define INCLUDE_FS_EVENT_UTIL
+#define INCLUDE_FS_MONITOR
+#define INCLUDE_XBD
+#define INCLUDE_XBD_BLK_DEV
+#define INCLUDE_XBD_TRANS
+#define INCLUDE_DOSFS_DIR_FIXED
+#define INCLUDE_DOSFS_DIR_VFAT
+#define INCLUDE_DOSFS_FAT
+#define INCLUDE_DOSFS_FMT
+#define INCLUDE_DOSFS_CHKDSK
+#define INCLUDE_DOSFS_MAIN
+#endif /* INCLUDE_DOSFS*/
+
+/* I2C not supported */
+#undef INCLUDE_I2C
+
+/* touch screen not supported */
+#undef INCLUDE_TOUCHSCREEN
+
+/*
+ * Interrupt mode. Preemptive interrupts are not supported by the interrupt
+ * driver so INT_MODE must be set to INT_NON_PREEMPT_MODEL.
+ */
+
+#define INT_MODE INT_NON_PREEMPT_MODEL
+
+/*
+ * miscellaneous definitions
+ * Note: ISR_STACK_SIZE is defined here rather than in ../all/configAll.h
+ * (as is more usual) because the stack size depends on the interrupt
+ * structure of the BSP.
+ */
+
+#define ISR_STACK_SIZE 0x2000 /* size of ISR stack, in bytes */
+
+/* Optional timestamp support */
+
+#undef INCLUDE_TIMESTAMP /* define to include timestamp driver */
+#define INCLUDE_TIMESTAMP
+
+#ifndef INCLUDE_LOADER
+#define INCLUDE_LOADER
+#endif
+#ifndef INCLUDE_LOADER_HOOKS
+#define INCLUDE_LOADER_HOOKS
+#endif
+#ifndef INCLUDE_PTYDRV
+#define INCLUDE_PTYDRV /* pseudo terminal driver */
+#endif
+/*script*/
+#ifndef INCLUDE_STARTUP_SCRIPT
+#define INCLUDE_STARTUP_SCRIPT
+#endif
+
+
+#define INCLUDE_SHELL_INTERP_C /* C interpreter */
+#define INCLUDE_SHELL_INTERP_CMD /* shell command interpreter */
+
+#undef SHELL_COMPATIBLE
+#define SHELL_COMPATIBLE TRUE
+
+#ifndef BSP_BUILD_BASIC_BTRM
+#define INCLUDE_RAWFS
+#define INCLUDE_XBD_RAMDRV
+#endif
+#ifndef _CONTROL_SLAVE_CORE_IMG
+#ifdef _BSP_BUILD_VXWORKS
+#define INCLUDE_SECURITY
+#endif
+#endif
+#ifdef INCLUDE_SECURITY
+#define LOGIN_USER_NAME "target"
+#endif
+
+#include "BrdCommon.h"
+//#include "configExtend.h"
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __INCconfigh */
diff --git a/HisiPkg/Include/Platform/ArmPlatform.h b/HisiPkg/Include/Platform/ArmPlatform.h new file mode 100644 index 000000000..3943384e8 --- /dev/null +++ b/HisiPkg/Include/Platform/ArmPlatform.h @@ -0,0 +1,192 @@ +/** @file
+* Header defining Versatile Express constants (Base addresses, sizes, flags)
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __ARM_D01_H__
+#define __ARM_D01_H__
+
+#define IS_PRIMARY_CORE(MpId) (((MpId) & PcdGet32(PcdArmPrimaryCoreMask)) == PcdGet32(PcdArmPrimaryCore))
+
+
+/***********************************************************************************
+// Motherboard memory-mapped peripherals
+************************************************************************************/
+
+// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)
+#define ARM_VE_SYS_ID_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00000)
+#define ARM_VE_SYS_SW_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00004)
+#define ARM_VE_SYS_LED_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00008)
+#define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
+#define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
+#define ARM_VE_SYS_FLAGS_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00034)
+#define ARM_VE_SYS_FLAGS_NV_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
+#define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
+#define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)
+#define ARM_VE_SYS_FLASH (ARM_VE_BOARD_PERIPH_BASE + 0x0004C)
+#define ARM_VE_SYS_CFGSWR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00058)
+#define ARM_VE_SYS_MISC (ARM_VE_BOARD_PERIPH_BASE + 0x00060)
+#define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00084)
+#define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00088)
+#define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)
+#define ARM_VE_SYS_CFGCTRL_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)
+#define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)
+
+// SP810 Controller
+#ifndef SP810_CTRL_BASE
+#define SP810_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x01000)
+#endif
+
+// PL111 Colour LCD Controller - motherboard
+#define PL111_CLCD_MOTHERBOARD_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x1F000)
+#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
+
+// VRAM offset for the PL111 Colour LCD Controller on the motherboard
+#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)
+
+#define ARM_VE_SYS_PROC_ID_HBI 0xFFF
+#define ARM_VE_SYS_PROC_ID_MASK (UINT32)(0xFFU << 24)
+#define ARM_VE_SYS_PROC_ID_UNSUPPORTED (UINT32)(0xFFU << 24)
+#define ARM_VE_SYS_PROC_ID_CORTEX_A9 (UINT32)(0x0CU << 24)
+#define ARM_VE_SYS_PROC_ID_CORTEX_A5 (UINT32)(0x12U << 24)
+#define ARM_VE_SYS_PROC_ID_CORTEX_A15 (UINT32)(0x14U << 24)
+
+// Boot Master Select:
+// 0 = Site 1 boot master
+// 1 = Site 2 boot master
+#define ARM_VE_SYS_MISC_MASTERSITE (1 << 14)
+//
+// Sites where the peripheral is fitted
+//
+#define ARM_VE_UNSUPPORTED ~0
+#define ARM_VE_MOTHERBOARD_SITE 0
+#define ARM_VE_DAUGHTERBOARD_1_SITE 1
+#define ARM_VE_DAUGHTERBOARD_2_SITE 2
+
+#define VIRTUAL_SYS_CFG(site,func) (((site) << 24) | (func))
+
+//
+// System Configuration Control Functions
+//
+#define SYS_CFG_OSC 1
+#define SYS_CFG_VOLT 2
+#define SYS_CFG_AMP 3
+#define SYS_CFG_TEMP 4
+#define SYS_CFG_RESET 5
+#define SYS_CFG_SCC 6
+#define SYS_CFG_MUXFPGA 7
+#define SYS_CFG_SHUTDOWN 8
+#define SYS_CFG_REBOOT 9
+#define SYS_CFG_DVIMODE 11
+#define SYS_CFG_POWER 12
+// Oscillator for Site 1
+#define SYS_CFG_OSC_SITE1 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_1_SITE,SYS_CFG_OSC)
+// Oscillator for Site 2
+#define SYS_CFG_OSC_SITE2 VIRTUAL_SYS_CFG(ARM_VE_DAUGHTERBOARD_2_SITE,SYS_CFG_OSC)
+// Can not access the battery backed-up hardware clock on the Versatile Express motherboard
+#define SYS_CFG_RTC VIRTUAL_SYS_CFG(ARM_VE_UNSUPPORTED,1)
+
+//
+// System ID
+//
+// All RTSM VE models have the same System ID : 0x225F500
+//
+// FVP models have a different System ID.
+// Default Base model System ID : 0x00201100
+// [31:28] Rev - Board revision: 0x0 = Rev A
+// [27:16] HBI - HBI board number in BCD: 0x020 = v8 Base Platform
+// [15:12] Variant - Build variant of board: 0x1 = Variant B. (GIC 64k map)
+// [11:8] Plat - Platform type: 0x1 = Model
+// [7:0] FPGA - FPGA build, BCD coded: 0x00
+//
+//HBI = 010 = Foundation Model
+//HBI = 020 = Base Platform
+//
+// And specifically, the GIC register banks start at the following
+// addresses:
+// Variant = 0 Variant = 1
+//GICD 0x2c001000 0x2f000000
+//GICC 0x2c002000 0x2c000000
+//GICH 0x2c004000 0x2c010000
+//GICV 0x2c006000 0x2c020000
+
+// The default SYS_IDs. These can be changed when starting the model.
+#define ARM_RTSM_SYS_ID (0x225F500)
+#define ARM_FVP_BASE_SYS_ID (0x00201100)
+#define ARM_FVP_FOUNDATION_SYS_ID (0x00101100)
+
+#define ARM_FVP_SYS_ID_VARIANT_MASK (UINT32)(0xFUL << 12)
+
+
+
+/***********************************************************************************
+// Platform Memory Map
+************************************************************************************/
+
+// Can be NOR0, NOR1, DRAM
+#define ARM_VE_REMAP_BASE 0x00000000
+#define ARM_VE_REMAP_SZ SIZE_64MB
+
+// Motherboard Peripheral and On-chip peripheral
+#define ARM_VE_BOARD_PERIPH_BASE 0x1C010000
+
+// NOR Flash 1
+// There is typo in the reference manual for the Base address of NOR Flash 1
+#define ARM_VE_SMB_NOR0_BASE 0x08000000
+#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
+// NOR Flash 2
+#define ARM_VE_SMB_NOR1_BASE 0x0C000000
+#define ARM_VE_SMB_NOR1_SZ SIZE_64MB
+// SRAM
+#define ARM_VE_SMB_SRAM_BASE 0x2E000000
+#define ARM_VE_SMB_SRAM_SZ SIZE_64KB
+// USB, Ethernet, VRAM
+#define ARM_VE_SMB_PERIPH_BASE 0x18000000
+#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE
+#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB
+
+// DRAM
+#define ARM_VE_DRAM_BASE PcdGet32 (PcdSystemMemoryBase)
+#define ARM_VE_DRAM_SZ PcdGet32 (PcdSystemMemorySize)
+
+// This can be any value since we only support motherboard PL111
+#define LCD_VRAM_CORE_TILE_BASE 0x00000000
+
+// On-chip peripherals (Snoop Control Unit etc...)
+#define ARM_VE_ON_CHIP_PERIPH_BASE 0x2C000000
+// Note: The TRM says not all the peripherals are implemented
+#define ARM_VE_ON_CHIP_PERIPH_SZ SIZE_256MB
+
+
+// External AXI between daughterboards (Logic Tile)
+#define ARM_VE_EXT_AXI_BASE 0x2E010000 // Not modelled
+#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */
+
+/***********************************************************************************
+// Memory-mapped peripherals
+************************************************************************************/
+
+// SP810 Controller
+#undef SP810_CTRL_BASE
+#define SP810_CTRL_BASE 0x1C020000
+
+// PL111 Colour LCD Controller
+#define PL111_CLCD_SITE ARM_VE_MOTHERBOARD_SITE
+#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
+#define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1
+
+// VRAM offset for the PL111 Colour LCD Controller on the motherboard
+#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)
+
+#endif
diff --git a/HisiPkg/Include/Ppi/.gitignore b/HisiPkg/Include/Ppi/.gitignore new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/HisiPkg/Include/Ppi/.gitignore diff --git a/HisiPkg/Include/Protocol/LinuxAtagListProtocol.h b/HisiPkg/Include/Protocol/LinuxAtagListProtocol.h new file mode 100644 index 000000000..0c95a748a --- /dev/null +++ b/HisiPkg/Include/Protocol/LinuxAtagListProtocol.h @@ -0,0 +1,178 @@ +/*****************************************************************
+#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#ifndef _LINUX_ATAG_LIST_PROTOCOL_H_
+#define _LINUX_ATAG_LIST_PROTOCOL_H_
+
+typedef struct {
+ UINT32 flags;
+ UINT32 pagesize;
+ UINT32 rootdev;
+} LINUX_ATAG_CORE;
+
+typedef struct {
+ UINT32 size;
+ UINTN start;
+} LINUX_ATAG_MEM;
+
+typedef struct {
+ UINT8 x;
+ UINT8 y;
+ UINT16 video_page;
+ UINT8 video_mode;
+ UINT8 video_cols;
+ UINT16 video_ega_bx;
+ UINT8 video_lines;
+ UINT8 video_isvga;
+ UINT16 video_points;
+} LINUX_ATAG_VIDEOTEXT;
+
+typedef struct {
+ UINT32 flags;
+ UINT32 size;
+ UINTN start;
+} LINUX_ATAG_RAMDISK;
+
+typedef struct {
+ UINT32 start;
+ UINT32 size;
+} LINUX_ATAG_INITRD2;
+
+typedef struct {
+ UINT32 low;
+ UINT32 high;
+} LINUX_ATAG_SERIALNR;
+
+typedef struct {
+ UINT32 rev;
+} LINUX_ATAG_REVISION;
+
+typedef struct {
+ UINT16 lfb_width;
+ UINT16 lfb_height;
+ UINT16 lfb_depth;
+ UINT16 lfb_linelength;
+ UINT32 lfb_base;
+ UINT32 lfb_size;
+ UINT8 red_size;
+ UINT8 red_pos;
+ UINT8 green_size;
+ UINT8 green_pos;
+ UINT8 blue_size;
+ UINT8 blue_pos;
+ UINT8 rsvd_size;
+ UINT8 rsvd_pos;
+} LINUX_ATAG_VIDEOLFB;
+
+typedef struct {
+ CHAR8 cmdline[255];
+} LINUX_ATAG_CMDLINE;
+
+typedef struct {
+ UINT32 addr;
+} LINUX_ATAG_BOOT_CMD;
+
+typedef struct {
+ UINT32 invalid;
+} LINUX_ATAG_CPUINFO;
+
+typedef struct {
+ UINT32 size; /* length of tag in words including this header */
+ UINT32 type; /* tag type */
+} LINUX_ATAG_HEADER;
+
+typedef VOID (*LINUX_KERNEL)(UINT32 Zero, UINT32 Arch, UINTN ParametersBase);
+
+//
+// ATAG Definitions
+//
+
+#define ATAG_MAX_SIZE 0x3000
+
+/* ATAG : list of possible tags */
+#define ATAG_NONE 0x00000000
+#define ATAG_CORE 0x54410001
+#define ATAG_MEM 0x54410002
+#define ATAG_VIDEOTEXT 0x54410003
+#define ATAG_RAMDISK 0x54410004
+#define ATAG_INITRD2 0x54420005
+#define ATAG_SERIAL 0x54410006
+#define ATAG_REVISION 0x54410007
+#define ATAG_VIDEOLFB 0x54410008
+#define ATAG_CMDLINE 0x54410009
+#define ATAG_ARM_MP_CORE 0x5441000A
+
+#define ATAG_BOOT_CMD 0x5aa50001
+#define ATAG_CPUINFO 0x5aa50002
+
+#define next_tag_address(t) ((LINUX_ATAG*)((UINT32)(t) + (UINT32)(SwapBytes32((UINT32)((t)->header.size))<<2)))
+#define tag_size(type) ((UINT32)((sizeof(LINUX_ATAG_HEADER) + sizeof(type)) >> 2))
+
+typedef struct {
+ LINUX_ATAG_HEADER header;
+ union {
+ LINUX_ATAG_CORE core_tag;
+ LINUX_ATAG_MEM mem_tag;
+ LINUX_ATAG_VIDEOTEXT videotext_tag;
+ LINUX_ATAG_RAMDISK ramdisk_tag;
+ LINUX_ATAG_INITRD2 initrd2_tag;
+ LINUX_ATAG_SERIALNR serialnr_tag;
+ LINUX_ATAG_REVISION revision_tag;
+ LINUX_ATAG_VIDEOLFB videolfb_tag;
+ LINUX_ATAG_CMDLINE cmdline_tag;
+ LINUX_ATAG_BOOT_CMD bootcmd_tag;
+ LINUX_ATAG_CPUINFO cpuinfo_tag;
+ } body;
+} LINUX_ATAG;
+
+typedef struct _LINUX_ATAG_LIST_PROTOCOL LINUX_ATAG_LIST_PROTOCOL;
+
+typedef struct
+{
+ LINUX_ATAG_CORE core_tag;
+ LINUX_ATAG_MEM mem_tag;
+ LINUX_ATAG_VIDEOTEXT videotext_tag;
+ LINUX_ATAG_RAMDISK ramdisk_tag;
+ LINUX_ATAG_INITRD2 initrd2_tag;
+ LINUX_ATAG_SERIALNR serialnr_tag;
+ LINUX_ATAG_REVISION revision_tag;
+ LINUX_ATAG_VIDEOLFB videolfb_tag;
+ LINUX_ATAG_CMDLINE cmdline_tag;
+ LINUX_ATAG_BOOT_CMD bootcmd_tag;
+ LINUX_ATAG_CPUINFO cpuinfo_tag;
+} LINUX_ATAG_LIST;
+
+typedef
+EFI_STATUS
+(EFIAPI *GET_LINUX_ATAG_LIST) (
+ IN LINUX_ATAG_LIST_PROTOCOL *This,
+ IN OUT LINUX_ATAG_LIST *LinuxAtagList
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *SET_LINUX_ATAG_LIST) (
+ IN LINUX_ATAG_LIST_PROTOCOL *This,
+ IN LINUX_ATAG_LIST *LinuxAtagList
+ );
+
+typedef struct _LINUX_ATAG_LIST_PROTOCOL
+{
+ GET_LINUX_ATAG_LIST GetLinuxAtagList;
+ SET_LINUX_ATAG_LIST SetLinuxAtagList;
+} LINUX_ATAG_LIST_PROTOCOL;
+
+extern EFI_GUID gLinuxAtagListProtocolGuid;
+
+#endif
diff --git a/HisiPkg/Include/Protocol/NandFlashProtocol.h b/HisiPkg/Include/Protocol/NandFlashProtocol.h new file mode 100644 index 000000000..f26d3d08d --- /dev/null +++ b/HisiPkg/Include/Protocol/NandFlashProtocol.h @@ -0,0 +1,127 @@ +/*******************************************************************
+#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+#ifndef __NANDDRIVER_H__
+#define __NANDDRIVER_H__
+
+
+
+//
+// GUID for EFI HFFS Driver Protocol
+//
+#define EFI_NAND_DRIVER_PROTOCOL_GUID \
+ {0xf355bcc3, 0x252d, 0x4dee, 0xad, 0x05, 0x94, 0xbb, 0x29, 0xc8, 0x4d, 0x46}
+
+
+typedef struct _EFI_NAND_DRIVER_PROTOCOL EFI_NAND_DRIVER_PROTOCOL;
+
+#if 1
+typedef struct NAND_CMD_INFO
+{
+ UINT32 ulPageSize; /* Page size */
+ UINT32 ulBlockSize; /* Block size */
+ UINT32 ulEndBlockNum;
+}NAND_CMD_INFO_STRU;
+#endif
+
+
+typedef
+UINT32 ( *EFI_NAND_DRIVER_INIT)
+(
+ IN EFI_NAND_DRIVER_PROTOCOL *This
+);
+
+typedef
+UINT32 ( *EFI_NAND_DRIVER_ERASE)
+(
+ IN EFI_NAND_DRIVER_PROTOCOL *This,
+ IN UINT32 ulBlockNum
+);
+
+typedef
+UINT32 ( *EFI_NAND_DRIVER_WRITE)
+(
+ IN EFI_NAND_DRIVER_PROTOCOL *This,
+ IN UINT32 ulChunkNum,
+ IN UINT32 ulOffsetInChunk,
+ IN UINT32 ulLength,
+ IN UINT8* pucData
+);
+
+typedef
+UINT32 ( *EFI_NAND_DRIVER_READ)
+(
+ IN EFI_NAND_DRIVER_PROTOCOL *This,
+ IN UINT32 ulChunkNum,
+ IN UINT32 ulOffsetInChunk,
+ IN UINT32 ulLength,
+ OUT UINT8* pucData
+);
+
+typedef
+UINT32 ( *EFI_NAND_DRIVER_WRITEECC)
+(
+ IN EFI_NAND_DRIVER_PROTOCOL *This,
+ IN UINT32 ulChunkNum,
+ IN UINT32 ulOffsetInChunk,
+ IN UINT32 ulLength,
+ IN UINT8* pucData
+);
+
+typedef
+UINT32 ( *EFI_NAND_DRIVER_READECC)
+(
+IN EFI_NAND_DRIVER_PROTOCOL *This,
+ IN UINT32 ulChunkNum,
+ IN UINT32 ulOffsetInChunk,
+ IN UINT32 ulLength,
+ OUT UINT8* pucData,
+ IN OUT UINT32* pulBitFlip
+);
+
+typedef
+UINT32 ( *EFI_NAND_DRIVER_READSPARE)
+(
+ IN EFI_NAND_DRIVER_PROTOCOL *This,
+ IN UINT32 ulChunkNum,
+ IN UINT32 ulOffsetInChunk,
+ IN UINT32 ulLength,
+ OUT UINT8* pucData
+);
+
+typedef
+NAND_CMD_INFO_STRU ( *EFI_NAND_DRIVER_GETCMDINFO)
+(
+ IN EFI_NAND_DRIVER_PROTOCOL *This
+);
+
+
+
+
+
+typedef struct _EFI_NAND_DRIVER_PROTOCOL {
+ EFI_NAND_DRIVER_INIT NandFlashInit;
+ EFI_NAND_DRIVER_ERASE NandFlashErase;
+ EFI_NAND_DRIVER_WRITE NandFlashWrite;
+ EFI_NAND_DRIVER_READ NandFlashRead;
+ EFI_NAND_DRIVER_WRITEECC NandFlashWriteEcc;
+ EFI_NAND_DRIVER_READECC NandFlashReadEcc;
+ EFI_NAND_DRIVER_READSPARE NandFlashReadSpare;
+ EFI_NAND_DRIVER_GETCMDINFO NandFlashGetCMDInfo;
+} EFI_NAND_DRIVER_PROTOCOL;
+
+extern EFI_GUID gNANDDriverProtocolGuid;
+
+#endif
diff --git a/HisiPkg/Include/Protocol/NorFlashProtocol.h b/HisiPkg/Include/Protocol/NorFlashProtocol.h new file mode 100644 index 000000000..11e64d37a --- /dev/null +++ b/HisiPkg/Include/Protocol/NorFlashProtocol.h @@ -0,0 +1,101 @@ +/*******************************************************************
+#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+#ifndef _NOR_FLASH_PROTOCOL_H_
+#define _NOR_FLASH_PROTOCOL_H_
+#include <Uefi/UefiBaseType.h>
+
+#define UNI_NOR_FLASH_PROTOCOL_GUID \
+ {0x86F305EA, 0xDFAC, 0x4A6B, {0x92, 0x77, 0x47, 0x31, 0x2E, 0xCE, 0x42, 0xA}}
+
+typedef struct _UNI_NOR_FLASH_PROTOCOL UNI_NOR_FLASH_PROTOCOL;
+
+typedef struct {
+ UINT32 ManufacturerID;
+ UINT32 DeviceID;
+ UINT32 FlashSize;
+ UINT32 BlockSize;
+ UINT8 ParallelNum;
+ UINT8 SeriesNum;
+ UINT32 Base;
+}NOR_FLASH_INFO_TABLE;
+
+
+typedef
+EFI_STATUS
+(EFIAPI *UNI_FLASH_ERASE_INTERFACE) (
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT32 Length
+ );
+typedef
+EFI_STATUS
+(EFIAPI *UNI_FLASH_WRITE_INTERFACE) (
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT8 *Buffer,
+ UINT32 ulLength
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *UNI_FLASH_READ_INTERFACE) (
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN OUT UINT8 *Buffer,
+ IN UINT32 ulLen
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *UNI_FLASH_GetFlashInfo_INTERFACE) (
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ OUT NOR_FLASH_INFO_TABLE *FlashInfo
+ );
+
+typedef
+EFI_STATUS
+(EFIAPI *UNI_FLASH_DIRECT_WRITE_INTERFACE) (
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 Offset,
+ IN UINT8 *Buffer,
+ UINT32 ulLength
+ );
+typedef
+EFI_STATUS
+(EFIAPI *UNI_FLASH_GET_MANUID_INTERFACE) (
+ IN UNI_NOR_FLASH_PROTOCOL *This,
+ IN UINT32 *ManuID
+ );
+
+typedef
+VOID
+(EFIAPI *UNI_FLASH_CHECK_PROTECT_INTERFACE) (
+ IN UNI_NOR_FLASH_PROTOCOL *This
+);
+
+struct _UNI_NOR_FLASH_PROTOCOL {
+ UNI_FLASH_ERASE_INTERFACE Erase;
+ UNI_FLASH_WRITE_INTERFACE Write;
+ UNI_FLASH_READ_INTERFACE Read;
+ UNI_FLASH_GetFlashInfo_INTERFACE GetFlashInfo;
+ UNI_FLASH_CHECK_PROTECT_INTERFACE CheckFlashProtectFlag;
+ UNI_FLASH_DIRECT_WRITE_INTERFACE DirectWrite;
+ UNI_FLASH_GET_MANUID_INTERFACE GetManuID;
+};
+
+extern EFI_GUID gUniNorFlashProtocolGuid;
+
+#endif
diff --git a/HisiPkg/Include/Protocol/WatchDogProtocol.h b/HisiPkg/Include/Protocol/WatchDogProtocol.h new file mode 100644 index 000000000..44f09cbf8 --- /dev/null +++ b/HisiPkg/Include/Protocol/WatchDogProtocol.h @@ -0,0 +1,61 @@ +/***************************************************************
+#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#ifndef _WATCH_DOG_PROTOCOL_H_
+#define _WATCH_GOG_PROTOCOL_H_
+
+#define OEM_WATCH_DOG_PROTOCOL_GUID \
+ {0x707ac059, 0xf335, 0x4643, 0xa6, 0x99, 0x5e, 0x3b, 0x9b, 0x82, 0x60, 0x74}
+
+
+typedef struct _OEM_WATCH_DOG_PROTOCOL OEM_WATCH_DOG_PROTOCOL;
+
+typedef
+EFI_STATUS
+(EFIAPI * WATCH_DOG_AUTO_CLEAR_START)(void);
+
+typedef
+EFI_STATUS
+(EFIAPI * WATCH_DOG_AUTO_CLEAR_STOP)(void);
+
+typedef
+EFI_STATUS
+(EFIAPI * WATCH_DOG_FEED_TIME_EXTEND)(UINT32 ulMin);
+
+typedef
+EFI_STATUS
+(EFIAPI * WATCH_DOG_FEED_TIME_RESTORE)(UINT32 ulMin);
+typedef
+VOID
+(EFIAPI * WATCH_DOG_DIAGNOSE_MODE_ENTER)(void);
+
+typedef
+VOID
+(EFIAPI * WATCH_DOG_DIAGNOSE_MODE_EXIT)(void);
+
+
+typedef struct _OEM_WATCH_DOG_PROTOCOL
+{
+ WATCH_DOG_AUTO_CLEAR_START WtdAutoClearStart;
+ WATCH_DOG_AUTO_CLEAR_STOP WtdAutoClearStop;
+ WATCH_DOG_FEED_TIME_EXTEND WtdFeedTimeExtend;
+ WATCH_DOG_FEED_TIME_RESTORE WtdFeedTimeRestore;
+ WATCH_DOG_DIAGNOSE_MODE_ENTER WtdDiagnoseModeEnter;
+ WATCH_DOG_DIAGNOSE_MODE_EXIT WtdDiagnoseModeExit;
+
+} OEM_WATCH_DOG_PROTOCOL;
+
+#define GLOBAL_VARIABLE_WTD_OF_TIME L"WTDOverFlowTime"
+
+#endif
diff --git a/HisiPkg/Library/BspUartLib/BspUartLib.c b/HisiPkg/Library/BspUartLib/BspUartLib.c new file mode 100644 index 000000000..7c313d300 --- /dev/null +++ b/HisiPkg/Library/BspUartLib/BspUartLib.c @@ -0,0 +1,159 @@ +/*******************************************************************
+#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+#include "BspUartLib.h"
+#include "BrdCommon.h"
+#include "config.h"
+#include <Library/DebugLib.h>
+#include <Library/ResetWdtLib.h>
+#include <Library/DebugLib.h>
+
+
+#define BSP_UartDelay(loop) delayuart(2 * loop)
+void delayuart(unsigned long ulCount)
+{
+ unsigned int ulRet, ulNumber;
+ for(ulRet = 0; ulRet < 2; ulRet++)
+ {
+ ulNumber = ulCount;
+ while ( ulNumber-- )
+ {
+ ;
+ }
+ }
+}
+
+
+UINT8 ROM_UartChkSndEnd(void)
+{
+ if(!(*(volatile UINT8 *)UART_LSR_REG & UART_LSR_THRE))
+ {
+ WDT_ResetWatchdog();
+ return 0;
+ }
+ else
+ {
+ return 1;
+ }
+}
+
+void ROM_UartSendChar(UINT8 scShowChar)
+{
+ UINT32 i = 0;
+
+ while(i < UART_SEND_DELAY)
+ {
+ WDT_ResetWatchdog();
+ if ((*(volatile UINT8 *)(UART_USR_REG) & UART_USR_TFNF) == UART_USR_TFNF)
+ {
+ break;
+ }
+ i++;
+ }
+
+ *(volatile UINT8 *)(UART_THR_REG) = scShowChar;
+
+
+ i = 0;
+ while (i < UART_SEND_DELAY)
+ {
+ if (ROM_UartChkSndEnd())
+ {
+ break;
+ }
+ i++;
+ }
+
+ return;
+
+}
+
+void BspSendUintHex(register UINT32 ulData)
+{
+ INT8 Buff[8];
+ INT32 i;
+ UINT32 uTemp = 0x0f;
+
+ for(i = 0; i < 8; i++)
+ {
+ Buff[i] = ((INT8)(ulData & uTemp));
+ ulData = ulData >> 4;
+ }
+
+ ROM_UartSendChar('0');
+ ROM_UartSendChar('x');
+
+ for(i = 0; i < 8; i++)
+ {
+ if(Buff[7 - i] < (char)10)
+ {
+ Buff[7 - i] += '0';
+ ROM_UartSendChar(Buff[7 - i]);
+ }
+ else
+ {
+ Buff[7 - i] = Buff[7 - i] - 10 + 'A';
+ ROM_UartSendChar(Buff[7-i]);
+ }
+ }
+ return;
+
+}
+
+void BspSendString(char *pShow)
+{
+ if( NULL == pShow)
+ {
+ return;
+ }
+ while( *((char *)pShow) )
+ {
+ WDT_ResetWatchdog();
+ ROM_UartSendChar( * ( (char *) pShow ) );
+ pShow++;
+ }
+ return;
+}
+
+char BspGetChar(UINT32 ulTimeOut)
+{
+ UINT32 i = 0;
+ register UINT8 recvchar = 0;
+ for(;;)
+ {
+ if ((*(UINT8 *)(UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR)
+ {
+ break;
+ }
+ WDT_ResetWatchdog();
+
+ if (i > ulTimeOut)
+ {
+ WDT_ResetWatchdog();
+ return recvchar;
+ }
+
+ BSP_UartDelay(10000);
+
+ i++;
+ }
+ recvchar = (*(volatile UINT8 *)(UART_RBR_REG));
+
+ *(volatile UINT8 *)(UART_THR_REG) = recvchar;
+
+ return recvchar;
+}
+
+
diff --git a/HisiPkg/Library/BspUartLib/BspUartLib.inf b/HisiPkg/Library/BspUartLib/BspUartLib.inf new file mode 100644 index 000000000..4b02b7bb5 --- /dev/null +++ b/HisiPkg/Library/BspUartLib/BspUartLib.inf @@ -0,0 +1,41 @@ +#/** @file
+#
+# Component discription file for NorFlashDxe module
+#
+# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BspUartLib
+ FILE_GUID = 16D53EE6-7EA6-47bd-8E2F-511FD9BCABF0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BspUartLib
+
+
+[Sources.common]
+ BspUartLib.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ HisiPkg/HisiPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ DebugAgentLib
+ ResetWdtLib
+
diff --git a/HisiPkg/Library/PinIoLib/PinIo.c b/HisiPkg/Library/PinIoLib/PinIo.c new file mode 100644 index 000000000..ce4882958 --- /dev/null +++ b/HisiPkg/Library/PinIoLib/PinIo.c @@ -0,0 +1,38 @@ +/***************************************************************************
+#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#include "PinIo_Api.h"
+#include "config.h"
+extern void D01_PortInit( U32 ulPortNo, U32 ulPinNo, U32 ulDir, U32 ulOpenDrain );
+extern void D01_SetPortLevel( U32 ulPortNo, U32 ulPinNo, U32 ulLevel );
+extern U32 D01_GetPortLevel( U32 ulPortNo, U32 ulPinNo );
+
+#define BSP_OUTPUT 0
+#define BSP_INPUT 1
+
+void PortInit( U32 ulPortNo, U32 ulPinNo, U32 ulDir, U32 ulOpenDrain )
+{
+ D01_PortInit(ulPortNo, ulPinNo, ulDir,ulOpenDrain);
+}
+
+void SetPortLevel( U32 ulPortNo, U32 ulPinNo, U32 ulLevel)
+{
+ /*lint -e553*/
+ D01_SetPortLevel(ulPortNo, ulPinNo, ulLevel);
+}
+U32 GetPortLevel( U32 ulPortNo, U32 ulPinNo )
+{
+ return D01_GetPortLevel(ulPortNo, ulPinNo);
+}
+
diff --git a/HisiPkg/Library/PinIoLib/PinIoLib.inf b/HisiPkg/Library/PinIoLib/PinIoLib.inf new file mode 100644 index 000000000..276e0805a --- /dev/null +++ b/HisiPkg/Library/PinIoLib/PinIoLib.inf @@ -0,0 +1,43 @@ +#/** @file
+#
+# Component discription file for NorFlashDxe module
+#
+# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PinIoLib
+ FILE_GUID = 16D53EC6-7EA6-47Cd-8E2F-512FD9BCA2F0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PinIoLib
+
+
+[Sources.common]
+ PinIo.c
+ PinIo_D01.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ HisiPkg/HisiPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+
+[FixedPcd]
+ gHwTokenSpaceGuid.PcdGPIO0Base
+
+
diff --git a/HisiPkg/Library/PinIoLib/PinIo_D01.c b/HisiPkg/Library/PinIoLib/PinIo_D01.c new file mode 100644 index 000000000..ba0aa16b0 --- /dev/null +++ b/HisiPkg/Library/PinIoLib/PinIo_D01.c @@ -0,0 +1,98 @@ +/************************************************************
+#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#include "PinIo_Api.h"
+#include "PinIo_D01.h"
+#ifndef ERROR
+#define ERROR -1
+#endif
+
+
+extern U32 rom_int_lock(void);
+
+extern void rom_int_unlock(U32 ulLock);
+
+void D01_PortInit( U32 ulPortNo, U32 ulPinNo, U32 ulDir, U32 ulOpenDrain )
+{
+ U32 ulRegVal = 0;
+ HI_CPU_GPIO_REG_READ(ulPortNo,HI_CPU_GPIO_INT_EN_REG,ulRegVal);
+ ulRegVal &= ~ulPinNo;
+ HI_CPU_GPIO_REG_WRITE(ulPortNo,HI_CPU_GPIO_INT_EN_REG,ulRegVal);
+
+ HI_CPU_GPIO_REG_READ(ulPortNo,HI_CPU_GPIO_DIR_REG,ulRegVal);
+ if (OUTPUT_PIN == ulDir)
+ {
+ ulRegVal |= ulPinNo;
+ }
+ else
+ {
+ ulRegVal &= ~ulPinNo;
+ }
+ HI_CPU_GPIO_REG_WRITE(ulPortNo,HI_CPU_GPIO_DIR_REG,ulRegVal);
+
+ return;
+}
+
+void D01_SetPortLevel( U32 ulPortNo, U32 ulPinNo, U32 ulLevel )
+{
+ U32 ulRegVal = 0;
+ U32 ulLock = 0;
+
+ ulLock = rom_int_lock();
+ HI_CPU_GPIO_REG_READ(ulPortNo,HI_CPU_GPIO_OUTPUT_REG,ulRegVal);
+ if (LOW_LEVEL == ulLevel)
+ {
+ ulRegVal &= ~ulPinNo;
+ }
+ else
+ {
+ ulRegVal |= ulPinNo;
+ }
+ HI_CPU_GPIO_REG_WRITE(ulPortNo,HI_CPU_GPIO_OUTPUT_REG,ulRegVal);
+
+
+ HI_CPU_GPIO_REG_READ(ulPortNo,HI_CPU_GPIO_DIR_REG,ulRegVal);
+ ulRegVal |= ulPinNo;
+ HI_CPU_GPIO_REG_WRITE(ulPortNo,HI_CPU_GPIO_DIR_REG,ulRegVal);
+
+ HI_CPU_GPIO_REG_READ(ulPortNo,HI_CPU_GPIO_OUTPUT_REG,ulRegVal);
+ if (LOW_LEVEL == ulLevel)
+ {
+ ulRegVal &= ~ulPinNo;
+ }
+ else
+ {
+ ulRegVal |= ulPinNo;
+ }
+ HI_CPU_GPIO_REG_WRITE(ulPortNo,HI_CPU_GPIO_OUTPUT_REG,ulRegVal);
+ rom_int_unlock(ulLock);
+}
+U32 D01_GetPortLevel( U32 ulPortNo, U32 ulPinNo )
+{
+ U32 ulRegVal = 0;
+ HI_CPU_GPIO_REG_READ(ulPortNo,HI_CPU_GPIO_DIR_REG,ulRegVal);
+ ulRegVal &= ~ulPinNo;
+ HI_CPU_GPIO_REG_WRITE(ulPortNo,HI_CPU_GPIO_DIR_REG,ulRegVal);
+
+ HI_CPU_GPIO_REG_READ(ulPortNo,HI_CPU_GPIO_INPUT_REG,ulRegVal);
+
+ if (ulRegVal&ulPinNo)
+ {
+ return HIGH_LEVEL;
+ }
+ else
+ {
+ return LOW_LEVEL;
+ }
+}
diff --git a/HisiPkg/Library/PinIoLib/PinIo_D01.h b/HisiPkg/Library/PinIoLib/PinIo_D01.h new file mode 100644 index 000000000..1d85e6c4c --- /dev/null +++ b/HisiPkg/Library/PinIoLib/PinIo_D01.h @@ -0,0 +1,115 @@ +/*****************************************************************
+#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C"{
+#endif
+#endif /* __cplusplus */
+
+#ifndef _PINIO_HI1380_H_
+#define _PINIO_HI1380_H_
+#include <Library/PcdLib.h>
+#ifndef HIGH_LEVEL
+#define HIGH_LEVEL 1
+#endif
+#ifndef LOW_LEVEL
+#define LOW_LEVEL 0
+#endif
+
+#ifndef INPUT_PIN
+#define INPUT_PIN 0
+#endif
+#ifndef OUTPUT_PIN
+#define OUTPUT_PIN 1
+#endif
+
+#define HI1380_GPIO_PORT_NUM 2
+#define HI1380_GPIO0 0
+#define HI1380_GPIO1 1
+
+
+#define HI1210_GPIO_PORT_NUM 4
+#define HI1210_GPIO0 0
+#define HI1210_GPIO1 1
+#define HI1210_GPIO2 2
+#define HI1210_GPIO3 3
+
+
+#define GPIO0 0x00000001
+#define GPIO1 0x00000002
+#define GPIO2 0x00000004
+#define GPIO3 0x00000008
+#define GPIO4 0x00000010
+#define GPIO5 0x00000020
+#define GPIO6 0x00000040
+#define GPIO7 0x00000080
+#define GPIO8 0x00000100
+#define GPIO9 0x00000200
+#define GPIO10 0x00000400
+#define GPIO11 0x00000800
+#define GPIO12 0x00001000
+#define GPIO13 0x00002000
+#define GPIO14 0x00004000
+#define GPIO15 0x00008000
+#define GPIO16 0x00010000
+#define GPIO17 0x00020000
+#define GPIO18 0x00040000
+#define GPIO19 0x00080000
+#define GPIO20 0x00100000
+#define GPIO21 0x00200000
+#define GPIO22 0x00400000
+#define GPIO23 0x00800000
+#define GPIO24 0x01000000
+#define GPIO25 0x02000000
+#define GPIO26 0x04000000
+#define GPIO27 0x08000000
+#define GPIO28 0x10000000
+#define GPIO29 0x20000000
+#define GPIO30 0x40000000
+#define GPIO31 0x80000000
+
+
+#define HI_CPU_GPIO_BASE PcdGet32(PcdGPIO0Base)
+
+#define HI_CPU_GPIO_OUTPUT_REG (0x0)
+#define HI_CPU_GPIO_DIR_REG (0x4)
+#define HI_CPU_GPIO_PORT_CTRL_REG (0x8)
+#define HI_CPU_GPIO_INT_EN_REG (0x30)
+#define HI_CPU_GPIO_INT_MASK_REG (0x34)
+#define HI_CPU_GPIO_INT_TYPE_REG (0x38)
+#define HI_CPU_GPIO_INT_POLARITY (0x3c)
+#define HI_CPU_GPIO_INT_CLR_REG (0x4c)
+#define HI_CPU_GPIO_INPUT_REG (0x50)
+#define HI_CPU_GPIO_SYNC_REG (0x60)
+
+#define HI_CPU_GPIO_REG_READ(port,reg,val)\
+{\
+ val = *(volatile U32 *)(HI_CPU_GPIO_BASE + (port)*0x1000 + (reg));\
+}
+
+#define HI_CPU_GPIO_REG_WRITE(port,reg,val)\
+{\
+ *(volatile U32 *)(HI_CPU_GPIO_BASE + (port)*0x1000 + (reg)) = (val);\
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif
+#endif /* __cplusplus */
+
+#endif
+
diff --git a/HisiPkg/Library/SerialPortLib/SerialPortLib.c b/HisiPkg/Library/SerialPortLib/SerialPortLib.c new file mode 100644 index 000000000..93cf04ad0 --- /dev/null +++ b/HisiPkg/Library/SerialPortLib/SerialPortLib.c @@ -0,0 +1,311 @@ +/** @file
+ UART Serial Port library functions
+
+ Copyright (c) 2006 - 2009, Intel Corporation
+ All rights reserved.
+ Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/SerialPortLib.h>
+#include "SerialPortLib.h"
+#include <Uefi/UefiBaseType.h>
+#include <Protocol/SerialIo.h>
+
+VOID SerialInit(VOID)
+{
+ UINT32 ulUartClkFreq;
+
+ *(volatile UINT32 *)(UART_LCR_REG) = UART_LCR_DLS8;
+
+ *(volatile UINT32 *)(UART_FCR_REG) = UART_FCR_EN | UART_FCR_RXCLR | UART_FCR_TXCLR;
+
+ *(volatile UINT32 *)(UART_LCR_REG) = UART_LCR_DLAB | UART_LCR_DLS8;
+
+ ulUartClkFreq = TCXO_CLK_FREQ;
+
+ *(volatile UINT32 *)(UART_DLL_REG) = (ulUartClkFreq / (16 * BAUDRATE) ) & 0xff;
+ *(volatile UINT32 *)(UART_DLH_REG) = ((ulUartClkFreq/ (16 * BAUDRATE) ) >> 8 ) & 0xff;
+
+ *(volatile UINT32 *)(UART_LCR_REG) = UART_LCR_DLS8;
+
+ *(volatile UINT32 *)(UART_IEL_REG) = 0x00;
+
+ *(volatile UINT32 *)(UART_THR_REG) = 0x53;
+
+ return ;
+
+}
+
+
+/**
+ Initialize the serial device hardware.
+
+ If no initialization is required, then return RETURN_SUCCESS.
+ If the serial device was successfuly initialized, then return RETURN_SUCCESS.
+ If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
+
+ @retval RETURN_SUCCESS The serial device was initialized.
+ @retval RETURN_DEVICE_ERROR The serail device could not be initialized.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ )
+{
+ return RETURN_SUCCESS;
+}
+
+
+UINT8 UART_ChkSndEnd(VOID)
+{
+ if(!(*(UINT8 *)UART_LSR_REG & UART_LSR_THRE))
+ {
+ return 0;
+ }
+ else
+ {
+ return 1;
+ }
+}
+
+/**
+ Write data from buffer to serial device.
+
+ Writes NumberOfBytes data bytes from Buffer to the serial device.
+ The number of bytes actually written to the serial device is returned.
+ If the return value is less than NumberOfBytes, then the write operation failed.
+
+ If Buffer is NULL, then ASSERT().
+
+ If NumberOfBytes is zero, then return 0.
+
+ @param Buffer Pointer to the data buffer to be written.
+ @param NumberOfBytes Number of bytes to written to the serial device.
+
+ @retval 0 NumberOfBytes is 0.
+ @retval >0 The number of bytes written to the serial device.
+ If this value is less than NumberOfBytes, then the read operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+)
+{
+ UINTN Result;
+
+ if (Buffer == NULL) {
+ return 0;
+ }
+
+ Result = NumberOfBytes;
+
+ while (NumberOfBytes--) {
+
+ SerialPortWriteChar(*Buffer);
+ Buffer++;
+ }
+
+ return Result;
+}
+
+
+/**
+ Reads data from a serial device into a buffer.
+
+ @param Buffer Pointer to the data buffer to store the data read from the serial device.
+ @param NumberOfBytes Number of bytes to read from the serial device.
+
+ @retval 0 NumberOfBytes is 0.
+ @retval >0 The number of bytes read from the serial device.
+ If this value is less than NumberOfBytes, then the read operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+)
+{
+ UINTN Result;
+
+ if (NULL == Buffer) {
+ return 0;
+ }
+
+ Result = NumberOfBytes;
+
+ while (NumberOfBytes--) {
+ //
+ // Wait for the serail port to be ready.
+ //
+ *Buffer=SerialPortReadChar();
+ Buffer++ ;
+ }
+
+ return Result;
+}
+
+/**
+ Polls a serial device to see if there is any data waiting to be read.
+
+ Polls aserial device to see if there is any data waiting to be read.
+ If there is data waiting to be read from the serial device, then TRUE is returned.
+ If there is no data waiting to be read from the serial device, then FALSE is returned.
+
+ @retval TRUE Data is waiting to be read from the serial device.
+ @retval FALSE There is no data waiting to be read from the serial device.
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ )
+{
+ return (BOOLEAN) ((*(volatile UINT8 *)(UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR);
+
+}
+
+VOID SerialPortWriteChar(UINT8 scShowChar)
+{
+ UINT32 ulLoop = 0;
+
+ while(ulLoop < UART_SEND_DELAY)
+ {
+ if ((*(volatile UINT8 *)(UART_USR_REG) & UART_FCR_RXCLR) == UART_FCR_RXCLR)
+ {
+ break;
+ }
+
+ ulLoop++;
+ }
+ *(volatile UINT8 *)(UART_THR_REG) = (UINT8)scShowChar;
+
+ ulLoop = 0;
+ while(ulLoop < UART_SEND_DELAY)
+ {
+ if ((*(volatile UINT8 *)(UART_USR_REG) & UART_FCR_TXCLR) == UART_FCR_TXCLR)
+ {
+ break;
+ }
+ ulLoop++;
+ }
+
+ return;
+}
+
+
+UINT8 SerialPortReadChar(VOID)
+{
+ UINT8 recvchar = 0;
+
+ do
+ {
+ if ((*(volatile UINT8 *)(UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR)
+ {
+ break;
+ }
+ }while(1);
+
+ recvchar = (*(volatile UINT8 *)(UART_RBR_REG));
+
+ return recvchar;
+}
+
+/**
+ Set new attributes to PL011.
+
+ @param BaudRate The baud rate of the serial device. If the baud rate is not supported,
+ the speed will be reduced down to the nearest supported one and the
+ variable's value will be updated accordingly.
+ @param ReceiveFifoDepth The number of characters the device will buffer on input. If the specified
+ value is not supported, the variable's value will be reduced down to the
+ nearest supported one.
+ @param Timeout If applicable, the number of microseconds the device will wait
+ before timing out a Read or a Write operation.
+ @param Parity If applicable, this is the EFI_PARITY_TYPE that is computer or checked
+ as each character is transmitted or received. If the device does not
+ support parity, the value is the default parity value.
+ @param DataBits The number of data bits in each character
+ @param StopBits If applicable, the EFI_STOP_BITS_TYPE number of stop bits per character.
+ If the device does not support stop bits, the value is the default stop
+ bit value.
+
+ @retval EFI_SUCCESS All attributes were set correctly on the serial device.
+ @retval EFI_INVALID_PARAMETERS One or more of the attributes has an unsupported value.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetAttributes (
+ IN UINT64 BaudRate,
+ IN UINT32 ReceiveFifoDepth,
+ IN UINT32 Timeout,
+ IN EFI_PARITY_TYPE Parity,
+ IN UINT8 DataBits,
+ IN EFI_STOP_BITS_TYPE StopBits
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Set the serial device control bits.
+
+ @param Control Control bits which are to be set on the serial device.
+
+ @retval EFI_SUCCESS The new control bits were set on the serial device.
+ @retval EFI_UNSUPPORTED The serial device does not support this operation.
+ @retval EFI_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetControl (
+ IN UINT32 Control
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Get the serial device control bits.
+
+ @param Control Control signals read from the serial device.
+
+ @retval EFI_SUCCESS The control bits were read from the serial device.
+ @retval EFI_DEVICE_ERROR The serial device is not functioning correctly.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortGetControl (
+ OUT UINT32 *Control
+ )
+{
+
+ if (SerialPortPoll ()) {
+ // If a character is pending don't set EFI_SERIAL_INPUT_BUFFER_EMPTY
+ *Control = EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+ } else {
+ *Control = EFI_SERIAL_INPUT_BUFFER_EMPTY | EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+ }
+ return EFI_SUCCESS;
+ //return EFI_UNSUPPORTED;
+}
+
diff --git a/HisiPkg/Library/SerialPortLib/SerialPortLib.h b/HisiPkg/Library/SerialPortLib/SerialPortLib.h new file mode 100644 index 000000000..b8f6f599c --- /dev/null +++ b/HisiPkg/Library/SerialPortLib/SerialPortLib.h @@ -0,0 +1,109 @@ +/*******************************************************************
+#
+#
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+#ifndef __HISIARM_SERIAL_PORT__
+#define __HISIARM_SERIAL_PORT__
+
+#include <Library/PcdLib.h>
+#define UART_USED_CHANNELS 1
+#define TCXO_CLK_FREQ 168750000
+#define SERIAL_0_BASE_ADR 0xe4007000
+#define REG_VAL (*(UINT32 *)0x118) & 0xffff
+#define UART_SEND_DELAY 500000
+#define BAUDRATE 115200
+
+
+#define UART_THR_REG (SERIAL_0_BASE_ADR + UART_RBR)
+#define UART_RBR_REG (SERIAL_0_BASE_ADR + UART_THR)
+#define UART_DLL_REG (SERIAL_0_BASE_ADR + UART_DLL)
+#define UART_DLH_REG (SERIAL_0_BASE_ADR + UART_DLH)
+#define UART_IEL_REG (SERIAL_0_BASE_ADR + UART_IEL)
+#define UART_IIR_REG (SERIAL_0_BASE_ADR + UART_IIR)
+#define UART_FCR_REG (SERIAL_0_BASE_ADR + UART_FCR)
+#define UART_LCR_REG (SERIAL_0_BASE_ADR + UART_LCR)
+#define UART_LSR_REG (SERIAL_0_BASE_ADR + UART_LSR)
+#define UART_USR_REG (SERIAL_0_BASE_ADR + UART_USR)
+
+#define UART_RBR 0x00
+#define UART_THR 0x00
+#define UART_DLL 0x00
+#define UART_DLH 0x04
+#define UART_IEL 0x04
+#define UART_IIR 0x08
+#define UART_FCR 0x08
+#define UART_LCR 0x0C
+#define UART_MCR 0x10
+#define UART_LSR 0x14
+#define UART_USR 0x7C
+
+/* register definitions */
+
+#define UART_FCR_EN 0x01
+#define UART_FCR_RXCLR 0x02
+#define UART_FCR_TXCLR 0x04
+#define UART_FCR_CLEARFIFO 0x00
+#define UART_FCR_RXL1 0x00
+#define UART_FCR_RXL4 0x40
+#define UART_FCR_RXL8 0x80
+#define UART_FCR_RXL14 0xc0
+#define UART_FCR_TXL0 0x00
+#define UART_FCR_TXL4 0x20
+#define UART_FCR_TXL8 0x30
+#define UART_FCR_TXL14 0x10
+
+#define UART_LCR_DLAB 0x80
+#define UART_LCR_EPS 0x10
+#define UART_LCR_PEN 0x08
+#define UART_LCR_STOP 0x04
+#define UART_LCR_DLS8 0x03
+#define UART_LCR_DLS7 0x02
+#define UART_LCR_DLS6 0x01
+#define UART_LCR_DLS5 0x00
+
+#define UART_DLH_AND_DLL_WIDTH 0xFF
+
+#define UART_IER_PTIME 0x80
+#define UART_IER_ELSI 0x04
+#define UART_IER_ETBEI 0x02
+#define UART_IER_ERBFI 0x01
+#define UART_IIR_FIFOSE 0xC0
+
+#define UART_IIR_InterruptID 0x01
+#define UART_IIR_INTIDTE 0x02
+#define UART_IIR_INTIDRA 0x04
+#define UART_IIR_INTIDRLS 0x06
+#define UART_IIR_INTMASK 0x0f
+#define UART_IIR_RDA 0x04
+#define UART_IIR_TE 0x02
+#define UART_LSR_TEMT 0x40
+#define UART_LSR_THRE 0x20
+#define UART_LSR_BI 0x10
+#define UART_LSR_FE 0x08
+#define UART_LSR_PE 0x04
+#define UART_LSR_R 0x02
+#define UART_LSR_DR 0x01
+
+
+#define UART_USR_BUSY 0x01
+
+#define FIFO_MAXSIZE 16
+
+
+extern UINT32 UART_UartClkFreq(VOID);
+extern UINT8 UART_ChkSndEnd(VOID);
+extern UINT8 SerialPortReadChar(VOID);
+extern VOID SerialPortWriteChar(UINT8 scShowChar);
+
+#endif
+
diff --git a/HisiPkg/Library/SerialPortLib/SerialPortLib.inf b/HisiPkg/Library/SerialPortLib/SerialPortLib.inf new file mode 100644 index 000000000..5b757350f --- /dev/null +++ b/HisiPkg/Library/SerialPortLib/SerialPortLib.inf @@ -0,0 +1,36 @@ +#/** @file
+#
+# Component discription file for NorFlashDxe module
+#
+# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SerialPortLib
+ FILE_GUID = 16D53E86-7EA6-47bd-861F-511ED9B8ABE0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SerialPortLib
+
+
+[Sources.common]
+ SerialPortLib.c
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
diff --git a/HisiPkg/README b/HisiPkg/README new file mode 100644 index 000000000..d4e8517d5 --- /dev/null +++ b/HisiPkg/README @@ -0,0 +1,49 @@ +
+=== D01Board OVERVIEW ===
+
+The project aims to support UEFI for D01 Board using the edk2
+code base.
+
+=== STATUS ===
+
+Current capabilities:
+* Uefi Boot from NORFLASH
+
+=== FUTURE PLANS ===
+
+* Support for PXE, SATA, ACPI, USB
+ - KeyBoard, Mouse and MassStorage
+
+=== BUILDING D01 Board ===
+
+Pre-requisites:
+* Build environment capable of build the edk2 MdeModulePkg.
+* A properly configured ASL compiler:
+ - Intel ASL compiler: Available from http://www.acpica.org
+ - Microsoft ASL compiler: Available from http://www.acpi.info
+
+Build the D01BoardPkg by running from the Workspace
+If you are using armcc as your compiler, you can build the project:
+build -D BIOS_L1 -p HisiPkg/D01BoardPkg/D01BoardPkg.dsc -b DEBUG
+If you are using gcc as your compiler, you can build the project:
+ ./uefi-build.sh -b DEBUG d01
+
+Following the edk2 build process, you will find the D01 binaries
+under the $WORKSPACE/Build/*/*/FV directory. You can find the below
+mentioned binary image.
+D01.fd
+
+=== RUNNING D01BoardPkg on the D01 board ===
+* If you can enter into the shell, connet the network cable from the D01 device to the PC terminal
+* Write BIOS to NORFLASH by using comands as follows:
+D01 >ifconfig -s eth0 192.168.10.50 255.255.255.0 192.168.10.1
+D01 >provision 192.168.10.100 -u admin -p admin -f norflash_header
+D01 >writefiletonor 0 norflash_header
+D01 >provision 192.168.10.100 -u admin -p admin -f D01.fd
+D01 >updateL1 D01.fd
+* If the NORFLASH in your board have nothing, you should adopt other method such as JTAG
+* Now the booting device is ready to be used.
+* Connect the Uart cable from the D01 device to the PC terminal.
+* Power ON the Device.
+* The boot message should be visible on the termial.
+* Finally, it should give boot options.
diff --git a/HisiPkg/norflash_header b/HisiPkg/norflash_header Binary files differnew file mode 100644 index 000000000..83a881804 --- /dev/null +++ b/HisiPkg/norflash_header diff --git a/ShellPkg/Include/Library/PathLib.h b/MdeModulePkg/Include/Library/PathLib.h index ee473523d..ee473523d 100644 --- a/ShellPkg/Include/Library/PathLib.h +++ b/MdeModulePkg/Include/Library/PathLib.h diff --git a/ShellPkg/Library/BasePathLib/BasePathLib.c b/MdeModulePkg/Library/BasePathLib/BasePathLib.c index 301bd3b27..301bd3b27 100644 --- a/ShellPkg/Library/BasePathLib/BasePathLib.c +++ b/MdeModulePkg/Library/BasePathLib/BasePathLib.c diff --git a/ShellPkg/Library/BasePathLib/BasePathLib.inf b/MdeModulePkg/Library/BasePathLib/BasePathLib.inf index a9bd6a8e4..734696878 100644 --- a/ShellPkg/Library/BasePathLib/BasePathLib.inf +++ b/MdeModulePkg/Library/BasePathLib/BasePathLib.inf @@ -30,8 +30,8 @@ [Packages]
MdePkg/MdePkg.dec
- ShellPkg/ShellPkg.dec
-
+ MdeModulePkg/MdeModulePkg.dec
+
[LibraryClasses]
BaseMemoryLib
diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index e04246a2f..d4d2a4232 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -692,6 +692,8 @@ ## Default Creator Revision for ACPI table creation.
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT32|0x30001038
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFdtImage|{ 0x66,0x0f,0xe1,0x96,0xa5,0x0f,0x43,0x8c,0xa9,0x50,0xbe,0x6a,0x58,0xb9,0x12,0x1b }|VOID*|0x30001041
+
[PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
## This PCD defines the Console output column and the default value is 25 according to UEFI spec.
# This PCD could be set to 0 then console output could be at max column and max row.
diff --git a/MdeModulePkg/MdeModulePkg.dsc b/MdeModulePkg/MdeModulePkg.dsc index 1abff5907..0c8aad414 100644 --- a/MdeModulePkg/MdeModulePkg.dsc +++ b/MdeModulePkg/MdeModulePkg.dsc @@ -323,6 +323,9 @@ MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf
MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf
+ MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemDxe.inf
+ MdeModulePkg/Universal/Fdt/FdtTableDxe/FdtTableDxe.inf
+
[Components.IA32, Components.X64, Components.IPF]
MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
MdeModulePkg/Universal/DebugSupportDxe/DebugSupportDxe.inf
diff --git a/MdeModulePkg/Universal/Fdt/FdtTableDxe/FdtTableDxe.c b/MdeModulePkg/Universal/Fdt/FdtTableDxe/FdtTableDxe.c new file mode 100644 index 000000000..c9b8b4c42 --- /dev/null +++ b/MdeModulePkg/Universal/Fdt/FdtTableDxe/FdtTableDxe.c @@ -0,0 +1,33 @@ +
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DxeServicesLib.h>
+
+#include <Guid/FdtTable.h>
+
+EFI_STATUS
+EFIAPI
+InitializeFdtTableDxe (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ VOID *FdtImageData;
+ UINTN FdtImageSize;
+
+ Status = GetSectionFromAnyFv(PcdGetPtr(PcdFdtImage), EFI_SECTION_RAW, 0,
+ &FdtImageData, &FdtImageSize);
+ if (EFI_ERROR(Status))
+ return Status;
+
+ DEBUG((EFI_D_ERROR, "InitializeFdtTableDxe: DTB @ 0x%08x\n", FdtImageData));
+
+ return gBS->InstallConfigurationTable(&gEfiFdtTableGuid, FdtImageData);
+}
diff --git a/MdeModulePkg/Universal/Fdt/FdtTableDxe/FdtTableDxe.inf b/MdeModulePkg/Universal/Fdt/FdtTableDxe/FdtTableDxe.inf new file mode 100644 index 000000000..993b778b8 --- /dev/null +++ b/MdeModulePkg/Universal/Fdt/FdtTableDxe/FdtTableDxe.inf @@ -0,0 +1,48 @@ +## @file
+# FDT Table Protocol Driver
+#
+# Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>
+# This program and the accompanying materials are
+# licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = FdtTableDxe
+ FILE_GUID = 261F9737-CDF6-46CE-A9E2-5DD16B957413
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeFdtTableDxe
+
+[Sources]
+ FdtTableDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ UefiDriverEntryPoint
+ DxeServicesLib
+
+[Guids]
+ gEfiFdtTableGuid
+
+[FeaturePcd]
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFdtImage
+
+[Protocols]
+
+[Depex]
+ TRUE
diff --git a/MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystem.c b/MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystem.c new file mode 100644 index 000000000..197526c8e --- /dev/null +++ b/MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystem.c @@ -0,0 +1,536 @@ +/** @file
+*
+* Copyright (c) 2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+/*
+ A driver using the EFI_FIRMWARE_VOLUME2_PROTOCOL to expose files in firmware
+ volumes via the the EFI_SIMPLE_FILESYSTEM_PROTOCOL and EFI_FILE_PROTOCOL.
+
+ Its primary intended use is to be able to start EFI applications embedded
+ in FVs from the UEFI shell. For this reason, it is not fully compliant as a
+ filesystem driver: it is entirely read-only, and does not support partially
+ reading files.
+
+ It will expose a single directory, containing one file for each file in the
+ firmware volume. If a file has a UI section, its contents will be used as
+ a filename. Otherwise, a string representation of the GUID will be used.
+ Files of an executable type (That is PEIM, DRIVER, COMBINED_PEIM_DRIVER
+ and APPLICATION) will have ".efi" added to their filename.
+
+ The data returned by Read() depends on the type of the underlying FV file:
+ - For executable types, the first section found that contains executable code
+ is returned.
+ - For files of type FREEFORM, the driver attempts to return the first section
+ of type RAW. If none is found, the entire contents of the FV file are
+ returned.
+ - On all other files the entire contents of the FV file is returned, as by
+ EFI_FIRMWARE_VOLUME2_PROTOCOL.ReadFile.
+
+ See the EFI Firmware Volume specification (a separate document from the main
+ UEFI specification) for more information about firmware volumes.
+*/
+
+#include <PiDxe.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PathLib.h>
+
+#include <Protocol/DriverBinding.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/SimpleFileSystem.h>
+#include <Protocol/UnicodeCollation.h>
+
+#include <Guid/FileSystemInfo.h>
+#include <Guid/FileInfo.h>
+
+#include "FvSimpleFilesystemInternal.h"
+
+/*
+ Find and call ReadSection on the first section found of an executable type.
+*/
+STATIC
+EFI_STATUS
+FvFsFindExecutableSection (
+ IN FV_FILESYSTEM_FILE *File,
+ OUT UINTN *BufferSize,
+ OUT VOID **Buffer
+ )
+{
+ EFI_SECTION_TYPE SectionType;
+ UINT32 AuthenticationStatus;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol;
+ EFI_STATUS Status;
+
+ FvProtocol = File->Instance->FvProtocol;
+
+ for (SectionType = EFI_SECTION_PE32; SectionType <= EFI_SECTION_TE; SectionType++) {
+ Status = FvProtocol->ReadSection (
+ FvProtocol,
+ &File->NameGuid,
+ SectionType,
+ 0,
+ Buffer,
+ BufferSize,
+ &AuthenticationStatus
+ );
+ if (Status != EFI_NOT_FOUND) {
+ return Status;
+ }
+ }
+ return EFI_NOT_FOUND;
+}
+
+/*
+ Get the size of the buffer that will be returned by FvFsReadFile.
+*/
+EFI_STATUS
+FvFsGetFileSize (
+ IN FV_FILESYSTEM_FILE *File,
+ OUT UINTN *Size
+ )
+{
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol;
+ UINT32 AuthenticationStatus;
+ EFI_FV_FILETYPE FoundType;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ EFI_STATUS Status;
+ UINT8 IgnoredByte;
+ VOID *IgnoredPtr;
+
+ FvProtocol = File->Instance->FvProtocol;
+
+ // To get the size of a section, we pass 0 for BufferSize. But we can't pass
+ // NULL for Buffer, as that will cause a return of INVALID_PARAMETER, and we
+ // can't pass NULL for *Buffer, as that will cause the callee to allocate
+ // a buffer of the sections size.
+ IgnoredPtr = &IgnoredByte;
+ *Size = 0;
+
+ if (FV_FILETYPE_IS_EXECUTABLE (File->Type)) {
+ // Get the size of the first executable section out of the file.
+ Status = FvFsFindExecutableSection (File, Size, &IgnoredPtr);
+ if (Status == EFI_WARN_BUFFER_TOO_SMALL) {
+ return EFI_SUCCESS;
+ }
+ } else if (File->Type == EFI_FV_FILETYPE_FREEFORM) {
+ // Try to get the size of a raw section out of the file
+ Status = FvProtocol->ReadSection (
+ FvProtocol,
+ &File->NameGuid,
+ EFI_SECTION_RAW,
+ 0,
+ &IgnoredPtr,
+ Size,
+ &AuthenticationStatus
+ );
+ if (Status == EFI_WARN_BUFFER_TOO_SMALL) {
+ return EFI_SUCCESS;
+ }
+ if (EFI_ERROR (Status)) {
+ // Didn't find a raw section, just return the whole file's size.
+ return FvProtocol->ReadFile (
+ FvProtocol,
+ &File->NameGuid,
+ NULL,
+ Size,
+ &FoundType,
+ &Attributes,
+ &AuthenticationStatus
+ );
+ }
+ } else {
+ // Get the size of the entire file
+ return FvProtocol->ReadFile (
+ FvProtocol,
+ &File->NameGuid,
+ NULL,
+ Size,
+ &FoundType,
+ &Attributes,
+ &AuthenticationStatus
+ );
+ }
+
+ return Status;
+}
+
+/*
+ Helper function to read a file. See comment at the top of this file for
+ information on behaviour.
+*/
+EFI_STATUS
+FvFsReadFile (
+ FV_FILESYSTEM_FILE *File,
+ UINTN *BufferSize,
+ VOID **Buffer
+ )
+{
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol;
+ UINT32 AuthenticationStatus;
+ EFI_FV_FILETYPE FoundType;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ EFI_STATUS Status;
+
+ FvProtocol = File->Instance->FvProtocol;
+
+ if (FV_FILETYPE_IS_EXECUTABLE (File->Type)) {
+ // Read the first executable section out of the file.
+ Status = FvFsFindExecutableSection (File, BufferSize, Buffer);
+ } else if (File->Type == EFI_FV_FILETYPE_FREEFORM) {
+ // Try to read a raw section out of the file
+ Status = FvProtocol->ReadSection (
+ FvProtocol,
+ &File->NameGuid,
+ EFI_SECTION_RAW,
+ 0,
+ Buffer,
+ BufferSize,
+ &AuthenticationStatus
+ );
+ if (EFI_ERROR (Status)) {
+ // Didn't find a raw section, just return the whole file.
+ Status = FvProtocol->ReadFile (
+ FvProtocol,
+ &File->NameGuid,
+ Buffer,
+ BufferSize,
+ &FoundType,
+ &Attributes,
+ &AuthenticationStatus
+ );
+ }
+ } else {
+ // Read the entire file
+ Status = FvProtocol->ReadFile (
+ FvProtocol,
+ &File->NameGuid,
+ Buffer,
+ BufferSize,
+ &FoundType,
+ &Attributes,
+ &AuthenticationStatus
+ );
+ }
+
+ return Status;
+}
+
+/*
+ Helper function for populating an EFI_FILE_INFO for a file.
+*/
+STATIC
+EFI_STATUS
+FvFsGetFileInfo (
+ IN FV_FILESYSTEM_FILE *File,
+ IN OUT UINTN *BufferSize,
+ OUT EFI_FILE_INFO *FileInfo
+ )
+{
+ UINTN InfoSize;
+
+ InfoSize = sizeof (EFI_FILE_INFO) + StrSize (File->Name) - sizeof (CHAR16);
+ if (*BufferSize < InfoSize) {
+ *BufferSize = InfoSize;
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ // Initialize FileInfo
+ ZeroMem (FileInfo, InfoSize);
+ FileInfo->Size = InfoSize;
+ FileInfo->Attribute = EFI_FILE_READ_ONLY;
+
+ // File is a directory if it is root.
+ if (File == File->Instance->Root) {
+ FileInfo->Attribute |= EFI_FILE_DIRECTORY;
+ }
+
+ FileInfo->FileSize = File->Size;
+ FileInfo->PhysicalSize = File->Size;
+
+ StrCpy (FileInfo->FileName, File->Name);
+
+ *BufferSize = InfoSize;
+ return EFI_SUCCESS;
+}
+
+EFIAPI
+EFI_STATUS
+FvSimpleFilesystemOpen (
+ IN EFI_FILE_PROTOCOL *This,
+ OUT EFI_FILE_PROTOCOL **NewHandle,
+ IN CHAR16 *FileName,
+ IN UINT64 OpenMode,
+ IN UINT64 Attributes
+ )
+{
+ FV_FILESYSTEM_INSTANCE *Instance;
+ FV_FILESYSTEM_FILE *File;
+ LIST_ENTRY *FileLink;
+
+ File = FVFS_FILE_FROM_FILE_THIS (This);
+ Instance = File->Instance;
+
+ FileName = PathCleanUpDirectories (FileName);
+
+ if (FileName[0] == L'\\') {
+ FileName++;
+ }
+
+ // Check for opening root
+ if (StrCmp (FileName, L".") == 0 || StrCmp (FileName, L"") == 0) {
+ *NewHandle = &Instance->Root->FileProtocol;
+ return EFI_SUCCESS;
+ }
+
+ //
+ // Do a linear search for a file in the FV with a matching filename
+ //
+ for (FileLink = GetFirstNode (&Instance->Files);
+ !IsNull (&Instance->Files, FileLink);
+ FileLink = GetNextNode (&Instance->Files, FileLink)) {
+
+ File = FVFS_FILE_FROM_LINK (FileLink);
+ if (mUnicodeCollation->StriColl (mUnicodeCollation, File->Name, FileName) == 0) {
+ *NewHandle = &File->FileProtocol;
+ return EFI_SUCCESS;
+ }
+ }
+ return EFI_NOT_FOUND;
+}
+
+EFIAPI
+EFI_STATUS
+FvSimpleFilesystemClose (
+ IN EFI_FILE_PROTOCOL *This
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/*
+ Implementation of EFI_FILE_PROTOCOL.Read.
+
+ This implementation is not compliant with the UEFI specification. As this
+ driver's only intended use case is for loading and executing EFI images,
+ it does not support partial reads. If *BufferSize is less than the size of the
+ image being read, it will return EFI_UNSUPPORTED.
+*/
+EFIAPI
+EFI_STATUS
+FvSimpleFilesystemRead (
+ IN EFI_FILE_PROTOCOL *This,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer
+ )
+{
+ FV_FILESYSTEM_INSTANCE *Instance;
+ FV_FILESYSTEM_FILE *File;
+ EFI_STATUS Status;
+ LIST_ENTRY *FileLink;
+
+ File = FVFS_FILE_FROM_FILE_THIS (This);
+ Instance = File->Instance;
+
+ if (File == Instance->Root) {
+ if (File->DirReadNext) {
+ //
+ // Directory read: populate Buffer with an EFI_FILE_INFO
+ //
+ Status = FvFsGetFileInfo (File->DirReadNext, BufferSize, Buffer);
+ if (!EFI_ERROR (Status)) {
+ //
+ // Successfully read a directory entry, now update the pointer to the
+ // next file, which will be read on the next call to this function
+ //
+
+ FileLink = GetNextNode (&Instance->Files, &File->DirReadNext->Link);
+ if (IsNull (&Instance->Files, FileLink)) {
+ // No more files left
+ File->DirReadNext = NULL;
+ } else {
+ File->DirReadNext = FVFS_FILE_FROM_LINK (FileLink);
+ }
+ }
+ return Status;
+ } else {
+ //
+ // Directory read. All entries have been read, so return a zero-size
+ // buffer.
+ //
+ *BufferSize = 0;
+ return EFI_SUCCESS;
+ }
+ } else {
+ if (*BufferSize < File->Size) {
+ DEBUG ((EFI_D_ERROR, "FV Filesystem does not support partial file reads\n", *BufferSize, File->Size));
+ return EFI_UNSUPPORTED;
+ }
+ return FvFsReadFile (File, BufferSize, &Buffer);
+ }
+}
+
+EFIAPI
+EFI_STATUS
+FvSimpleFilesystemWrite (
+ IN EFI_FILE_PROTOCOL *This,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+
+EFIAPI
+EFI_STATUS
+FvSimpleFilesystemGetPosition (
+ IN EFI_FILE_PROTOCOL *This,
+ OUT UINT64 *Position
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/*
+ This implementation of EFI_FILE_PROTOCOL.SetPosition is not compliant with
+ the UEFI specification. We do not support partial file reads (see comment on
+ FvSimpleFilesystemRead), therefore we only support seeking to position 0
+*/
+EFIAPI
+EFI_STATUS
+FvSimpleFilesystemSetPosition (
+ IN EFI_FILE_PROTOCOL *This,
+ IN UINT64 Position
+ )
+{
+ FV_FILESYSTEM_INSTANCE *Instance;
+ FV_FILESYSTEM_FILE *File;
+
+ File = FVFS_FILE_FROM_FILE_THIS (This);
+ Instance = File->Instance;
+
+ if (File == Instance->Root) {
+ if (Position != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+ // Reset directory position to first entry
+ File->DirReadNext = FVFS_GET_FIRST_FILE (Instance);
+ } else if (Position != 0) {
+ // We don't support partial file reads, so we don't support seeking either.
+ return EFI_UNSUPPORTED;
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFIAPI
+EFI_STATUS
+FvSimpleFilesystemFlush (
+ IN EFI_FILE_PROTOCOL *This
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFIAPI
+EFI_STATUS
+FvSimpleFilesystemDelete (
+ IN EFI_FILE_PROTOCOL *This
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+STATIC EFI_FILE_SYSTEM_INFO mFsInfoTemplate = {
+ 0, // Populate at runtime
+ TRUE, // Read-only
+ 0, // Don't know volume size
+ 0, // No free space
+ 0, // Don't know block size
+ L"" // Populate at runtime
+};
+
+EFIAPI
+EFI_STATUS
+FvSimpleFilesystemGetInfo (
+ IN EFI_FILE_PROTOCOL *This,
+ IN EFI_GUID *InformationType,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer
+ )
+{
+ FV_FILESYSTEM_FILE *File;
+ EFI_FILE_SYSTEM_INFO *FsInfoOut;
+ FV_FILESYSTEM_INSTANCE *Instance;
+ UINTN InfoSize;
+
+ File = FVFS_FILE_FROM_FILE_THIS (This);
+
+ if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid)) {
+ //
+ // Return filesystem info
+ //
+ Instance = File->Instance;
+
+ InfoSize = sizeof (EFI_FILE_SYSTEM_INFO) + StrSize (Instance->VolumeLabel)
+ - sizeof (CHAR16);
+
+ if (*BufferSize < InfoSize) {
+ *BufferSize = InfoSize;
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ // Cast output buffer for convenience
+ FsInfoOut = (EFI_FILE_SYSTEM_INFO *) Buffer;
+
+ CopyMem (FsInfoOut, &mFsInfoTemplate, mFsInfoTemplate.Size);
+ StrCpy (FsInfoOut->VolumeLabel, Instance->VolumeLabel);
+ return EFI_SUCCESS;
+ } else if (CompareGuid (InformationType, &gEfiFileInfoGuid)) {
+ //
+ // Return file info
+ //
+
+ return FvFsGetFileInfo (File, BufferSize, (EFI_FILE_INFO *) Buffer);
+ } else {
+ return EFI_UNSUPPORTED;
+ }
+}
+
+EFIAPI
+EFI_STATUS
+FvSimpleFilesystemSetInfo (
+ IN EFI_FILE_PROTOCOL *This,
+ IN EFI_GUID *InformationType,
+ IN UINTN BufferSize,
+ IN VOID *Buffer
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+EFI_FILE_PROTOCOL mFilesystemTemplate = {
+ EFI_FILE_PROTOCOL_REVISION,
+ FvSimpleFilesystemOpen,
+ FvSimpleFilesystemClose,
+ FvSimpleFilesystemDelete,
+ FvSimpleFilesystemRead,
+ FvSimpleFilesystemWrite,
+ FvSimpleFilesystemGetPosition,
+ FvSimpleFilesystemSetPosition,
+ FvSimpleFilesystemGetInfo,
+ FvSimpleFilesystemSetInfo,
+ FvSimpleFilesystemFlush
+};
diff --git a/MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemDxe.inf b/MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemDxe.inf new file mode 100644 index 000000000..9d4200405 --- /dev/null +++ b/MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemDxe.inf @@ -0,0 +1,52 @@ +#/** @file
+# Support for Simple File System over Firmware Volume
+#
+# Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = FvSimpleFilesystem
+ FILE_GUID = 907125c0-a5f1-11e3-a3fe-a3198b49350c
+ MODULE_TYPE = UEFI_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = FvSimpleFilesystemEntryPoint
+
+[Sources]
+ FvSimpleFilesystem.c
+ FvSimpleFilesystemEntryPoint.c
+ FvSimpleFilesystemInternal.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DevicePathLib
+ MemoryAllocationLib
+ PathLib
+ PrintLib
+ UefiDriverEntryPoint
+
+[Guids]
+ gEfiFileInfoGuid
+ gEfiFileSystemInfoGuid
+ gEfiFileSystemVolumeLabelInfoIdGuid
+
+[Protocols]
+ gEfiDevicePathFromTextProtocolGuid
+ gEfiDevicePathProtocolGuid
+ gEfiDriverBindingProtocolGuid
+ gEfiFirmwareVolume2ProtocolGuid
+ gEfiSimpleFileSystemProtocolGuid
+ gEfiUnicodeCollationProtocolGuid
diff --git a/MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemEntryPoint.c b/MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemEntryPoint.c new file mode 100644 index 000000000..2828f8aed --- /dev/null +++ b/MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemEntryPoint.c @@ -0,0 +1,401 @@ +/** @file
+*
+* Copyright (c) 2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <PiDxe.h>
+
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PrintLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/DriverBinding.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/SimpleFileSystem.h>
+#include <Protocol/UnicodeCollation.h>
+
+#include "FvSimpleFilesystemInternal.h"
+
+EFI_UNICODE_COLLATION_PROTOCOL *mUnicodeCollation = NULL;
+
+// A Guid string is 32 hex characters with 4 hyphens: 36 characters total
+#define GUID_STRING_SIZE (36 * sizeof (CHAR16))
+
+#define FVFS_VOLUME_LABEL_PREFIX L"Firmware Volume: "
+#define FVFS_VOLUME_LABEL_SIZE (sizeof (FVFS_VOLUME_LABEL_PREFIX) + GUID_STRING_SIZE)
+#define FVFS_FALLBACK_VOLUME_LABEL L"Firmware Volume"
+
+EFI_STATUS
+EFIAPI
+FvSimpleFilesystemOpenVolume (
+ IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,
+ OUT EFI_FILE_PROTOCOL **RootFile
+ )
+{
+ EFI_STATUS Status;
+ FV_FILESYSTEM_FILE *Root;
+ CHAR16 *UiSection;
+ EFI_GUID NameGuid;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINT32 Authentication;
+ VOID *Key;
+ EFI_FV_FILETYPE FileType;
+ UINTN Size;
+ FV_FILESYSTEM_INSTANCE *Instance;
+ FV_FILESYSTEM_FILE *File;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol;
+ CHAR16 *Name;
+
+ Instance = FVFS_INSTANCE_FROM_SIMPLE_FS_THIS (This);
+ Status = EFI_SUCCESS;
+
+ if (Instance->Root == NULL) {
+ //
+ // Allocate file structure for root file
+ //
+ Root = AllocatePool (sizeof (FV_FILESYSTEM_FILE));
+ if (Root == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Instance->Root = Root;
+
+ Root->Instance = Instance;
+ Root->Signature = FVFS_FILE_SIGNATURE;
+ Root->Name = L"";
+ Root->Size = 0;
+ CopyMem (&Root->FileProtocol, &mFilesystemTemplate, sizeof (mFilesystemTemplate));
+
+ //
+ // Populate the instance's list of files. We consider anything a file that
+ // has a UI_SECTION, which we consider to be its filename.
+ //
+
+ FvProtocol = Instance->FvProtocol;
+
+ // Allocate Key
+ Key = AllocatePool (FvProtocol->KeySize);
+ ASSERT (Key != NULL);
+ ZeroMem (Key, FvProtocol->KeySize);
+
+ do {
+ FileType = EFI_FV_FILETYPE_ALL;
+
+ Status = FvProtocol->GetNextFile (
+ FvProtocol,
+ Key,
+ &FileType,
+ &NameGuid,
+ &Attributes,
+ &Size
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT (Status == EFI_NOT_FOUND);
+ break;
+ }
+
+ //
+ // Found a file.
+ // Allocate a file structure and populate it.
+ //
+ File = AllocatePool (sizeof (FV_FILESYSTEM_FILE));
+ if (File == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ //
+ // Get a file's name: If it has a UI section, use that, otherwise use
+ // its NameGuid.
+ //
+
+ UiSection = NULL;
+ Status = FvProtocol->ReadSection (
+ FvProtocol,
+ &NameGuid,
+ EFI_SECTION_USER_INTERFACE,
+ 0,
+ (VOID **)&UiSection,
+ &Size,
+ &Authentication
+ );
+ if (!EFI_ERROR (Status)) {
+ Name = UiSection;
+ } else {
+ Name = AllocatePool (GUID_STRING_SIZE);
+ if (Name == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ UnicodeSPrint (Name, GUID_STRING_SIZE, L"%g", &NameGuid);
+ }
+
+ // Add ".efi" to filenames of drivers and applications.
+ if (FV_FILETYPE_IS_EXECUTABLE (FileType)) {
+ File->Name = AllocateCopyPool (StrSize (Name) + 8, Name);
+ StrCat (File->Name, L".efi");
+ FreePool (Name);
+ } else {
+ File->Name = Name;
+ }
+
+ File->Type = FileType;
+ File->Signature = FVFS_FILE_SIGNATURE;
+ CopyGuid (&File->NameGuid, &NameGuid);
+ File->Instance = Instance;
+ CopyMem (&File->FileProtocol, &mFilesystemTemplate, sizeof (mFilesystemTemplate));
+ InsertHeadList (&Instance->Files, &File->Link);
+
+ // Call FvFsReadFile to get the file's size
+ File->Size = 0;
+ Status = FvFsGetFileSize (File, &File->Size);
+ ASSERT_EFI_ERROR (Status);
+ } while (TRUE);
+
+ FreePool (Key);
+
+ if (Status == EFI_NOT_FOUND) {
+ Status = EFI_SUCCESS;
+ }
+ }
+
+ Instance->Root->DirReadNext = FVFS_GET_FIRST_FILE (Instance);
+ *RootFile = &Instance->Root->FileProtocol;
+ return Status;
+}
+
+STATIC EFI_SIMPLE_FILE_SYSTEM_PROTOCOL mSimpleFsTemplate = {
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION,
+ FvSimpleFilesystemOpenVolume
+};
+
+EFI_STATUS
+EFIAPI
+FvSimpleFilesystemDriverSupported (
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath OPTIONAL
+ )
+{
+ return gBS->OpenProtocol (
+ ControllerHandle,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ gImageHandle,
+ ControllerHandle,
+ EFI_OPEN_PROTOCOL_TEST_PROTOCOL
+ );
+}
+
+EFI_STATUS
+EFIAPI
+FvSimpleFilesystemDriverStart (
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath OPTIONAL
+ )
+{
+ EFI_STATUS Status;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol;
+ FV_FILESYSTEM_INSTANCE *Instance;
+ EFI_DEVICE_PATH_PROTOCOL *FvDevicePath;
+ EFI_GUID *FvGuid;
+
+ Status = gBS->LocateProtocol (
+ &gEfiUnicodeCollationProtocolGuid,
+ NULL,
+ (VOID **) &mUnicodeCollation
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Open FV protocol
+ //
+
+ Status = gBS->OpenProtocol (
+ ControllerHandle,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **) &FvProtocol,
+ gImageHandle,
+ ControllerHandle,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Create an instance
+ //
+ Instance = AllocatePool (sizeof (FV_FILESYSTEM_INSTANCE));
+ if (Instance == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ Instance->Root = NULL;
+ Instance->FvProtocol = FvProtocol;
+ Instance->Signature = FVFS_INSTANCE_SIGNATURE;
+ InitializeListHead (&Instance->Files);
+ CopyMem (&Instance->SimpleFs, &mSimpleFsTemplate, sizeof (mSimpleFsTemplate));
+
+ Status = gBS->InstallProtocolInterface(
+ &ControllerHandle,
+ &gEfiSimpleFileSystemProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &Instance->SimpleFs
+ );
+
+ //
+ // Decide on a filesystem volume label, which will include the FV's guid.
+ //
+
+ // Get the device path to find the FV's GUID
+ Instance->VolumeLabel = NULL;
+ Status = gBS->OpenProtocol (
+ ControllerHandle,
+ &gEfiDevicePathProtocolGuid,
+ (VOID **) &FvDevicePath,
+ gImageHandle,
+ ControllerHandle,
+ EFI_OPEN_PROTOCOL_BY_DRIVER
+ );
+ if (!EFI_ERROR (Status)) {
+ // Iterate over device path until we find a firmware volume node
+ while (!IsDevicePathEndType (FvDevicePath)) {
+ if (DevicePathType (FvDevicePath) == MEDIA_DEVICE_PATH &&
+ DevicePathSubType (FvDevicePath) == MEDIA_PIWG_FW_VOL_DP) {
+ // Allocate the volume label
+ Instance->VolumeLabel = AllocatePool (FVFS_VOLUME_LABEL_SIZE);
+ // Check the allocation was successful
+ if (Instance->VolumeLabel != NULL) {
+ // Extract the FV's guid
+ FvGuid = &((MEDIA_FW_VOL_DEVICE_PATH *) FvDevicePath)->FvName;
+ // Build the volume label string
+ UnicodeSPrint (
+ Instance->VolumeLabel,
+ FVFS_VOLUME_LABEL_SIZE,
+ FVFS_VOLUME_LABEL_PREFIX L"%g",
+ FvGuid
+ );
+ }
+ break;
+ }
+ FvDevicePath = NextDevicePathNode (FvDevicePath);
+ }
+ }
+ // If we didn't decide on a volume label, set a fallback one
+ if (Instance->VolumeLabel == NULL) {
+ Instance->VolumeLabel = AllocateCopyPool (
+ sizeof (FVFS_FALLBACK_VOLUME_LABEL),
+ FVFS_FALLBACK_VOLUME_LABEL
+ );
+ }
+
+ return Status;
+}
+
+EFI_STATUS
+EFIAPI
+FvSimpleFilesystemDriverStop (
+ IN EFI_DRIVER_BINDING_PROTOCOL *DriverBinding,
+ IN EFI_HANDLE ControllerHandle,
+ IN UINTN NumberOfChildren,
+ IN EFI_HANDLE *ChildHandleBuffer OPTIONAL
+ )
+{
+ EFI_STATUS Status;
+ FV_FILESYSTEM_INSTANCE *Instance;
+ FV_FILESYSTEM_FILE *File;
+ LIST_ENTRY *FileLink;
+
+ Instance = FVFS_INSTANCE_FROM_BINDING_THIS (DriverBinding);
+
+ //
+ // Close and uninstall protocols.
+ //
+
+ Status = gBS->CloseProtocol (
+ ControllerHandle,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ gImageHandle,
+ ControllerHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gBS->UninstallProtocolInterface (
+ ControllerHandle,
+ &gEfiSimpleFileSystemProtocolGuid,
+ &Instance->SimpleFs
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Free file structures
+ //
+
+ if (Instance->Root != NULL) {
+ for (FileLink = GetFirstNode (&Instance->Files);
+ !IsNull (&Instance->Files, FileLink);
+ FileLink = GetNextNode (&Instance->Files, FileLink)) {
+ File = FVFS_FILE_FROM_LINK (FileLink);
+
+ FreePool (File->Name);
+ FreePool (File);
+ }
+ // Root->Name is statically allocated, no need to free.
+ FreePool (Instance->Root);
+ }
+
+ //
+ // Free Instance
+ //
+
+ if (Instance->VolumeLabel != NULL) {
+ FreePool (Instance->VolumeLabel);
+ }
+ FreePool (Instance);
+
+ return EFI_SUCCESS;
+}
+
+EFI_DRIVER_BINDING_PROTOCOL mDriverBinding = {
+ FvSimpleFilesystemDriverSupported,
+ FvSimpleFilesystemDriverStart,
+ FvSimpleFilesystemDriverStop,
+ 0,
+ NULL,
+ NULL
+};
+
+EFIAPI
+EFI_STATUS
+FvSimpleFilesystemEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ Status = gBS->InstallProtocolInterface (
+ &ImageHandle,
+ &gEfiDriverBindingProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mDriverBinding
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemInternal.h b/MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemInternal.h new file mode 100644 index 000000000..ecf5461a0 --- /dev/null +++ b/MdeModulePkg/Universal/FvSimpleFilesystemDxe/FvSimpleFilesystemInternal.h @@ -0,0 +1,99 @@ +/** @file
+*
+* Copyright (c) 2014, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __FVFS_INTERNAL_H__
+#define __FVFS_INTERNAL_H__
+
+#include <Library/BaseLib.h>
+
+typedef struct _FV_FILESYSTEM_FILE FV_FILESYSTEM_FILE;
+
+// Struct representing an instance of the "filesystem". There will be one of
+// these structs per FV.
+typedef struct _FV_FILESYSTEM_INSTANCE {
+ UINT32 Signature;
+ LIST_ENTRY Link;
+ LIST_ENTRY Files;
+ EFI_DRIVER_BINDING_PROTOCOL *DriverBinding;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FvProtocol;
+ EFI_SIMPLE_FILE_SYSTEM_PROTOCOL SimpleFs;
+ FV_FILESYSTEM_FILE *Root;
+ CHAR16 *VolumeLabel;
+} FV_FILESYSTEM_INSTANCE;
+
+// Struct representing a file. There will be one of these for each file on each
+// FV, plus one for each FV representing the "root directory".
+struct _FV_FILESYSTEM_FILE {
+ UINT32 Signature;
+ LIST_ENTRY Link;
+ CHAR16 *Name;
+ FV_FILESYSTEM_FILE *DirReadNext;
+ EFI_GUID NameGuid;
+ FV_FILESYSTEM_INSTANCE *Instance;
+ EFI_FILE_PROTOCOL FileProtocol;
+ UINTN Size;
+ EFI_FV_FILETYPE Type;
+};
+
+#define FVFS_FILE_SIGNATURE SIGNATURE_32 ('f', 'v', 'f', 'l')
+#define FVFS_INSTANCE_SIGNATURE SIGNATURE_32 ('f', 'v', 'f', 's')
+
+#define FVFS_INSTANCE_FROM_BINDING_THIS(This) CR ( \
+ This, \
+ FV_FILESYSTEM_INSTANCE, \
+ DriverBinding, \
+ FVFS_INSTANCE_SIGNATURE \
+ )
+
+#define FVFS_INSTANCE_FROM_SIMPLE_FS_THIS(This) CR ( \
+ This, \
+ FV_FILESYSTEM_INSTANCE, \
+ SimpleFs, \
+ FVFS_INSTANCE_SIGNATURE \
+ )
+
+#define FVFS_FILE_FROM_FILE_THIS(This) CR ( \
+ This, \
+ FV_FILESYSTEM_FILE, \
+ FileProtocol, \
+ FVFS_FILE_SIGNATURE \
+ )
+
+#define FVFS_FILE_FROM_LINK(FileLink) CR (FileLink, FV_FILESYSTEM_FILE, Link, FVFS_FILE_SIGNATURE)
+
+#define FVFS_GET_FIRST_FILE(Instance) FVFS_FILE_FROM_LINK (GetFirstNode (&Instance->Files))
+
+#define FV_FILETYPE_IS_EXECUTABLE(Type) ((Type) == EFI_FV_FILETYPE_PEIM || \
+ (Type) == EFI_FV_FILETYPE_DRIVER || \
+ (Type) == EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER || \
+ (Type) == EFI_FV_FILETYPE_APPLICATION)
+
+EFI_STATUS
+FvFsReadFile (
+ FV_FILESYSTEM_FILE *File,
+ UINTN *BufferSize,
+ VOID **Buffer
+ );
+
+EFI_STATUS
+FvFsGetFileSize (
+ IN FV_FILESYSTEM_FILE *File,
+ OUT UINTN *Size
+ );
+
+extern EFI_FILE_PROTOCOL mFilesystemTemplate;
+
+extern EFI_UNICODE_COLLATION_PROTOCOL *mUnicodeCollation;
+
+#endif
diff --git a/MdePkg/Include/Guid/FdtTable.h b/MdePkg/Include/Guid/FdtTable.h new file mode 100644 index 000000000..ab2e0bc43 --- /dev/null +++ b/MdePkg/Include/Guid/FdtTable.h @@ -0,0 +1,26 @@ +/** @file
+ GUIDs used to locate the FDT image in the UEFI 2.x system table.
+
+ Copyright (c) 2014 Linaro Ltd. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __FDT_TABLE_GUID_H__
+#define __FDT_TABLE_GUID_H__
+
+#define FDT_TABLE_GUID \
+ { \
+ 0xb1b621d5, 0xf19c, 0x41a5, { 0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0 } \
+ }
+
+extern EFI_GUID gEfiFdtTableGuid;
+
+#endif
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 4daf3e6a7..574561b9f 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -615,6 +615,9 @@ ## Include/Guid/VectorHandoffTable.h
gEfiVectorHandoffTableGuid = { 0x996ec11c, 0x5397, 0x4e73, { 0xb5, 0x8f, 0x82, 0x7e, 0x52, 0x90, 0x6d, 0xef }}
+ ## Include/Guid/FdtTable.h
+ gEfiFdtTableGuid = { 0xb1b621d5, 0xf19c, 0x41a5, {0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0 }}
+
[Guids.IA32, Guids.X64]
## Include/Guid/Cper.h
gEfiIa32X64ErrorTypeCacheCheckGuid = { 0xA55701F5, 0xE3EF, 0x43de, { 0xAC, 0x72, 0x24, 0x9B, 0x57, 0x3F, 0xAD, 0x2C }}
diff --git a/Omap44xxPkg/Gpio/Gpio.c b/Omap44xxPkg/Gpio/Gpio.c new file mode 100644 index 000000000..282722268 --- /dev/null +++ b/Omap44xxPkg/Gpio/Gpio.c @@ -0,0 +1,135 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Uefi.h> + +#include <Library/IoLib.h> +#include <Library/OmapLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <Protocol/EmbeddedGpio.h> + +#include <Omap4430/Omap4430.h> + +EFI_STATUS +Get ( + IN EMBEDDED_GPIO *This, + IN EMBEDDED_GPIO_PIN Gpio, + OUT UINTN *Value + ) +{ + UINTN Port; + UINTN Pin; + UINT32 DataInRegister; + + if (Value == NULL) + { + return EFI_UNSUPPORTED; + } + + Port = GPIO_PORT(Gpio); + Pin = GPIO_PIN(Gpio); + + DataInRegister = GpioBase(Port) + GPIO_DATAIN; + + if (MmioRead32 (DataInRegister) & GPIO_DATAIN_MASK(Pin)) { + *Value = 1; + } else { + *Value = 0; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +Set ( + IN EMBEDDED_GPIO *This, + IN EMBEDDED_GPIO_PIN Gpio, + IN EMBEDDED_GPIO_MODE Mode + ) +{ + UINTN Port; + UINTN Pin; + UINT32 OutputEnableRegister; + UINT32 SetDataOutRegister; + UINT32 ClearDataOutRegister; + + Port = GPIO_PORT(Gpio); + Pin = GPIO_PIN(Gpio); + + OutputEnableRegister = GpioBase(Port) + GPIO_OE; + SetDataOutRegister = GpioBase(Port) + GPIO_SETDATAOUT; + ClearDataOutRegister = GpioBase(Port) + GPIO_CLEARDATAOUT; + + switch (Mode) + { + case GPIO_MODE_INPUT: + MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_INPUT(Pin)); + break; + + case GPIO_MODE_OUTPUT_0: + MmioWrite32 (ClearDataOutRegister, GPIO_CLEARDATAOUT_BIT(Pin)); + MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin)); + break; + + case GPIO_MODE_OUTPUT_1: + MmioWrite32 (SetDataOutRegister, GPIO_SETDATAOUT_BIT(Pin)); + MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin)); + break; + + default: + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +GetMode ( + IN EMBEDDED_GPIO *This, + IN EMBEDDED_GPIO_PIN Gpio, + OUT EMBEDDED_GPIO_MODE *Mode + ) +{ + return EFI_UNSUPPORTED; +} + +EFI_STATUS +SetPull ( + IN EMBEDDED_GPIO *This, + IN EMBEDDED_GPIO_PIN Gpio, + IN EMBEDDED_GPIO_PULL Direction + ) +{ + return EFI_UNSUPPORTED; +} + +EMBEDDED_GPIO Gpio = { + Get, + Set, + GetMode, + SetPull +}; + +EFI_STATUS +GpioInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = gBS->InstallMultipleProtocolInterfaces(&ImageHandle, &gEmbeddedGpioProtocolGuid, &Gpio, NULL); + return Status; +} diff --git a/Omap44xxPkg/Gpio/Gpio.inf b/Omap44xxPkg/Gpio/Gpio.inf new file mode 100644 index 000000000..89ab02167 --- /dev/null +++ b/Omap44xxPkg/Gpio/Gpio.inf @@ -0,0 +1,45 @@ +#/** @file +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Gpio + FILE_GUID = E7D9CAE1-6930-46E3-BDF9-0027446E7DF2 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = GpioInitialize + + +[Sources.common] + Gpio.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + IoLib + UefiDriverEntryPoint + OmapLib + +[Guids] + +[Protocols] + gEmbeddedGpioProtocolGuid + +[Pcd] + +[depex] + TRUE
\ No newline at end of file diff --git a/Omap44xxPkg/Include/Library/OmapDmaLib.h b/Omap44xxPkg/Include/Library/OmapDmaLib.h new file mode 100755 index 000000000..9d81d5049 --- /dev/null +++ b/Omap44xxPkg/Include/Library/OmapDmaLib.h @@ -0,0 +1,90 @@ +/** @file + + Abstractions for simple OMAP DMA. + OMAP_DMA4 structure elements are described in the OMAP44xx TRM. + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP_DMA_LIB_H__ +#define __OMAP_DMA_LIB_H__ + + +// Example from DMA chapter of the OMAP44xx spec +typedef struct { + UINT8 DataType; // DMA4_CSDPi[1:0] + UINT8 ReadPortAccessType; // DMA4_CSDPi[8:7] + UINT8 WritePortAccessType; // DMA4_CSDPi[15:14] + UINT8 SourceEndiansim; // DMA4_CSDPi[21] + UINT8 DestinationEndianism; // DMA4_CSDPi[19] + UINT8 WriteMode; // DMA4_CSDPi[17:16] + UINT8 SourcePacked; // DMA4_CSDPi[6] + UINT8 DestinationPacked; // DMA4_CSDPi[13] + UINT32 NumberOfElementPerFrame; // DMA4_CENi + UINT32 NumberOfFramePerTransferBlock; // DMA4_CFNi + UINT32 SourceStartAddress; // DMA4_CSSAi + UINT32 DestinationStartAddress; // DMA4_CDSAi + UINT32 SourceElementIndex; // DMA4_CSEi + UINT32 SourceFrameIndex; // DMA4_CSFi + UINT32 DestinationElementIndex; // DMA4_CDEi + UINT32 DestinationFrameIndex; // DMA4_CDFi + UINT8 ReadPortAccessMode; // DMA4_CCRi[13:12] + UINT8 WritePortAccessMode; // DMA4_CCRi[15:14] + UINT8 ReadPriority; // DMA4_CCRi[6] + UINT8 WritePriority; // DMA4_CCRi[23] + UINT8 ReadRequestNumber; // DMA4_CCRi[4:0] + UINT8 WriteRequestNumber; // DMA4_CCRi[20:19] +} OMAP_DMA4; + + +/** + Configure OMAP DMA Channel + + @param Channel DMA Channel to configure + @param Dma4 Pointer to structure used to initialize DMA registers for the Channel + + @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. + @retval EFI_INVALID_PARAMETER Channel is not valid + @retval EFI_DEVICE_ERROR The system hardware could not map the requested information. + +**/ +EFI_STATUS +EFIAPI +EnableDmaChannel ( + IN UINTN Channel, + IN OMAP_DMA4 *Dma4 + ); + +/** + Turn of DMA channel configured by EnableDma(). + + @param Channel DMA Channel to configure + @param SuccesMask Bits in DMA4_CSR register indicate EFI_SUCCESS + @param ErrorMask Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR + + @retval EFI_SUCCESS DMA hardware disabled + @retval EFI_INVALID_PARAMETER Channel is not valid + @retval EFI_DEVICE_ERROR The system hardware could not map the requested information. + +**/ +EFI_STATUS +EFIAPI +DisableDmaChannel ( + IN UINTN Channel, + IN UINT32 SuccessMask, + IN UINT32 ErrorMask + ); + + + +#endif + diff --git a/Omap44xxPkg/Include/Library/OmapLib.h b/Omap44xxPkg/Include/Library/OmapLib.h new file mode 100644 index 000000000..419227515 --- /dev/null +++ b/Omap44xxPkg/Include/Library/OmapLib.h @@ -0,0 +1,44 @@ +/** @file + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAPLIB_H__ +#define __OMAPLIB_H__ + +UINT32 +EFIAPI +GpioBase ( + IN UINTN Port + ); + +UINT32 +EFIAPI +TimerBase ( + IN UINTN Timer + ); + +UINTN +EFIAPI +InterruptVectorForTimer ( + IN UINTN TImer + ); + +UINT32 +EFIAPI +UartBase ( + IN UINTN Uart + ); + + +#endif // __OMAPLIB_H__ + diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430.h b/Omap44xxPkg/Include/Omap4430/Omap4430.h new file mode 100644 index 000000000..f59eec4dc --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430.h @@ -0,0 +1,31 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430_H__ +#define __OMAP4430_H__ + +#include "Omap4430Gpio.h" +#include "Omap4430Interrupt.h" +#include "Omap4430Prcm.h" +#include "Omap4430Timer.h" +#include "Omap4430Uart.h" +#include "Omap4430Usb.h" +#include "Omap4430MMCHS.h" +#include "Omap4430I2c.h" +#include "Omap4430PadConfiguration.h" +#include "Omap4430Gpmc.h" +#include "Omap4430Dma.h" + +#endif // __OMAP4430_H__ + diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Dma.h b/Omap44xxPkg/Include/Omap4430/Omap4430Dma.h new file mode 100755 index 000000000..cf27e2719 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Dma.h @@ -0,0 +1,130 @@ +/** @file + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430DMA_H__ +#define __OMAP4430DMA_H__ + + +#define DMA4_MAX_CHANNEL 31 + +#define DMA4_IRQENABLE_L(_i) (0x48056018 + (0x4*(_i))) + +#define DMA4_CCR(_i) (0x48056080 + (0x60*(_i))) +#define DMA4_CICR(_i) (0x48056088 + (0x60*(_i))) +#define DMA4_CSR(_i) (0x4805608c + (0x60*(_i))) +#define DMA4_CSDP(_i) (0x48056090 + (0x60*(_i))) +#define DMA4_CEN(_i) (0x48056094 + (0x60*(_i))) +#define DMA4_CFN(_i) (0x48056098 + (0x60*(_i))) +#define DMA4_CSSA(_i) (0x4805609c + (0x60*(_i))) +#define DMA4_CDSA(_i) (0x480560a0 + (0x60*(_i))) +#define DMA4_CSEI(_i) (0x480560a4 + (0x60*(_i))) +#define DMA4_CSFI(_i) (0x480560a8 + (0x60*(_i))) +#define DMA4_CDEI(_i) (0x480560ac + (0x60*(_i))) +#define DMA4_CDFI(_i) (0x480560b0 + (0x60*(_i))) + +#define DMA4_GCR (0x48056078) + +// Channel Source Destination parameters +#define DMA4_CSDP_DATA_TYPE8 0 +#define DMA4_CSDP_DATA_TYPE16 1 +#define DMA4_CSDP_DATA_TYPE32 2 + +#define DMA4_CSDP_SRC_PACKED BIT6 +#define DMA4_CSDP_SRC_NONPACKED 0 + +#define DMA4_CSDP_SRC_BURST_EN (0x0 << 7) +#define DMA4_CSDP_SRC_BURST_EN16 (0x1 << 7) +#define DMA4_CSDP_SRC_BURST_EN32 (0x2 << 7) +#define DMA4_CSDP_SRC_BURST_EN64 (0x3 << 7) + +#define DMA4_CSDP_DST_PACKED BIT13 +#define DMA4_CSDP_DST_NONPACKED 0 + +#define DMA4_CSDP_BURST_EN (0x0 << 14) +#define DMA4_CSDP_BURST_EN16 (0x1 << 14) +#define DMA4_CSDP_BURST_EN32 (0x2 << 14) +#define DMA4_CSDP_BURST_EN64 (0x3 << 14) + +#define DMA4_CSDP_WRITE_MODE_NONE_POSTED (0x0 << 16) +#define DMA4_CSDP_WRITE_MODE_POSTED (0x1 << 16) +#define DMA4_CSDP_WRITE_MODE_LAST_NON_POSTED (0x2 << 16) + +#define DMA4_CSDP_DST_ENDIAN_LOCK_LOCK BIT18 +#define DMA4_CSDP_DST_ENDIAN_LOCK_ADAPT 0 + +#define DMA4_CSDP_DST_ENDIAN_BIG BIT19 +#define DMA4_CSDP_DST_ENDIAN_LITTLE 0 + +#define DMA4_CSDP_SRC_ENDIAN_LOCK_LOCK BIT20 +#define DMA4_CSDP_SRC_ENDIAN_LOCK_ADAPT 0 + +#define DMA4_CSDP_SRC_ENDIAN_BIG BIT21 +#define DMA4_CSDP_SRC_ENDIAN_LITTLE 0 + +// Channel Control +#define DMA4_CCR_SYNCHRO_CONTROL_MASK 0x1f + +#define DMA4_CCR_FS_ELEMENT (0 | 0) +#define DMA4_CCR_FS_BLOCK (0 | BIT18) +#define DMA4_CCR_FS_FRAME (BIT5 | 0) +#define DMA4_CCR_FS_PACKET (BIT5 | BIT18) + +#define DMA4_CCR_READ_PRIORITY_HIGH BIT6 +#define DMA4_CCR_READ_PRIORITY_LOW 0 + +#define DMA4_CCR_ENABLE BIT7 +#define DMA4_CCR_DISABLE 0 + +#define DMA4_CCR_SUSPEND_SENSITIVE_IGNORE BIT8 +#define DMA4_CCR_SUSPEND_SENSITIVE 0 + +#define DMA4_CCR_RD_ACTIVE BIT9 +#define DMA4_CCR_WR_ACTIVE BIT10 + +#define DMA4_CCR_SRC_AMODE (0 | 0) +#define DMA4_CCR_SRC_AMODE_POST_INC (0 | BIT12) +#define DMA4_CCR_SRC_AMODE_SINGLE_INDEX (BIT13 | 0) +#define DMA4_CCR_SRC_AMODE_DOUBLE_INDEX (BIT13 | BIT12) + +#define DMA4_CCR_DST_AMODE (0 | 0) +#define DMA4_CCR_DST_AMODE_POST_INC (0 | BIT14) +#define DMA4_CCR_DST_AMODE_SINGLE_INDEX (BIT15 | 0) +#define DMA4_CCR_DST_AMODE_DOUBLE_INDEX (BIT15 | BIT14) + +#define DMA4_CCR_CONST_FILL_ENABLE BIT16 +#define DMA4_CCR_TRANSPARENT_COPY_ENABLE BIT17 + +#define DMA4_CCR_SEL_SRC_DEST_SYNC_SOURCE BIT24 + +#define DMA4_CSR_DROP BIT1 +#define DMA4_CSR_HALF BIT2 +#define DMA4_CSR_FRAME BIT3 +#define DMA4_CSR_LAST BIT4 +#define DMA4_CSR_BLOCK BIT5 +#define DMA4_CSR_SYNC BIT6 +#define DMA4_CSR_PKT BIT7 +#define DMA4_CSR_TRANS_ERR BIT8 +#define DMA4_CSR_SECURE_ERR BIT9 +#define DMA4_CSR_SUPERVISOR_ERR BIT10 +#define DMA4_CSR_MISALIGNED_ADRS_ERR BIT11 +#define DMA4_CSR_DRAIN_END BIT12 +#define DMA4_CSR_RESET 0x1FE +#define DMA4_CSR_ERR (DMA4_CSR_TRANS_ERR | DMA4_CSR_SECURE_ERR | DMA4_CSR_SUPERVISOR_ERR | DMA4_CSR_MISALIGNED_ADRS_ERR) + +// same mapping as CSR except for SYNC. Enable all since we are polling +#define DMA4_CICR_ENABLE_ALL 0x1FBE + + +#endif + diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Gpio.h b/Omap44xxPkg/Include/Omap4430/Omap4430Gpio.h new file mode 100644 index 000000000..dcaa74cce --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Gpio.h @@ -0,0 +1,132 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430GPIO_H__ +#define __OMAP4430GPIO_H__ + +#define GPIO1_BASE (0x4A310000) +#define GPIO2_BASE (0x48055000) +#define GPIO3_BASE (0x48057000) +#define GPIO4_BASE (0x48059000) +#define GPIO5_BASE (0x4805B000) +#define GPIO6_BASE (0x4805D000) + +// TODO: review below defines, offsets changed from omap3 to omap4 +#define GPIO_SYSCONFIG (0x0010) +#define GPIO_SYSSTATUS (0x0014) +#define GPIO_IRQSTATUS1 (0x0018) +#define GPIO_IRQENABLE1 (0x001C) +#define GPIO_WAKEUPENABLE (0x0020) +#define GPIO_IRQSTATUS2 (0x0028) +#define GPIO_IRQENABLE2 (0x002C) +#define GPIO_CTRL (0x0030) +#define GPIO_OE (0x0134) +#define GPIO_DATAIN (0x0138) +#define GPIO_DATAOUT (0x003C) +#define GPIO_LEVELDETECT0 (0x0040) +#define GPIO_LEVELDETECT1 (0x0044) +#define GPIO_RISINGDETECT (0x0048) +#define GPIO_FALLINGDETECT (0x004C) +#define GPIO_DEBOUNCENABLE (0x0050) +#define GPIO_DEBOUNCINGTIME (0x0054) +#define GPIO_CLEARIRQENABLE1 (0x0060) +#define GPIO_SETIRQENABLE1 (0x0064) +#define GPIO_CLEARIRQENABLE2 (0x0070) +#define GPIO_SETIRQENABLE2 (0x0074) +#define GPIO_CLEARWKUENA (0x0080) +#define GPIO_SETWKUENA (0x0084) +#define GPIO_CLEARDATAOUT (0x0190) +#define GPIO_SETDATAOUT (0x0194) + +#define GPIO_SYSCONFIG_IDLEMODE_MASK (3UL << 3) +#define GPIO_SYSCONFIG_IDLEMODE_FORCE (0UL << 3) +#define GPIO_SYSCONFIG_IDLEMODE_NONE BIT3 +#define GPIO_SYSCONFIG_IDLEMODE_SMART (2UL << 3) +#define GPIO_SYSCONFIG_ENAWAKEUP_MASK BIT2 +#define GPIO_SYSCONFIG_ENAWAKEUP_DISABLE (0UL << 2) +#define GPIO_SYSCONFIG_ENAWAKEUP_ENABLE BIT2 +#define GPIO_SYSCONFIG_SOFTRESET_MASK BIT1 +#define GPIO_SYSCONFIG_SOFTRESET_NORMAL (0UL << 1) +#define GPIO_SYSCONFIG_SOFTRESET_RESET BIT1 +#define GPIO_SYSCONFIG_AUTOIDLE_MASK BIT0 +#define GPIO_SYSCONFIG_AUTOIDLE_FREE_RUN (0UL << 0) +#define GPIO_SYSCONFIG_AUTOIDLE_ON BIT0 + +#define GPIO_SYSSTATUS_RESETDONE_MASK BIT0 +#define GPIO_SYSSTATUS_RESETDONE_ONGOING (0UL << 0) +#define GPIO_SYSSTATUS_RESETDONE_COMPLETE BIT0 + +#define GPIO_IRQSTATUS_MASK(x) (1UL << (x)) +#define GPIO_IRQSTATUS_NOT_TRIGGERED(x) (0UL << (x)) +#define GPIO_IRQSTATUS_TRIGGERED(x) (1UL << (x)) +#define GPIO_IRQSTATUS_CLEAR(x) (1UL << (x)) + +#define GPIO_IRQENABLE_MASK(x) (1UL << (x)) +#define GPIO_IRQENABLE_DISABLE(x) (0UL << (x)) +#define GPIO_IRQENABLE_ENABLE(x) (1UL << (x)) + +#define GPIO_WAKEUPENABLE_MASK(x) (1UL << (x)) +#define GPIO_WAKEUPENABLE_DISABLE(x) (0UL << (x)) +#define GPIO_WAKEUPENABLE_ENABLE(x) (1UL << (x)) + +#define GPIO_CTRL_GATINGRATIO_MASK (3UL << 1) +#define GPIO_CTRL_GATINGRATIO_DIV_1 (0UL << 1) +#define GPIO_CTRL_GATINGRATIO_DIV_2 BIT1 +#define GPIO_CTRL_GATINGRATIO_DIV_4 (2UL << 1) +#define GPIO_CTRL_GATINGRATIO_DIV_8 (3UL << 1) +#define GPIO_CTRL_DISABLEMODULE_MASK BIT0 +#define GPIO_CTRL_DISABLEMODULE_ENABLE (0UL << 0) +#define GPIO_CTRL_DISABLEMODULE_DISABLE BIT0 + +#define GPIO_OE_MASK(x) (1UL << (x)) +#define GPIO_OE_OUTPUT(x) (0UL << (x)) +#define GPIO_OE_INPUT(x) (1UL << (x)) + +#define GPIO_DATAIN_MASK(x) (1UL << (x)) + +#define GPIO_DATAOUT_MASK(x) (1UL << (x)) + +#define GPIO_LEVELDETECT_MASK(x) (1UL << (x)) +#define GPIO_LEVELDETECT_DISABLE(x) (0UL << (x)) +#define GPIO_LEVELDETECT_ENABLE(x) (1UL << (x)) + +#define GPIO_RISINGDETECT_MASK(x) (1UL << (x)) +#define GPIO_RISINGDETECT_DISABLE(x) (0UL << (x)) +#define GPIO_RISINGDETECT_ENABLE(x) (1UL << (x)) + +#define GPIO_FALLINGDETECT_MASK(x) (1UL << (x)) +#define GPIO_FALLINGDETECT_DISABLE(x) (0UL << (x)) +#define GPIO_FALLINGDETECT_ENABLE(x) (1UL << (x)) + +#define GPIO_DEBOUNCENABLE_MASK(x) (1UL << (x)) +#define GPIO_DEBOUNCENABLE_DISABLE(x) (0UL << (x)) +#define GPIO_DEBOUNCENABLE_ENABLE(x) (1UL << (x)) + +#define GPIO_DEBOUNCINGTIME_MASK (0xFF) +#define GPIO_DEBOUNCINGTIME_US(x) ((((x) / 31) - 1) & GPIO_DEBOUNCINGTIME_MASK) + +#define GPIO_CLEARIRQENABLE_BIT(x) (1UL << (x)) + +#define GPIO_SETIRQENABLE_BIT(x) (1UL << (x)) + +#define GPIO_CLEARWKUENA_BIT(x) (1UL << (x)) + +#define GPIO_SETWKUENA_BIT(x) (1UL << (x)) + +#define GPIO_CLEARDATAOUT_BIT(x) (1UL << (x)) + +#define GPIO_SETDATAOUT_BIT(x) (1UL << (x)) + +#endif // __OMAP4430GPIO_H__ + diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Gpmc.h b/Omap44xxPkg/Include/Omap4430/Omap4430Gpmc.h new file mode 100644 index 000000000..7d105cea4 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Gpmc.h @@ -0,0 +1,107 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430GPMC_H__ +#define __OMAP4430GPMC_H__ + +#define GPMC_BASE (0x50000000) + +//GPMC NAND definitions. +#define GPMC_SYSCONFIG (GPMC_BASE + 0x10) +#define SMARTIDLEMODE (0x2UL << 3) + +#define GPMC_SYSSTATUS (GPMC_BASE + 0x14) +#define GPMC_IRQSTATUS (GPMC_BASE + 0x18) +#define GPMC_IRQENABLE (GPMC_BASE + 0x1C) + +#define GPMC_TIMEOUT_CONTROL (GPMC_BASE + 0x40) +#define TIMEOUTENABLE BIT0 +#define TIMEOUTDISABLE (0x0UL << 0) + +#define GPMC_ERR_ADDRESS (GPMC_BASE + 0x44) +#define GPMC_ERR_TYPE (GPMC_BASE + 0x48) + +#define GPMC_CONFIG (GPMC_BASE + 0x50) +#define WRITEPROTECT_HIGH BIT4 +#define WRITEPROTECT_LOW (0x0UL << 4) + +#define GPMC_STATUS (GPMC_BASE + 0x54) + +#define GPMC_CONFIG1_0 (GPMC_BASE + 0x60) +#define DEVICETYPE_NOR (0x0UL << 10) +#define DEVICETYPE_NAND (0x2UL << 10) +#define DEVICESIZE_X8 (0x0UL << 12) +#define DEVICESIZE_X16 BIT12 + +#define GPMC_CONFIG2_0 (GPMC_BASE + 0x64) +#define CSONTIME (0x0UL << 0) +#define CSRDOFFTIME (0x14UL << 8) +#define CSWROFFTIME (0x14UL << 16) + +#define GPMC_CONFIG3_0 (GPMC_BASE + 0x68) +#define ADVRDOFFTIME (0x14UL << 8) +#define ADVWROFFTIME (0x14UL << 16) + +#define GPMC_CONFIG4_0 (GPMC_BASE + 0x6C) +#define OEONTIME BIT0 +#define OEOFFTIME (0xFUL << 8) +#define WEONTIME BIT16 +#define WEOFFTIME (0xFUL << 24) + +#define GPMC_CONFIG5_0 (GPMC_BASE + 0x70) +#define RDCYCLETIME (0x14UL << 0) +#define WRCYCLETIME (0x14UL << 8) +#define RDACCESSTIME (0xCUL << 16) +#define PAGEBURSTACCESSTIME BIT24 + +#define GPMC_CONFIG6_0 (GPMC_BASE + 0x74) +#define CYCLE2CYCLESAMECSEN BIT7 +#define CYCLE2CYCLEDELAY (0xAUL << 8) +#define WRDATAONADMUXBUS (0xFUL << 16) +#define WRACCESSTIME BIT24 + +#define GPMC_CONFIG7_0 (GPMC_BASE + 0x78) +#define BASEADDRESS (0x30UL << 0) +#define CSVALID BIT6 +#define MASKADDRESS_128MB (0x8UL << 8) + +#define GPMC_NAND_COMMAND_0 (GPMC_BASE + 0x7C) +#define GPMC_NAND_ADDRESS_0 (GPMC_BASE + 0x80) +#define GPMC_NAND_DATA_0 (GPMC_BASE + 0x84) + +#define GPMC_ECC_CONFIG (GPMC_BASE + 0x1F4) +#define ECCENABLE BIT0 +#define ECCDISABLE (0x0UL << 0) +#define ECCCS_0 (0x0UL << 1) +#define ECC16B BIT7 + +#define GPMC_ECC_CONTROL (GPMC_BASE + 0x1F8) +#define ECCPOINTER_REG1 BIT0 +#define ECCCLEAR BIT8 + +#define GPMC_ECC_SIZE_CONFIG (GPMC_BASE + 0x1FC) +#define ECCSIZE0_512BYTES (0xFFUL << 12) +#define ECCSIZE1_512BYTES (0xFFUL << 22) + +#define GPMC_ECC1_RESULT (GPMC_BASE + 0x200) +#define GPMC_ECC2_RESULT (GPMC_BASE + 0x204) +#define GPMC_ECC3_RESULT (GPMC_BASE + 0x208) +#define GPMC_ECC4_RESULT (GPMC_BASE + 0x20C) +#define GPMC_ECC5_RESULT (GPMC_BASE + 0x210) +#define GPMC_ECC6_RESULT (GPMC_BASE + 0x214) +#define GPMC_ECC7_RESULT (GPMC_BASE + 0x218) +#define GPMC_ECC8_RESULT (GPMC_BASE + 0x21C) +#define GPMC_ECC9_RESULT (GPMC_BASE + 0x220) + +#endif //__OMAP4430GPMC_H__ diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430I2c.h b/Omap44xxPkg/Include/Omap4430/Omap4430I2c.h new file mode 100644 index 000000000..50d5a4a05 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430I2c.h @@ -0,0 +1,62 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430I2C_H__ +#define __OMAP4430I2C_H__ + +//I2C register definitions. +#define I2C1BASE 0x48070000 + +#define I2C_IE (I2C1BASE + 0x84) +#define XRDY_IE BIT4 +#define RRDY_IE BIT3 +#define ARDY_IE BIT2 +#define NACK_IE BIT1 + +#define I2C_STAT (I2C1BASE + 0x88) +#define BB BIT12 +#define XRDY BIT4 +#define RRDY BIT3 +#define ARDY BIT2 +#define NACK BIT1 + +#define I2C_WE (I2C1BASE + 0x34) +#define I2C_SYSS (I2C1BASE + 0x90) +#define I2C_BUF (I2C1BASE + 0x94) +#define I2C_CNT (I2C1BASE + 0x98) +#define I2C_DATA (I2C1BASE + 0x9C) +#define I2C_SYSC (I2C1BASE + 0x10) + +#define I2C_CON (I2C1BASE + 0xA4) +#define STT BIT0 +#define STP BIT1 +#define XSA BIT8 +#define TRX BIT9 +#define MST BIT10 +#define I2C_EN BIT15 + +//#define I2C_OA0 (I2C1BASE + 0x28) +#define I2C_SA (I2C1BASE + 0xAC) +#define I2C_PSC (I2C1BASE + 0xB0) +#define I2C_SCLL (I2C1BASE + 0xB4) +#define I2C_SCLH (I2C1BASE + 0xB8) +#define I2C_SYSTEST (I2C1BASE + 0xBC) +#define I2C_BUFSTAT (I2C1BASE + 0xC0) +#define I2C_OA1 (I2C1BASE + 0xC4) +#define I2C_OA2 (I2C1BASE + 0xC8) +#define I2C_OA3 (I2C1BASE + 0xCC) +#define I2C_ACTOA (I2C1BASE + 0xD0) +#define I2C_SBLOCK (I2C1BASE + 0xD4) + +#endif //__OMAP4430I2C_H__ diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Interrupt.h b/Omap44xxPkg/Include/Omap4430/Omap4430Interrupt.h new file mode 100644 index 000000000..2b9968f51 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Interrupt.h @@ -0,0 +1,48 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430INTERRUPT_H__ +#define __OMAP4430INTERRUPT_H__ + +#define INTERRUPT_BASE (0x48200000) + +#define INT_NROF_VECTORS (96) +#define MAX_VECTOR (INT_NROF_VECTORS - 1) +#define INTCPS_SYSCONFIG (INTERRUPT_BASE + 0x0010) +#define INTCPS_SYSSTATUS (INTERRUPT_BASE + 0x0014) +#define INTCPS_SIR_IRQ (INTERRUPT_BASE + 0x0040) +#define INTCPS_SIR_IFQ (INTERRUPT_BASE + 0x0044) +#define INTCPS_CONTROL (INTERRUPT_BASE + 0x0048) +#define INTCPS_PROTECTION (INTERRUPT_BASE + 0x004C) +#define INTCPS_IDLE (INTERRUPT_BASE + 0x0050) +#define INTCPS_IRQ_PRIORITY (INTERRUPT_BASE + 0x0060) +#define INTCPS_FIQ_PRIORITY (INTERRUPT_BASE + 0x0064) +#define INTCPS_THRESHOLD (INTERRUPT_BASE + 0x0068) +#define INTCPS_ITR(n) (INTERRUPT_BASE + 0x0080 + (0x20 * (n))) +#define INTCPS_MIR(n) (INTERRUPT_BASE + 0x0084 + (0x20 * (n))) +#define INTCPS_MIR_CLEAR(n) (INTERRUPT_BASE + 0x0088 + (0x20 * (n))) +#define INTCPS_MIR_SET(n) (INTERRUPT_BASE + 0x008C + (0x20 * (n))) +#define INTCPS_ISR_SET(n) (INTERRUPT_BASE + 0x0090 + (0x20 * (n))) +#define INTCPS_ISR_CLEAR(n) (INTERRUPT_BASE + 0x0094 + (0x20 * (n))) +#define INTCPS_PENDING_IRQ(n) (INTERRUPT_BASE + 0x0098 + (0x20 * (n))) +#define INTCPS_PENDING_FIQ(n) (INTERRUPT_BASE + 0x009C + (0x20 * (n))) +#define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m))) + +#define INTCPS_ILR_FIQ BIT0 +#define INTCPS_SIR_IRQ_MASK (0x7F) +#define INTCPS_CONTROL_NEWIRQAGR BIT0 +#define INTCPS_CONTROL_NEWFIQAGR BIT1 + +#endif // __OMAP4430INTERRUPT_H__ + diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430MMCHS.h b/Omap44xxPkg/Include/Omap4430/Omap4430MMCHS.h new file mode 100644 index 000000000..579236104 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430MMCHS.h @@ -0,0 +1,214 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430SDIO_H__ +#define __OMAP4430SDIO_H__ + +//MMC/SD/SDIO1 register definitions. +#define MMCHS1BASE 0x4809C000 +#define MMC_REFERENCE_CLK (96000000) + +#define MMCHS_SYSCONFIG (MMCHS1BASE + 0x110) +#define SOFTRESET BIT1 +#define ENAWAKEUP BIT2 + +#define MMCHS_SYSSTATUS (MMCHS1BASE + 0x114) +#define RESETDONE_MASK BIT0 +#define RESETDONE BIT0 + +#define MMCHS_CSRE (MMCHS1BASE + 0x124) +#define MMCHS_SYSTEST (MMCHS1BASE + 0x128) + +#define MMCHS_CON (MMCHS1BASE + 0x12C) +#define OD BIT0 +#define NOINIT (0x0UL << 1) +#define INIT BIT1 +#define HR BIT2 +#define STR BIT3 +#define MODE BIT4 +#define DW8_1_4_BIT (0x0UL << 5) +#define DW8_8_BIT BIT5 +#define MIT BIT6 +#define CDP BIT7 +#define WPP BIT8 +#define CTPL BIT11 +#define CEATA_OFF (0x0UL << 12) +#define CEATA_ON BIT12 + +#define MMCHS_PWCNT (MMCHS1BASE + 0x130) + +#define MMCHS_BLK (MMCHS1BASE + 0x204) +#define BLEN_512BYTES (0x200UL << 0) + +#define MMCHS_ARG (MMCHS1BASE + 0x208) + +#define MMCHS_CMD (MMCHS1BASE + 0x20C) +#define DE_ENABLE BIT0 +#define BCE_ENABLE BIT1 +#define ACEN_ENABLE BIT2 +#define DDIR_READ BIT4 +#define DDIR_WRITE (0x0UL << 4) +#define MSBS_SGLEBLK (0x0UL << 5) +#define MSBS_MULTBLK BIT5 +#define RSP_TYPE_MASK (0x3UL << 16) +#define RSP_TYPE_136BITS BIT16 +#define RSP_TYPE_48BITS (0x2UL << 16) +#define CCCE_ENABLE BIT19 +#define CICE_ENABLE BIT20 +#define DP_ENABLE BIT21 +#define INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24) + +#define MMCHS_RSP10 (MMCHS1BASE + 0x210) +#define MMCHS_RSP32 (MMCHS1BASE + 0x214) +#define MMCHS_RSP54 (MMCHS1BASE + 0x218) +#define MMCHS_RSP76 (MMCHS1BASE + 0x21C) +#define MMCHS_DATA (MMCHS1BASE + 0x220) + +#define MMCHS_PSTATE (MMCHS1BASE + 0x224) +#define CMDI_MASK BIT0 +#define CMDI_ALLOWED (0x0UL << 0) +#define CMDI_NOT_ALLOWED BIT0 +#define DATI_MASK BIT1 +#define DATI_ALLOWED (0x0UL << 1) +#define DATI_NOT_ALLOWED BIT1 + +#define MMCHS_HCTL (MMCHS1BASE + 0x228) +#define DTW_1_BIT (0x0UL << 1) +#define DTW_4_BIT BIT1 +#define SDBP_MASK BIT8 +#define SDBP_OFF (0x0UL << 8) +#define SDBP_ON BIT8 +#define SDVS_1_8_V (0x5UL << 9) +#define SDVS_3_0_V (0x6UL << 9) +#define IWE BIT24 + +#define MMCHS_SYSCTL (MMCHS1BASE + 0x22C) +#define ICE BIT0 +#define ICS_MASK BIT1 +#define ICS BIT1 +#define CEN BIT2 +#define CLKD_MASK (0x3FFUL << 6) +#define CLKD_80KHZ (0x258UL) //(96*1000/80)/2 +#define CLKD_400KHZ (0xF0UL) +#define DTO_MASK (0xFUL << 16) +#define DTO_VAL (0xEUL << 16) +#define SRA BIT24 +#define SRC_MASK BIT25 +#define SRC BIT25 +#define SRD BIT26 + +#define MMCHS_STAT (MMCHS1BASE + 0x230) +#define CC BIT0 +#define TC BIT1 +#define BWR BIT4 +#define BRR BIT5 +#define ERRI BIT15 +#define CTO BIT16 +#define DTO BIT20 +#define DCRC BIT21 +#define DEB BIT22 + +#define MMCHS_IE (MMCHS1BASE + 0x234) +#define CC_EN BIT0 +#define TC_EN BIT1 +#define BWR_EN BIT4 +#define BRR_EN BIT5 +#define CTO_EN BIT16 +#define CCRC_EN BIT17 +#define CEB_EN BIT18 +#define CIE_EN BIT19 +#define DTO_EN BIT20 +#define DCRC_EN BIT21 +#define DEB_EN BIT22 +#define CERR_EN BIT28 +#define BADA_EN BIT29 + +#define MMCHS_ISE (MMCHS1BASE + 0x238) +#define CC_SIGEN BIT0 +#define TC_SIGEN BIT1 +#define BWR_SIGEN BIT4 +#define BRR_SIGEN BIT5 +#define CTO_SIGEN BIT16 +#define CCRC_SIGEN BIT17 +#define CEB_SIGEN BIT18 +#define CIE_SIGEN BIT19 +#define DTO_SIGEN BIT20 +#define DCRC_SIGEN BIT21 +#define DEB_SIGEN BIT22 +#define CERR_SIGEN BIT28 +#define BADA_SIGEN BIT29 + +#define MMCHS_AC12 (MMCHS1BASE + 0x23C) + +#define MMCHS_CAPA (MMCHS1BASE + 0x240) +#define VS30 BIT25 +#define VS18 BIT26 + +#define MMCHS_CUR_CAPA (MMCHS1BASE + 0x248) +#define MMCHS_REV (MMCHS1BASE + 0x2FC) + +#define CMD0 INDX(0) +#define CMD0_INT_EN (CC_EN | CEB_EN) + +#define CMD1 (INDX(1) | RSP_TYPE_48BITS) +#define CMD1_INT_EN (CC_EN | CEB_EN | CTO_EN) + +#define CMD2 (INDX(2) | CCCE_ENABLE | RSP_TYPE_136BITS) +#define CMD2_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#define CMD3 (INDX(3) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) +#define CMD3_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#define CMD5 (INDX(5) | RSP_TYPE_48BITS) +#define CMD5_INT_EN (CC_EN | CEB_EN | CTO_EN) + +#define CMD7 (INDX(7) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) +#define CMD7_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#define CMD8 (INDX(8) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) +#define CMD8_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) +//Reserved(0)[12:31], Supply voltage(1)[11:8], check pattern(0xCE)[7:0] = 0x1CE +#define CMD8_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0) + +#define CMD9 (INDX(9) | CCCE_ENABLE | RSP_TYPE_136BITS) +#define CMD9_INT_EN (CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#define CMD16 (INDX(16) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) +#define CMD16_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#define CMD17 (INDX(17) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_READ) +#define CMD17_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN) + +#define CMD18 (INDX(18) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE) +#define CMD18_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN) + +#define CMD23 (INDX(23) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) +#define CMD23_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#define CMD24 (INDX(24) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_WRITE) +#define CMD24_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BWR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN) + +#define CMD25 (INDX(25) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE) +#define CMD25_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN) + +#define CMD55 (INDX(55) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) +#define CMD55_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#define ACMD41 (INDX(41) | RSP_TYPE_48BITS) +#define ACMD41_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#define ACMD6 (INDX(6) | RSP_TYPE_48BITS) +#define ACMD6_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) + +#endif //__OMAP4430SDIO_H__ diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430PadConfiguration.h b/Omap44xxPkg/Include/Omap4430/Omap4430PadConfiguration.h new file mode 100644 index 000000000..449e99662 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430PadConfiguration.h @@ -0,0 +1,334 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430_PAD_CONFIGURATION_H__ +#define __OMAP4430_PAD_CONFIGURATION_H__ + +#define OMAP4430_CONTROL_MODULE_CORE_BASE 0x4A100000 +#define OMAP4430_CONTROL_MODULE_WKUP_BASE 0x4A31E000 + +#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x4A31E05A + +#ifdef CONFIG_OFF_PADCONF +#define OFF_PD (1 << 12) +#define OFF_PU (3 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (2 << 10) +#define OFF_IN (1 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (1 << 9) +#else +#define OFF_PD (0 << 12) +#define OFF_PU (0 << 12) +#define OFF_OUT_PTD (0 << 10) +#define OFF_OUT_PTU (0 << 10) +#define OFF_IN (0 << 10) +#define OFF_OUT (0 << 10) +#define OFF_EN (0 << 9) +#endif + +#define IEN (1 << 8) +#define IDIS (0 << 8) +#define PTU (3 << 3) +#define PTD (1 << 3) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +#define SAFE_MODE M7 + +#ifdef CONFIG_OFF_PADCONF +#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) +#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) +#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) +#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) +#else +#define OFF_IN_PD 0 +#define OFF_IN_PU 0 +#define OFF_OUT_PD 0 +#define OFF_OUT_PU 0 +#endif + +#define CORE_REVISION 0x0000 +#define CORE_HWINFO 0x0004 +#define CORE_SYSCONFIG 0x0010 +#define GPMC_AD0 0x0040 +#define GPMC_AD1 0x0042 +#define GPMC_AD2 0x0044 +#define GPMC_AD3 0x0046 +#define GPMC_AD4 0x0048 +#define GPMC_AD5 0x004A +#define GPMC_AD6 0x004C +#define GPMC_AD7 0x004E +#define GPMC_AD8 0x0050 +#define GPMC_AD9 0x0052 +#define GPMC_AD10 0x0054 +#define GPMC_AD11 0x0056 +#define GPMC_AD12 0x0058 +#define GPMC_AD13 0x005A +#define GPMC_AD14 0x005C +#define GPMC_AD15 0x005E +#define GPMC_A16 0x0060 +#define GPMC_A17 0x0062 +#define GPMC_A18 0x0064 +#define GPMC_A19 0x0066 +#define GPMC_A20 0x0068 +#define GPMC_A21 0x006A +#define GPMC_A22 0x006C +#define GPMC_A23 0x006E +#define GPMC_A24 0x0070 +#define GPMC_A25 0x0072 +#define GPMC_NCS0 0x0074 +#define GPMC_NCS1 0x0076 +#define GPMC_NCS2 0x0078 +#define GPMC_NCS3 0x007A +#define GPMC_NWP 0x007C +#define GPMC_CLK 0x007E +#define GPMC_NADV_ALE 0x0080 +#define GPMC_NOE 0x0082 +#define GPMC_NWE 0x0084 +#define GPMC_NBE0_CLE 0x0086 +#define GPMC_NBE1 0x0088 +#define GPMC_WAIT0 0x008A +#define GPMC_WAIT1 0x008C +#define C2C_DATA11 0x008E +#define C2C_DATA12 0x0090 +#define C2C_DATA13 0x0092 +#define C2C_DATA14 0x0094 +#define C2C_DATA15 0x0096 +#define HDMI_HPD 0x0098 +#define HDMI_CEC 0x009A +#define HDMI_DDC_SCL 0x009C +#define HDMI_DDC_SDA 0x009E +#define CSI21_DX0 0x00A0 +#define CSI21_DY0 0x00A2 +#define CSI21_DX1 0x00A4 +#define CSI21_DY1 0x00A6 +#define CSI21_DX2 0x00A8 +#define CSI21_DY2 0x00AA +#define CSI21_DX3 0x00AC +#define CSI21_DY3 0x00AE +#define CSI21_DX4 0x00B0 +#define CSI21_DY4 0x00B2 +#define CSI22_DX0 0x00B4 +#define CSI22_DY0 0x00B6 +#define CSI22_DX1 0x00B8 +#define CSI22_DY1 0x00BA +#define CAM_SHUTTER 0x00BC +#define CAM_STROBE 0x00BE +#define CAM_GLOBALRESET 0x00C0 +#define USBB1_ULPITLL_CLK 0x00C2 +#define USBB1_ULPITLL_STP 0x00C4 +#define USBB1_ULPITLL_DIR 0x00C6 +#define USBB1_ULPITLL_NXT 0x00C8 +#define USBB1_ULPITLL_DAT0 0x00CA +#define USBB1_ULPITLL_DAT1 0x00CC +#define USBB1_ULPITLL_DAT2 0x00CE +#define USBB1_ULPITLL_DAT3 0x00D0 +#define USBB1_ULPITLL_DAT4 0x00D2 +#define USBB1_ULPITLL_DAT5 0x00D4 +#define USBB1_ULPITLL_DAT6 0x00D6 +#define USBB1_ULPITLL_DAT7 0x00D8 +#define USBB1_HSIC_DATA 0x00DA +#define USBB1_HSIC_STROBE 0x00DC +#define USBC1_ICUSB_DP 0x00DE +#define USBC1_ICUSB_DM 0x00E0 +#define SDMMC1_CLK 0x00E2 +#define SDMMC1_CMD 0x00E4 +#define SDMMC1_DAT0 0x00E6 +#define SDMMC1_DAT1 0x00E8 +#define SDMMC1_DAT2 0x00EA +#define SDMMC1_DAT3 0x00EC +#define SDMMC1_DAT4 0x00EE +#define SDMMC1_DAT5 0x00F0 +#define SDMMC1_DAT6 0x00F2 +#define SDMMC1_DAT7 0x00F4 +#define ABE_MCBSP2_CLKX 0x00F6 +#define ABE_MCBSP2_DR 0x00F8 +#define ABE_MCBSP2_DX 0x00FA +#define ABE_MCBSP2_FSX 0x00FC +#define ABE_MCBSP1_CLKX 0x00FE +#define ABE_MCBSP1_DR 0x0100 +#define ABE_MCBSP1_DX 0x0102 +#define ABE_MCBSP1_FSX 0x0104 +#define ABE_PDM_UL_DATA 0x0106 +#define ABE_PDM_DL_DATA 0x0108 +#define ABE_PDM_FRAME 0x010A +#define ABE_PDM_LB_CLK 0x010C +#define ABE_CLKS 0x010E +#define ABE_DMIC_CLK1 0x0110 +#define ABE_DMIC_DIN1 0x0112 +#define ABE_DMIC_DIN2 0x0114 +#define ABE_DMIC_DIN3 0x0116 +#define UART2_CTS 0x0118 +#define UART2_RTS 0x011A +#define UART2_RX 0x011C +#define UART2_TX 0x011E +#define HDQ_SIO 0x0120 +#define I2C1_SCL 0x0122 +#define I2C1_SDA 0x0124 +#define I2C2_SCL 0x0126 +#define I2C2_SDA 0x0128 +#define I2C3_SCL 0x012A +#define I2C3_SDA 0x012C +#define I2C4_SCL 0x012E +#define I2C4_SDA 0x0130 +#define MCSPI1_CLK 0x0132 +#define MCSPI1_SOMI 0x0134 +#define MCSPI1_SIMO 0x0136 +#define MCSPI1_CS0 0x0138 +#define MCSPI1_CS1 0x013A +#define MCSPI1_CS2 0x013C +#define MCSPI1_CS3 0x013E +#define UART3_CTS_RCTX 0x0140 +#define UART3_RTS_SD 0x0142 +#define UART3_RX_IRRX 0x0144 +#define UART3_TX_IRTX 0x0146 +#define SDMMC5_CLK 0x0148 +#define SDMMC5_CMD 0x014A +#define SDMMC5_DAT0 0x014C +#define SDMMC5_DAT1 0x014E +#define SDMMC5_DAT2 0x0150 +#define SDMMC5_DAT3 0x0152 +#define MCSPI4_CLK 0x0154 +#define MCSPI4_SIMO 0x0156 +#define MCSPI4_SOMI 0x0158 +#define MCSPI4_CS0 0x015A +#define UART4_RX 0x015C +#define UART4_TX 0x015E +#define USBB2_ULPITLL_CLK 0x0160 +#define USBB2_ULPITLL_STP 0x0162 +#define USBB2_ULPITLL_DIR 0x0164 +#define USBB2_ULPITLL_NXT 0x0166 +#define USBB2_ULPITLL_DAT0 0x0168 +#define USBB2_ULPITLL_DAT1 0x016A +#define USBB2_ULPITLL_DAT2 0x016C +#define USBB2_ULPITLL_DAT3 0x016E +#define USBB2_ULPITLL_DAT4 0x0170 +#define USBB2_ULPITLL_DAT5 0x0172 +#define USBB2_ULPITLL_DAT6 0x0174 +#define USBB2_ULPITLL_DAT7 0x0176 +#define USBB2_HSIC_DATA 0x0178 +#define USBB2_HSIC_STROBE 0x017A +#define UNIPRO_TX0 0x017C +#define UNIPRO_TY0 0x017E +#define UNIPRO_TX1 0x0180 +#define UNIPRO_TY1 0x0182 +#define UNIPRO_TX2 0x0184 +#define UNIPRO_TY2 0x0186 +#define UNIPRO_RX0 0x0188 +#define UNIPRO_RY0 0x018A +#define UNIPRO_RX1 0x018C +#define UNIPRO_RY1 0x018E +#define UNIPRO_RX2 0x0190 +#define UNIPRO_RY2 0x0192 +#define USBA0_OTG_CE 0x0194 +#define USBA0_OTG_DP 0x0196 +#define USBA0_OTG_DM 0x0198 +#define FREF_CLK1_OUT 0x019A +#define FREF_CLK2_OUT 0x019C +#define SYS_NIRQ1 0x019E +#define SYS_NIRQ2 0x01A0 +#define SYS_BOOT0 0x01A2 +#define SYS_BOOT1 0x01A4 +#define SYS_BOOT2 0x01A6 +#define SYS_BOOT3 0x01A8 +#define SYS_BOOT4 0x01AA +#define SYS_BOOT5 0x01AC +#define DPM_EMU0 0x01AE +#define DPM_EMU1 0x01B0 +#define DPM_EMU2 0x01B2 +#define DPM_EMU3 0x01B4 +#define DPM_EMU4 0x01B6 +#define DPM_EMU5 0x01B8 +#define DPM_EMU6 0x01BA +#define DPM_EMU7 0x01BC +#define DPM_EMU8 0x01BE +#define DPM_EMU9 0x01C0 +#define DPM_EMU10 0x01C2 +#define DPM_EMU11 0x01C4 +#define DPM_EMU12 0x01C6 +#define DPM_EMU13 0x01C8 +#define DPM_EMU14 0x01CA +#define DPM_EMU15 0x01CC +#define DPM_EMU16 0x01CE +#define DPM_EMU17 0x01D0 +#define DPM_EMU18 0x01D2 +#define DPM_EMU19 0x01D4 +#define WAKEUPEVENT_0 0x01D8 +#define WAKEUPEVENT_1 0x01DC +#define WAKEUPEVENT_2 0x01E0 +#define WAKEUPEVENT_3 0x01E4 +#define WAKEUPEVENT_4 0x01E8 +#define WAKEUPEVENT_5 0x01EC +#define WAKEUPEVENT_6 0x01F0 + +#define WKUP_REVISION 0x0000 +#define WKUP_HWINFO 0x0004 +#define WKUP_SYSCONFIG 0x0010 +#define PAD0_SIM_IO 0x0040 +#define PAD1_SIM_CLK 0x0042 +#define PAD0_SIM_RESET 0x0044 +#define PAD1_SIM_CD 0x0046 +#define PAD0_SIM_PWRCTRL 0x0048 +#define PAD1_SR_SCL 0x004A +#define PAD0_SR_SDA 0x004C +#define PAD1_FREF_XTAL_IN 0x004E +#define PAD0_FREF_SLICER_IN 0x0050 +#define PAD1_FREF_CLK_IOREQ 0x0052 +#define PAD0_FREF_CLK0_OUT 0x0054 +#define PAD1_FREF_CLK3_REQ 0x0056 +#define PAD0_FREF_CLK3_OUT 0x0058 +#define PAD1_FREF_CLK4_REQ 0x005A +#define PAD0_FREF_CLK4_OUT 0x005C +#define PAD1_SYS_32K 0x005E +#define PAD0_SYS_NRESPWRON 0x0060 +#define PAD1_SYS_NRESWARM 0x0062 +#define PAD0_SYS_PWR_REQ 0x0064 +#define PAD1_SYS_PWRON_RESET 0x0066 +#define PAD0_SYS_BOOT6 0x0068 +#define PAD1_SYS_BOOT7 0x006A +#define PAD0_JTAG_NTRST 0x006C +#define PAD1_JTAG_TCK 0x006D +#define PAD0_JTAG_RTCK 0x0070 +#define PAD1_JTAG_TMS_TMSC 0x0072 +#define PAD0_JTAG_TDI 0x0074 +#define PAD1_JTAG_TDO 0x0076 +#define PADCONF_WAKEUPEVENT_0 0x007C +#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 +#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 +#define PADCONF_MODE 0x05A8 +#define CONTROL_XTAL_OSCILLATOR 0x05AC +#define CONTROL_CONTROL_I2C_2 0x0604 +#define CONTROL_CONTROL_JTAG 0x0608 +#define CONTROL_CONTROL_SYS 0x060C +#define CONTROL_SPARE_RW 0x0614 +#define CONTROL_SPARE_R 0x0618 +#define CONTROL_SPARE_R_C0 0x061C + +typedef struct { + UINT16 Off; + UINT16 Val; + +} PAD_CONFIGURATION; + +#endif //__OMAP4430_PAD_CONFIGURATION_H__ diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Prcm.h b/Omap44xxPkg/Include/Omap4430/Omap4430Prcm.h new file mode 100644 index 000000000..40b6e1f36 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Prcm.h @@ -0,0 +1,148 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430PRCM_H__ +#define __OMAP4430PRCM_H__ + +// CONTROL_CORE + +#define CONTROL_CORE_U_BASE (0x4A002000) +#define CONTROL_CORE_ID_CODE (CONTROL_CORE_U_BASE+0x204) +#define CONTROL_CORE_LDOSRAM_IVA_VOLTAGE_CTRL (CONTROL_CORE_U_BASE+0x320) +#define CONTROL_CORE_LDOSRAM_MPU_VOLTAGE_CTRL (CONTROL_CORE_U_BASE+0x324) +#define CONTROL_CORE_LDOSRAM_CORE_VOLTAGE_CTRL (CONTROL_CORE_U_BASE+0x328) + +#define CONTROL_CORE_LDOSRAM_VOLTAGE_CTRL_VAL (0x0401040F) + +#define CONTROL_PBIAS_LITE (0x4a100600) +#define PBIASVMODE3V (BIT21) +#define PBIASLITEPWRDNZ (BIT22) +#define PBIASVMODEERR (BIT23) +#define PBIASHIZ (BIT25) +#define PBIASPWRDNZ (BIT26) + +// PRM + +#define PRM_U_BASE (0x4A307B00) + +#define PRM_RSTCTRL (PRM_U_BASE+0x0) +#define PRM_RSTST (PRM_U_BASE+0x4) + +#define PRM_RSTST_GLOBAL_COLD_RST_MASK (0x1) + +#define PRM_RSTCTRL_RST_GLOBAL_COLD_SW_VAL (0x2) + +#define PRM_VC_VAL_BYPASS (PRM_U_BASE+0xA0) +#define PRM_VC_VAL_BYPASS_REGADDR_POS (8) +#define PRM_VC_VAL_BYPASS_DATA_POS (16) + +#define PRM_VC_CFG_I2C_MODE (PRM_U_BASE+0xA8) +#define PRM_VC_CFG_I2C_CLK (PRM_U_BASE+0xAC) + +#define VC_CFG_I2C_MODE_VAL (0x0) +#define VC_CFG_I2C_CLK_VAL (0x167FFB) + +#define PMIC_SMPS_ID0_SLAVE_ADDR (0x12) +#define PMIC_VCORE3_CFG_FORCE_REGADDR (0x61) +#define PMIC_VCORE1_CFG_FORCE_REGADDR (0x55) +#define PMIC_VCORE2_CFG_FORCE_REGADDR (0x5B) +#define PMIC_VCORE3_CFG_FORCE_VSEL (0x28) +#define PMIC_VCORE1_CFG_FORCE_VSEL_VDD_MPU_4430 (0x32) +#define PMIC_VCORE1_CFG_FORCE_VSEL_VDD_CORE_4460 (0x28) +#define PMIC_VCORE2_CFG_FORCE_VSEL (0x28) + +#define TPS62361_SLAVE_ADDR (0x60) +#define TPS62361_SET1_REG_ADDR (0x01) +#define TPS62361_SET1_REG_VAL (0x46) + +// CKGEN_CM1 + +#define CKGEN_CM1_U_BASE (0x4A004100) + +#define CKGEN_CM1_CM_DIV_M3_DPLL_CORE (CKGEN_CM1_U_BASE+0x34) +#define CKGEN_CM1_CM_DIV_M4_DPLL_CORE (CKGEN_CM1_U_BASE+0x38) +#define CKGEN_CM1_CM_DIV_M5_DPLL_CORE (CKGEN_CM1_U_BASE+0x3C) +#define CKGEN_CM1_CM_DIV_M6_DPLL_CORE (CKGEN_CM1_U_BASE+0x40) +#define CKGEN_CM1_CM_DIV_M7_DPLL_CORE (CKGEN_CM1_U_BASE+0x44) + +#define CKGEN_CM1_CM_DIV_M2_DPLL_MPU (CKGEN_CM1_U_BASE+0x70) + +#define CKGEN_CM1_CM_CLKMODE_DPLL_IVA (CKGEN_CM1_U_BASE+0xA0) +#define CKGEN_CM1_CM_CLKSEL_DPLL_IVA (CKGEN_CM1_U_BASE+0xAC) +#define CKGEN_CM1_CM_DIV_M4_DPLL_IVA (CKGEN_CM1_U_BASE+0xB8) +#define CKGEN_CM1_CM_DIV_M5_DPLL_IVA (CKGEN_CM1_U_BASE+0xBC) +#define CKGEN_CM1_CM_BYPCLK_DPLL_IVA (CKGEN_CM1_U_BASE+0xDC) + +#define CKGEN_CM1_CM_CLKSEL_DPLL_IVA_CLKSEL_VAL (0x19c10) +#define CKGEN_CM1_CM_CLKSEL_DPLL_IVA_M4_VAL (4) +#define CKGEN_CM1_CM_CLKSEL_DPLL_IVA_M5_VAL (7) +#define CKGEN_CM1_CM_CLKSEL_DPLL_IVA_BYCLK_VAL (1) +#define CKGEN_CM1_CM_CLKSEL_DPLL_IVA_CLKMODE_VAL (7) + +#define CKGEN_CM1_CM_CLKMODE_DPLL_ABE (CKGEN_CM1_U_BASE+0xE0) +#define CKGEN_CM1_CM_CLKSEL_DPLL_ABE (CKGEN_CM1_U_BASE+0xEC) +#define CKGEN_CM1_CM_DIV_M2_DPLL_ABE (CKGEN_CM1_U_BASE+0xF0) +#define CKGEN_CM1_CM_DIV_M3_DPLL_ABE (CKGEN_CM1_U_BASE+0xF4) + +#define CKGEN_CM1_CM_CLKSEL_DPLL_ABE_VAL (0x82ee00) +#define CKGEN_CM1_CM_DIV_M2_DPLL_ABE_VAL (1) +#define CKGEN_CM1_CM_DIV_M3_DPLL_ABE_VAL (1) +#define CKGEN_CM1_CM_CLKMODE_DPLL_ABE_VAL (0xf27) + +#define CKGEN_CM1_CM_SHADOW_FREQ_CONFIG1 (CKGEN_CM1_U_BASE+0x160) +#define CM_SHADOW_FREQ_CONFIG1_DPLL_CORE_M2_DIV_OPP100 (1<<11) +#define CM_SHADOW_FREQ_CONFIG1_DPLL_CORE_DPLL_EN_LOCK (7<<8) +#define CM_SHADOW_FREQ_CONFIG1_DLL_RESET_RST (1<<3) +#define CM_SHADOW_FREQ_CONFIG1_FREQ_UPDATE_START (1<<0) + +#define CM_DIV_M2_DPLL_MPU_OPP100_VAL (1) +#define CM_DIV_M3_DPLL_CORE_OPP100_VAL (5) +#define CM_DIV_M4_DPLL_CORE_OPP100_VAL (8) +#define CM_DIV_M5_DPLL_CORE_OPP100_VAL (4) +#define CM_DIV_M6_DPLL_CORE_OPP100_VAL (6) +#define CM_DIV_M7_DPLL_CORE_OPP100_VAL (5) + +// CKGEN_CM2 + +#define CKGEN_CM2_U_BASE (0x4A008100) + +#define CKGEN_CM2_CM_CLKMODE_DPLL_USB (CKGEN_CM2_U_BASE+0x80) +#define CKGEN_CM2_CM_CLKSEL_DPLL_USB (CKGEN_CM2_U_BASE+0x8C) +#define CKGEN_CM2_CM_DIV_M2_DPLL_USB (CKGEN_CM2_U_BASE+0x90) + +#define CKGEN_CM2_CM_CLKSEL_DPLL_USB_VAL (0x25817) +#define CKGEN_CM2_CM_DIV_M2_DPLL_USB_VAL (0x282) +#define CKGEN_CM2_CM_CLKMODE_DPLL_USB_VAL (0x7) + +// RESTORE_CM1 + +#define RESTORE_CM1_U_BASE (0x4A004E00) + +#define RESTORE_CM1_CM_DIV_M2_DPLL_CORE_RESTORE (RESTORE_CM1_U_BASE+0x4) +#define RESTORE_CM1_CM_DIV_M3_DPLL_CORE_RESTORE (RESTORE_CM1_U_BASE+0x8) +#define RESTORE_CM1_CM_DIV_M5_DPLL_CORE_RESTORE (RESTORE_CM1_U_BASE+0x10) +#define RESTORE_CM1_CM_DIV_M6_DPLL_CORE_RESTORE (RESTORE_CM1_U_BASE+0x14) +#define RESTORE_CM1_CM_DIV_M7_DPLL_CORE_RESTORE (RESTORE_CM1_U_BASE+0x18) +#define RESTORE_CM1_CM_CLKSEL_DPLL_CORE_RESTORE (RESTORE_CM1_U_BASE+0x1C) +#define RESTORE_CM1_CM_SHADOW_FREQ_CONFIG1_RESTORE (RESTORE_CM1_U_BASE+0x30) + +// SCRM + +#define SCRM_U_BASE (0x4A30A000) + +#define SCRM_AUXCLK3 (SCRM_U_BASE+0x31C) +#define SCRM_AUXCLK3_VAL (0x00010100) + +#endif // __OMAP4430PRCM_H__ + diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Rom.h b/Omap44xxPkg/Include/Omap4430/Omap4430Rom.h new file mode 100644 index 000000000..d2d2ef3d6 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Rom.h @@ -0,0 +1,53 @@ +/** @file + + Copyright (c) 2012 - 2013, Texas Instruments Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430ROM_H__ +#define __OMAP4430ROM_H__ + +#define PUBLIC_API_BASE (0x28400) + +#define PUBLIC_API_IRQ_REGISTER (0x44) +#define PUBLIC_API_IRQ_UNREGISTER (0x48) +#define PUBLIC_API_CM_ENABLEMODULECLOCKS (0xA0) +#define PUBLIC_API_WDTIMER_DISABLE (0x54) +#define PUBLIC_API_CTRL_CONFIGUREPADS (0xA8) + +//PUBLIC_API_IRQ_REGISTER +typedef UINT32 (** const IRQ_Register_pt)( UINT32, + UINT32, + UINT32 ); +#define RomIrqRegister(a, b, c) \ + (*(IRQ_Register_pt) ((PUBLIC_API_BASE+PUBLIC_API_IRQ_REGISTER)&0xFFFFFFFE))(a, b, c); + +//PUBLIC_API_IRQ_UNREGISTER +typedef UINT32 (** const IRQ_UnRegister_pt)( UINT32 ); +#define RomIrqUnRegister(a) \ + (*(IRQ_UnRegister_pt) (PUBLIC_API_BASE+PUBLIC_API_IRQ_UNREGISTER))(a); + +// PUBLIC_API_WDTIMER_DISABLE +typedef void (** const HAL_WDTIMER_Disable_pt)( void ); +#define RomWdtimerDisable() \ + (*(HAL_WDTIMER_Disable_pt) ((PUBLIC_API_BASE+PUBLIC_API_WDTIMER_DISABLE)&0xFFFFFFFE))(); + +//PUBLIC_API_CM_ENABLEMODULECLOCKS +typedef UINT32 (** const HAL_CM_EnableModuleClocks_pt)( UINT32, UINT32 ); +#define RomEnableClocks(a, b) \ + (*(HAL_CM_EnableModuleClocks_pt) ((PUBLIC_API_BASE+PUBLIC_API_CM_ENABLEMODULECLOCKS)&0xFFFFFFFE))(a, b); + +//PUBLIC_API_CTRL_CONFIGUREPADS +typedef UINT32 (** const HAL_CTRL_ConfigurePads_pt)( UINT32, UINT32 ); +#define RomCtrlConfigurePads(a, b) \ + (*(HAL_CTRL_ConfigurePads_pt) ((PUBLIC_API_BASE+PUBLIC_API_CTRL_CONFIGUREPADS)&0xFFFFFFFE))(a, b); + +#endif // __OMAP4430ROM_H__ diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Timer.h b/Omap44xxPkg/Include/Omap4430/Omap4430Timer.h new file mode 100644 index 000000000..15608e356 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Timer.h @@ -0,0 +1,88 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4TIMER_H__ +#define __OMAP4TIMER_H__ + +/* Watchdog */ +#define WDTIMER2_BASE (0x4A314000) +#define WWPS (0x034) +#define WSPR (0x048) + +/* DMTIMERS*/ + +#define GPTIMER1_BASE (0x48313000) +#define GPTIMER2_BASE (0x48032000) +#define GPTIMER3_BASE (0x48034000) +#define GPTIMER4_BASE (0x48036000) +#define GPTIMER5_BASE (0x49038000) +#define GPTIMER6_BASE (0x4903A000) +#define GPTIMER7_BASE (0x4903C000) +#define GPTIMER8_BASE (0x4903E000) +#define GPTIMER9_BASE (0x4803E000) +#define GPTIMER10_BASE (0x48086000) +#define GPTIMER11_BASE (0x48088000) +#define GPTIMER12_BASE (0x48304000) + +// TODO: review below timer IP register offsets changing from OMAP3 to OMAP4 + +#define GPTIMER_TIOCP_CFG (/*0x0010*/) +#define GPTIMER_TISTAT (/*0x0014*/) +#define GPTIMER_TISR (/*0x0018 => IRQSTATUS*/0x28) +#define GPTIMER_TIER (/*0x001C => IRQSTATUS_SET*/0x2C) +#define GPTIMER_TWER (/*0x0020*/) +#define GPTIMER_TCLR (/*0x0024*/0x38) +#define GPTIMER_TCRR (/*0x0028*/0x3C) +#define GPTIMER_TLDR (/*0x002C*/0x40) +#define GPTIMER_TTGR (/*0x0030*/0x44) +#define GPTIMER_TWPS (/*0x0034*/0x48) +#define GPTIMER_TMAR (/*0x0038*/0x4C) +#define GPTIMER_TCAR1 (/*0x003C*/0x50) +#define GPTIMER_TSICR (/*0x0040*/0x54) +#define GPTIMER_TCAR2 (/*0x0044*/0x58) +#define GPTIMER_TPIR (/*0x0048*/) +#define GPTIMER_TNIR (/*0x004C*/) +#define GPTIMER_TCVR (/*0x0050*/) +#define GPTIMER_TOCR (/*0x0054*/) +#define GPTIMER_TOWR (/*0x0058*/) + +#define TISR_TCAR_IT_FLAG_MASK BIT2 +#define TISR_OVF_IT_FLAG_MASK BIT1 +#define TISR_MAT_IT_FLAG_MASK BIT0 +#define TISR_ALL_INTERRUPT_MASK (TISR_TCAR_IT_FLAG_MASK | TISR_OVF_IT_FLAG_MASK | TISR_MAT_IT_FLAG_MASK) + +#define TISR_TCAR_IT_FLAG_NOT_PENDING (0UL << 2) +#define TISR_OVF_IT_FLAG_NOT_PENDING (0UL << 1) +#define TISR_MAT_IT_FLAG_NOT_PENDING (0UL << 0) +#define TISR_NO_INTERRUPTS_PENDING (TISR_TCAR_IT_FLAG_NOT_PENDING | TISR_OVF_IT_FLAG_NOT_PENDING | TISR_MAT_IT_FLAG_NOT_PENDING) + +#define TISR_TCAR_IT_FLAG_CLEAR BIT2 +#define TISR_OVF_IT_FLAG_CLEAR BIT1 +#define TISR_MAT_IT_FLAG_CLEAR BIT0 +#define TISR_CLEAR_ALL (TISR_TCAR_IT_FLAG_CLEAR | TISR_OVF_IT_FLAG_CLEAR | TISR_MAT_IT_FLAG_CLEAR) + +#define TCLR_AR_AUTORELOAD BIT1 +#define TCLR_AR_ONESHOT (0UL << 1) +#define TCLR_ST_ON BIT0 +#define TCLR_ST_OFF (0UL << 0) + +#define TIER_TCAR_IT_ENABLE (BIT2 +#define TIER_TCAR_IT_DISABLE (0UL << 2) +#define TIER_OVF_IT_ENABLE BIT1 +#define TIER_OVF_IT_DISABLE (0UL << 1) +#define TIER_MAT_IT_ENABLE BIT0 +#define TIER_MAT_IT_DISABLE (0UL << 0) + +#endif // __OMAP4TIMER_H__ + diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Uart.h b/Omap44xxPkg/Include/Omap4430/Omap4430Uart.h new file mode 100644 index 000000000..27ba44563 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Uart.h @@ -0,0 +1,54 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430UART_H__ +#define __OMAP4430UART_H__ + +#define UART1_BASE (0x4806A000) +#define UART2_BASE (0x4806C000) +#define UART3_BASE (0x48020000) + +#define UART_DLL_REG (0x0000) +#define UART_RBR_REG (0x0000) +#define UART_THR_REG (0x0000) +#define UART_DLH_REG (0x0004) +#define UART_FCR_REG (0x0008) +#define UART_LCR_REG (0x000C) +#define UART_MCR_REG (0x0010) +#define UART_LSR_REG (0x0014) +#define UART_MDR1_REG (0x0020) + +#define UART_FCR_TX_FIFO_CLEAR BIT2 +#define UART_FCR_RX_FIFO_CLEAR BIT1 +#define UART_FCR_FIFO_ENABLE BIT0 + +#define UART_LCR_DIV_EN_ENABLE BIT7 +#define UART_LCR_DIV_EN_DISABLE (0UL << 7) +#define UART_LCR_CHAR_LENGTH_8 (BIT1 | BIT0) + +#define UART_MCR_RTS_FORCE_ACTIVE BIT1 +#define UART_MCR_DTR_FORCE_ACTIVE BIT0 + +#define UART_LSR_TX_FIFO_E_MASK BIT5 +#define UART_LSR_TX_FIFO_E_NOT_EMPTY (0UL << 5) +#define UART_LSR_TX_FIFO_E_EMPTY BIT5 +#define UART_LSR_RX_FIFO_E_MASK BIT0 +#define UART_LSR_RX_FIFO_E_NOT_EMPTY BIT0 +#define UART_LSR_RX_FIFO_E_EMPTY (0UL << 0) + +// BIT2:BIT0 +#define UART_MDR1_MODE_SELECT_DISABLE (7UL) +#define UART_MDR1_MODE_SELECT_UART_16X (0UL) + +#endif // __OMAP4430UART_H__ diff --git a/Omap44xxPkg/Include/Omap4430/Omap4430Usb.h b/Omap44xxPkg/Include/Omap4430/Omap4430Usb.h new file mode 100644 index 000000000..22fe47c83 --- /dev/null +++ b/Omap44xxPkg/Include/Omap4430/Omap4430Usb.h @@ -0,0 +1,41 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4430USB_H__ +#define __OMAP4430USB_H__ + +#define USB_BASE (0x4A060000) + +#define UHH_SYSCONFIG (USB_BASE + 0x4010) +#define UHH_HOSTCONFIG (USB_BASE + 0x4040) +#define UHH_SYSSTATUS (USB_BASE + 0x4014) + +#define USB_EHCI_HCCAPBASE (USB_BASE + 0x4C00) + +#define UHH_SYSCONFIG_STANDBYMODE_NO_STANDBY BIT4 +#define UHH_SYSCONFIG_IDLEMODE_NO_IDLE BIT2 +#define UHH_SYSCONFIG_SOFTRESET BIT0 + +#define UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT (0UL << 9) +#define UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT (0UL << 8) +#define UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE (0UL << 5) +#define UHH_HOSTCONFIG_ENA_INCR16_ENABLE BIT4 +#define UHH_HOSTCONFIG_ENA_INCR8_ENABLE BIT3 +#define UHH_HOSTCONFIG_ENA_INCR4_ENABLE BIT2 +#define UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON (0UL << 1) +#define UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE (0UL << 16) + +#define UHH_SYSSTATUS_RESETDONE (BIT1 | BIT2) + +#endif // __OMAP4430USB_H__ diff --git a/Omap44xxPkg/Include/TWL6030.h b/Omap44xxPkg/Include/TWL6030.h new file mode 100644 index 000000000..8126ca7c2 --- /dev/null +++ b/Omap44xxPkg/Include/TWL6030.h @@ -0,0 +1,78 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __TWL6030_H__ +#define __TWL6030_H__ + +#define EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(x) (((x) >> 8) & 0xFF) +#define EXTERNAL_DEVICE_REGISTER_TO_REGISTER(x) ((x) & 0xFF) +#define EXTERNAL_DEVICE_REGISTER(SlaveAddress, Register) (((SlaveAddress) & 0xFF) << 8 | ((Register) & 0xFF)) + +// I2C Address group +#define I2C_ADDR_GRP_ID1 0x48 +#define I2C_ADDR_GRP_ID2 0x49 +#define I2C_ADDR_GRP_ID3 0x4A +#define I2C_ADDR_GRP_ID4 0x4B +#define I2C_ADDR_GRP_ID5 0x12 + +// MMC definitions. +#define VMMC_CFG_GRP 0x98 +#define DEV_GRP_APP BIT0 + +#define VMMC_CFG_STATE 0x9A +#define VMMC_CFG_STATE_OFF 0xE0 +#define VMMC_CFG_STATE_ON 0xE1 + +#define VMMC_CFG_VOLTAGE 0x9B +#define VSEL_3_00V 0x15 + +#define MMCCTRL 0xEE +#define CARD_DET_STS_MMC BIT0 +#define CARD_DET_CFG BIT3 + +// LEDEN register +#define LEDEN 0xEE +#define LEDAON BIT0 +#define LEDBON BIT1 +#define LEDAPWM BIT4 +#define LEDBPWM BIT5 + +// RTC registers +#define SECONDS_REG 0x1C +#define MINUTES_REG 0x1D +#define HOURS_REG 0x1E +#define DAYS_REG 0x1F +#define MONTHS_REG 0x20 +#define YEARS_REG 0x21 +#define WEEKS_REG 0x22 +#define RTC_CTRL_REG 0x29 + +// USB PHY power +#define VAUX2_DEDICATED 0x79 +#define VAUX2_DEV_GRP 0x76 + +#define VAUX_DEV_GRP_NONE 0x00 +#define VAUX_DEV_GRP_P1 0x20 +#define VAUX_DEV_GRP_P2 0x40 +#define VAUX_DEV_GRP_P3 0x80 +#define VAUX_DEDICATED_18V 0x05 + +// Display subsystem +#define VPLL2_DEDICATED 0x91 +#define VPLL2_DEV_GRP 0x8E + +#define GPIODATADIR1 0x9B +#define SETGPIODATAOUT1 0xA4 + +#endif //__TWL6030_H__ diff --git a/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c b/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c new file mode 100644 index 000000000..38c84dd88 --- /dev/null +++ b/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputBlt.c @@ -0,0 +1,445 @@ +/** @file + + Copyright (c) 2011, ARM Ltd. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + **/ + +#include <PiDxe.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DevicePathLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiRuntimeServicesTableLib.h> +#include <Library/MemoryAllocationLib.h> + +#include <Guid/GlobalVariable.h> + +#include "LcdGraphicsOutputDxe.h" + +extern BOOLEAN mDisplayInitialized; + +// +// Function Definitions +// + +STATIC +EFI_STATUS +VideoCopyNoHorizontalOverlap ( + IN UINTN BitsPerPixel, + IN volatile VOID *FrameBufferBase, + IN UINT32 HorizontalResolution, + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINTN SourceLine; + UINTN DestinationLine; + UINTN WidthInBytes; + UINTN LineCount; + INTN Step; + VOID *SourceAddr; + VOID *DestinationAddr; + + if( DestinationY <= SourceY ) { + // scrolling up (or horizontally but without overlap) + SourceLine = SourceY; + DestinationLine = DestinationY; + Step = 1; + } else { + // scrolling down + SourceLine = SourceY + Height; + DestinationLine = DestinationY + Height; + Step = -1; + } + + WidthInBytes = Width * 2; + + for( LineCount = 0; LineCount < Height; LineCount++ ) { + // Update the start addresses of source & destination using 16bit pointer arithmetic + SourceAddr = (VOID *)((UINT16 *)FrameBufferBase + SourceLine * HorizontalResolution + SourceX ); + DestinationAddr = (VOID *)((UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationX); + + // Copy the entire line Y from video ram to the temp buffer + CopyMem( DestinationAddr, SourceAddr, WidthInBytes); + + // Update the line numbers + SourceLine += Step; + DestinationLine += Step; + } + + return Status; +} + +STATIC +EFI_STATUS +VideoCopyHorizontalOverlap ( + IN UINTN BitsPerPixel, + IN volatile VOID *FrameBufferBase, + UINT32 HorizontalResolution, + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + UINT16 *PixelBuffer16bit; + UINT16 *SourcePixel16bit; + UINT16 *DestinationPixel16bit; + + UINT32 SourcePixelY; + UINT32 DestinationPixelY; + UINTN SizeIn16Bits; + + // Allocate a temporary buffer + PixelBuffer16bit = (UINT16 *) AllocatePool((Height * Width) * sizeof(UINT16)); + + if (PixelBuffer16bit == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto EXIT; + } + + // Access each pixel inside the source area of the Video Memory and copy it to the temp buffer + + SizeIn16Bits = Width * 2; + + for (SourcePixelY = SourceY, DestinationPixel16bit = PixelBuffer16bit; + SourcePixelY < SourceY + Height; + SourcePixelY++, DestinationPixel16bit += Width) + { + // Calculate the source address: + SourcePixel16bit = (UINT16 *)FrameBufferBase + SourcePixelY * HorizontalResolution + SourceX; + + // Copy the entire line Y from Video to the temp buffer + CopyMem( (VOID *)DestinationPixel16bit, (CONST VOID *)SourcePixel16bit, SizeIn16Bits); + } + + // Copy from the temp buffer into the destination area of the Video Memory + + for (DestinationPixelY = DestinationY, SourcePixel16bit = PixelBuffer16bit; + DestinationPixelY < DestinationY + Height; + DestinationPixelY++, SourcePixel16bit += Width) + { + // Calculate the target address: + DestinationPixel16bit = (UINT16 *)FrameBufferBase + (DestinationPixelY * HorizontalResolution + DestinationX); + + // Copy the entire line Y from the temp buffer to Video + CopyMem( (VOID *)DestinationPixel16bit, (CONST VOID *)SourcePixel16bit, SizeIn16Bits); + } + + // Free the allocated memory + FreePool((VOID *) PixelBuffer16bit); + + +EXIT: + return Status; +} + +STATIC +EFI_STATUS +BltVideoFill ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *EfiSourcePixel, OPTIONAL + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer + ) +{ + EFI_PIXEL_BITMASK* PixelInformation; + EFI_STATUS Status; + UINT32 HorizontalResolution; + VOID *FrameBufferBase; + UINT16 *DestinationPixel16bit; + UINT16 Pixel16bit; + UINT32 DestinationPixelX; + UINT32 DestinationLine; + + Status = EFI_SUCCESS; + PixelInformation = &This->Mode->Info->PixelInformation; + FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase)); + HorizontalResolution = This->Mode->Info->HorizontalResolution; + + // Convert the EFI pixel at the start of the BltBuffer(0,0) into a video display pixel + Pixel16bit = (UINT16) ( + ( (EfiSourcePixel->Red << 8) & PixelInformation->RedMask ) + | ( (EfiSourcePixel->Green << 3) & PixelInformation->GreenMask ) + | ( (EfiSourcePixel->Blue >> 3) & PixelInformation->BlueMask ) + ); + + // Copy the SourcePixel into every pixel inside the target rectangle + for (DestinationLine = DestinationY; + DestinationLine < DestinationY + Height; + DestinationLine++) + { + for (DestinationPixelX = DestinationX; + DestinationPixelX < DestinationX + Width; + DestinationPixelX++) + { + // Calculate the target address: + DestinationPixel16bit = (UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationPixelX; + + // Copy the pixel into the new target + *DestinationPixel16bit = Pixel16bit; + } + } + + + return Status; +} + +STATIC +EFI_STATUS +BltVideoToBltBuffer ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer + ) +{ + EFI_STATUS Status; + UINT32 HorizontalResolution; + EFI_PIXEL_BITMASK *PixelInformation; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL *EfiDestinationPixel; + VOID *FrameBufferBase; + UINT16 *SourcePixel16bit; + UINT16 Pixel16bit; + UINT32 SourcePixelX; + UINT32 SourceLine; + UINT32 DestinationPixelX; + UINT32 DestinationLine; + UINT32 BltBufferHorizontalResolution; + + Status = EFI_SUCCESS; + PixelInformation = &This->Mode->Info->PixelInformation; + HorizontalResolution = This->Mode->Info->HorizontalResolution; + FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase)); + + if(( Delta != 0 ) && ( Delta != Width * sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) { + // Delta is not zero and it is different from the width. + // Divide it by the size of a pixel to find out the buffer's horizontal resolution. + BltBufferHorizontalResolution = (UINT32) (Delta / sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL)); + } else { + BltBufferHorizontalResolution = Width; + } + + // Access each pixel inside the Video Memory + for (SourceLine = SourceY, DestinationLine = DestinationY; + SourceLine < SourceY + Height; + SourceLine++, DestinationLine++) + { + for (SourcePixelX = SourceX, DestinationPixelX = DestinationX; + SourcePixelX < SourceX + Width; + SourcePixelX++, DestinationPixelX++) + { + // Calculate the source and target addresses: + SourcePixel16bit = (UINT16 *)FrameBufferBase + SourceLine * HorizontalResolution + SourcePixelX; + EfiDestinationPixel = BltBuffer + DestinationLine * BltBufferHorizontalResolution + DestinationPixelX; + + // Snapshot the pixel from the video buffer once, to speed up the operation. + // If we were dereferencing the pointer, as it is volatile, we would perform 3 memory read operations. + Pixel16bit = *SourcePixel16bit; + + // Copy the pixel into the new target + EfiDestinationPixel->Red = (UINT8) ( (Pixel16bit & PixelInformation->RedMask ) >> 8 ); + EfiDestinationPixel->Green = (UINT8) ( (Pixel16bit & PixelInformation->GreenMask ) >> 3 ); + EfiDestinationPixel->Blue = (UINT8) ( (Pixel16bit & PixelInformation->BlueMask ) << 3 ); + } + } + + return Status; +} + +STATIC +EFI_STATUS +BltBufferToVideo ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer + ) +{ + EFI_STATUS Status; + UINT32 HorizontalResolution; + EFI_PIXEL_BITMASK *PixelInformation; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL *EfiSourcePixel; + VOID *FrameBufferBase; + UINT16 *DestinationPixel16bit; + UINT32 SourcePixelX; + UINT32 SourceLine; + UINT32 DestinationPixelX; + UINT32 DestinationLine; + UINT32 BltBufferHorizontalResolution; + + Status = EFI_SUCCESS; + PixelInformation = &This->Mode->Info->PixelInformation; + HorizontalResolution = This->Mode->Info->HorizontalResolution; + FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase)); + + if(( Delta != 0 ) && ( Delta != Width * sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL))) { + // Delta is not zero and it is different from the width. + // Divide it by the size of a pixel to find out the buffer's horizontal resolution. + BltBufferHorizontalResolution = (UINT32) (Delta / sizeof(EFI_GRAPHICS_OUTPUT_BLT_PIXEL)); + } else { + BltBufferHorizontalResolution = Width; + } + + // Access each pixel inside the BltBuffer Memory + for (SourceLine = SourceY, DestinationLine = DestinationY; + SourceLine < SourceY + Height; + SourceLine++, DestinationLine++) { + + for (SourcePixelX = SourceX, DestinationPixelX = DestinationX; + SourcePixelX < SourceX + Width; + SourcePixelX++, DestinationPixelX++) + { + // Calculate the source and target addresses: + EfiSourcePixel = BltBuffer + SourceLine * BltBufferHorizontalResolution + SourcePixelX; + DestinationPixel16bit = (UINT16 *)FrameBufferBase + DestinationLine * HorizontalResolution + DestinationPixelX; + + // Copy the pixel into the new target + // Only the most significant bits will be copied across: + // To convert from 8 bits to 5 bits per pixel we throw away the 3 least significant bits + *DestinationPixel16bit = (UINT16) ( + ( (EfiSourcePixel->Red << 8) & PixelInformation->RedMask ) + | ( (EfiSourcePixel->Green << 3) & PixelInformation->GreenMask ) + | ( (EfiSourcePixel->Blue >> 3) & PixelInformation->BlueMask ) + ); + } + } + + return Status; +} + +STATIC +EFI_STATUS +BltVideoToVideo ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer + ) +{ + EFI_STATUS Status; + UINT32 HorizontalResolution; + UINTN BitsPerPixel; + VOID *FrameBufferBase; + + BitsPerPixel = 16; + + HorizontalResolution = This->Mode->Info->HorizontalResolution; + FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase)); + + // + // BltVideo to BltVideo: + // + // Source is the Video Memory, + // Destination is the Video Memory + + FrameBufferBase = (UINTN *)((UINTN)(This->Mode->FrameBufferBase)); + + // The UEFI spec currently states: + // "There is no limitation on the overlapping of the source and destination rectangles" + // Therefore, we must be careful to avoid overwriting the source data + if( SourceY == DestinationY ) { + // Copying within the same height, e.g. horizontal shift + if( SourceX == DestinationX ) { + // Nothing to do + Status = EFI_SUCCESS; + } else if( ((SourceX>DestinationX)?(SourceX - DestinationX):(DestinationX - SourceX)) < Width ) { + // There is overlap + Status = VideoCopyHorizontalOverlap (BitsPerPixel, FrameBufferBase, HorizontalResolution, SourceX, SourceY, DestinationX, DestinationY, Width, Height ); + } else { + // No overlap + Status = VideoCopyNoHorizontalOverlap (BitsPerPixel, FrameBufferBase, HorizontalResolution, SourceX, SourceY, DestinationX, DestinationY, Width, Height ); + } + } else { + // Copying from different heights + Status = VideoCopyNoHorizontalOverlap (BitsPerPixel, FrameBufferBase, HorizontalResolution, SourceX, SourceY, DestinationX, DestinationY, Width, Height ); + } + + return Status; +} + +EFI_STATUS +EFIAPI +LcdGraphicsBlt ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL + IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation, + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer + ) +{ + EFI_STATUS Status; + LCD_INSTANCE *Instance; + + Instance = LCD_INSTANCE_FROM_GOP_THIS(This); + + if (!mDisplayInitialized) { + InitializeDisplay (Instance); + } + + switch (BltOperation) { + case EfiBltVideoFill: + Status = BltVideoFill (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta); + break; + + case EfiBltVideoToBltBuffer: + Status = BltVideoToBltBuffer (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta); + break; + + case EfiBltBufferToVideo: + Status = BltBufferToVideo (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta); + break; + + case EfiBltVideoToVideo: + Status = BltVideoToVideo (This, BltBuffer, SourceX, SourceY, DestinationX, DestinationY, Width, Height, Delta); + break; + + case EfiGraphicsOutputBltOperationMax: + default: + DEBUG((DEBUG_ERROR, "LcdGraphicsBlt: Invalid Operation\n")); + Status = EFI_INVALID_PARAMETER; + break; + } + + return Status; +} diff --git a/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c b/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c new file mode 100644 index 000000000..ea6760d06 --- /dev/null +++ b/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.c @@ -0,0 +1,407 @@ +/** @file + + Copyright (c) 2011, ARM Ltd. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "LcdGraphicsOutputDxe.h" + +BOOLEAN mDisplayInitialized = FALSE; + +LCD_MODE LcdModes[] = { + { + 0, 640, 480, + 9, 4, + 96, 16, 48, + 2, 10, 33 + }, + { + 1, 800, 600, + 11, 2, + 120, 56, 64, + 5, 37, 22 + }, + { + 2, 1024, 768, + 6, 2, + 96, 16, 48, + 2, 10, 33 + }, +}; + +LCD_INSTANCE mLcdTemplate = { + LCD_INSTANCE_SIGNATURE, + NULL, // Handle + { // ModeInfo + 0, // Version + 0, // HorizontalResolution + 0, // VerticalResolution + PixelBltOnly, // PixelFormat + { + 0xF800, //RedMask; + 0x7E0, //GreenMask; + 0x1F, //BlueMask; + 0x0//ReservedMask + }, // PixelInformation + 0, // PixelsPerScanLine + }, + { // Mode + 3, // MaxMode; + 0, // Mode; + NULL, // Info; + 0, // SizeOfInfo; + 0, // FrameBufferBase; + 0 // FrameBufferSize; + }, + { // Gop + LcdGraphicsQueryMode, // QueryMode + LcdGraphicsSetMode, // SetMode + LcdGraphicsBlt, // Blt + NULL // *Mode + }, + { // DevicePath + { + { + HARDWARE_DEVICE_PATH, HW_VENDOR_DP, + { + (UINT8) (sizeof(VENDOR_DEVICE_PATH)), + (UINT8) ((sizeof(VENDOR_DEVICE_PATH)) >> 8) + } + }, + // Hardware Device Path for Lcd + EFI_CALLER_ID_GUID // Use the driver's GUID + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { sizeof(EFI_DEVICE_PATH_PROTOCOL), 0 } + } + } +}; + +EFI_STATUS +LcdInstanceContructor ( + OUT LCD_INSTANCE** NewInstance + ) +{ + LCD_INSTANCE* Instance; + + Instance = AllocateCopyPool (sizeof(LCD_INSTANCE), &mLcdTemplate); + if (Instance == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Instance->Gop.Mode = &Instance->Mode; + Instance->Mode.Info = &Instance->ModeInfo; + + *NewInstance = Instance; + return EFI_SUCCESS; +} + +EFI_STATUS +LcdPlatformGetVram ( + OUT EFI_PHYSICAL_ADDRESS* VramBaseAddress, + OUT UINTN* VramSize + ) +{ + EFI_STATUS Status; + EFI_CPU_ARCH_PROTOCOL *Cpu; + UINTN MaxSize; + + MaxSize = 0x500000; + *VramSize = MaxSize; + + // Allocate VRAM from DRAM + Status = gBS->AllocatePages (AllocateAnyPages, EfiBootServicesData, EFI_SIZE_TO_PAGES((MaxSize)), VramBaseAddress); + if (EFI_ERROR(Status)) { + return Status; + } + + // Ensure the Cpu architectural protocol is already installed + Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu); + ASSERT_EFI_ERROR(Status); + + // Mark the VRAM as un-cacheable. The VRAM is inside the DRAM, which is cacheable. + Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC); + if (EFI_ERROR(Status)) { + gBS->FreePool (VramBaseAddress); + return Status; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +DssSetMode ( + UINT32 VramBaseAddress, + UINTN ModeNumber + ) +{ + // Make sure the interface clock is running + MmioWrite32 (CM_ICLKEN_DSS, EN_DSS); + + // Stop the functional clocks + MmioAnd32 (CM_FCLKEN_DSS, ~(EN_DSS1 | EN_DSS2 | EN_TV)); + + // Program the DSS clock divisor + MmioWrite32 (CM_CLKSEL_DSS, 0x1000 | (LcdModes[ModeNumber].DssDivisor)); + + // Start the functional clocks + MmioOr32 (CM_FCLKEN_DSS, (EN_DSS1 | EN_DSS2 | EN_TV)); + + // Wait for DSS to stabilize + gBS->Stall(1); + + // Reset the subsystem + MmioWrite32(DSS_SYSCONFIG, DSS_SOFTRESET); + while (!(MmioRead32 (DSS_SYSSTATUS) & DSS_RESETDONE)); + + // Configure LCD parameters + MmioWrite32 (DISPC_SIZE_LCD, + ((LcdModes[ModeNumber].HorizontalResolution - 1) + | ((LcdModes[ModeNumber].VerticalResolution - 1) << 16)) + ); + MmioWrite32 (DISPC_TIMING_H, + ( (LcdModes[ModeNumber].HSync - 1) + | ((LcdModes[ModeNumber].HFrontPorch - 1) << 8) + | ((LcdModes[ModeNumber].HBackPorch - 1) << 20)) + ); + MmioWrite32 (DISPC_TIMING_V, + ( (LcdModes[ModeNumber].VSync - 1) + | ((LcdModes[ModeNumber].VFrontPorch - 1) << 8) + | ((LcdModes[ModeNumber].VBackPorch - 1) << 20)) + ); + + // Set the framebuffer to only load frames (no gamma tables) + MmioAnd32 (DISPC_CONFIG, CLEARLOADMODE); + MmioOr32 (DISPC_CONFIG, LOAD_FRAME_ONLY); + + // Divisor for the pixel clock + MmioWrite32(DISPC_DIVISOR, ((1 << 16) | LcdModes[ModeNumber].DispcDivisor) ); + + // Set up the graphics layer + MmioWrite32 (DISPC_GFX_PRELD, 0x2D8); + MmioWrite32 (DISPC_GFX_BA0, VramBaseAddress); + MmioWrite32 (DISPC_GFX_SIZE, + ((LcdModes[ModeNumber].HorizontalResolution - 1) + | ((LcdModes[ModeNumber].VerticalResolution - 1) << 16)) + ); + + MmioWrite32(DISPC_GFX_ATTR, (GFXENABLE | RGB16 | BURSTSIZE16)); + + // Start it all + MmioOr32 (DISPC_CONTROL, (LCDENABLE | ACTIVEMATRIX | DATALINES24 | BYPASS_MODE | LCDENABLESIGNAL)); + MmioOr32 (DISPC_CONTROL, GOLCD); + + return EFI_SUCCESS; +} + +EFI_STATUS +HwInitializeDisplay ( + UINTN VramBaseAddress, + UINTN VramSize + ) +{ + EFI_STATUS Status; + UINT8 Data; + EFI_TPL OldTpl; + EMBEDDED_EXTERNAL_DEVICE *gTPS65950; + + // Enable power lines used by TFP410 + Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950); + ASSERT_EFI_ERROR (Status); + + OldTpl = gBS->RaiseTPL(TPL_NOTIFY); + Data = VAUX_DEV_GRP_P1; + Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VPLL2_DEV_GRP), 1, &Data); + ASSERT_EFI_ERROR(Status); + + Data = VAUX_DEDICATED_18V; + Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VPLL2_DEDICATED), 1, &Data); + ASSERT_EFI_ERROR (Status); + + // Power up TFP410 (set GPIO2 on TPS - for PandaBoard-xM) + Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, GPIODATADIR1), 1, &Data); + ASSERT_EFI_ERROR (Status); + Data |= BIT2; + Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, GPIODATADIR1), 1, &Data); + ASSERT_EFI_ERROR (Status); + + Data = BIT2; + Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID2, SETGPIODATAOUT1), 1, &Data); + ASSERT_EFI_ERROR (Status); + + gBS->RestoreTPL(OldTpl); + + // Power up TFP410 (set GPIO 170 - for older PandaBoards) + MmioAnd32 (GPIO6_BASE + GPIO_OE, ~BIT10); + MmioOr32 (GPIO6_BASE + GPIO_SETDATAOUT, BIT10); + + return EFI_SUCCESS; +} + +EFI_STATUS +InitializeDisplay ( + IN LCD_INSTANCE* Instance + ) +{ + EFI_STATUS Status; + UINTN VramSize; + EFI_PHYSICAL_ADDRESS VramBaseAddress; + + Status = LcdPlatformGetVram (&VramBaseAddress, &VramSize); + if (EFI_ERROR (Status)) { + return Status; + } + + Instance->Mode.FrameBufferBase = VramBaseAddress; + Instance->Mode.FrameBufferSize = VramSize; + + Status = HwInitializeDisplay((UINTN)VramBaseAddress, VramSize); + if (!EFI_ERROR (Status)) { + mDisplayInitialized = TRUE; + } + + return Status; +} + +EFI_STATUS +EFIAPI +LcdGraphicsQueryMode ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN UINT32 ModeNumber, + OUT UINTN *SizeOfInfo, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info + ) +{ + LCD_INSTANCE *Instance; + + Instance = LCD_INSTANCE_FROM_GOP_THIS(This); + + if (!mDisplayInitialized) { + InitializeDisplay (Instance); + } + + // Error checking + if ( (This == NULL) || (Info == NULL) || (SizeOfInfo == NULL) || (ModeNumber >= This->Mode->MaxMode) ) { + DEBUG((DEBUG_ERROR, "LcdGraphicsQueryMode: ERROR - For mode number %d : Invalid Parameter.\n", ModeNumber )); + return EFI_INVALID_PARAMETER; + } + + *Info = AllocateCopyPool(sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION), &Instance->ModeInfo); + if (*Info == NULL) { + return EFI_OUT_OF_RESOURCES; + } + + *SizeOfInfo = sizeof (EFI_GRAPHICS_OUTPUT_MODE_INFORMATION); + + (*Info)->Version = 0; + (*Info)->HorizontalResolution = LcdModes[ModeNumber].HorizontalResolution; + (*Info)->VerticalResolution = LcdModes[ModeNumber].VerticalResolution; + (*Info)->PixelFormat = PixelBltOnly; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +LcdGraphicsSetMode ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN UINT32 ModeNumber + ) +{ + LCD_INSTANCE *Instance; + + Instance = LCD_INSTANCE_FROM_GOP_THIS(This); + + if (ModeNumber >= Instance->Mode.MaxMode) { + return EFI_UNSUPPORTED; + } + + if (!mDisplayInitialized) { + InitializeDisplay (Instance); + } + + DssSetMode((UINT32)Instance->Mode.FrameBufferBase, ModeNumber); + + Instance->Mode.Mode = ModeNumber; + Instance->ModeInfo.HorizontalResolution = LcdModes[ModeNumber].HorizontalResolution; + Instance->ModeInfo.VerticalResolution = LcdModes[ModeNumber].VerticalResolution; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +LcdGraphicsOutputDxeInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + LCD_INSTANCE* Instance; + + // TODO: this driver makes boot-up crashing on Panda + return EFI_SUCCESS; + + Status = LcdInstanceContructor (&Instance); + if (EFI_ERROR(Status)) { + goto EXIT; + } + + // Install the Graphics Output Protocol and the Device Path + Status = gBS->InstallMultipleProtocolInterfaces( + &Instance->Handle, + &gEfiGraphicsOutputProtocolGuid, &Instance->Gop, + &gEfiDevicePathProtocolGuid, &Instance->DevicePath, + NULL + ); + + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "GraphicsOutputDxeInitialize: Can not install the protocol. Exit Status=%r\n", Status)); + goto EXIT; + } + + // Register for an ExitBootServicesEvent + // When ExitBootServices starts, this function here will make sure that the graphics driver will shut down properly, + // i.e. it will free up all allocated memory and perform any necessary hardware re-configuration. + /*Status = gBS->CreateEvent ( + EVT_SIGNAL_EXIT_BOOT_SERVICES, + TPL_NOTIFY, + LcdGraphicsExitBootServicesEvent, NULL, + &Instance->ExitBootServicesEvent + ); + + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "GraphicsOutputDxeInitialize: Can not install the ExitBootServicesEvent handler. Exit Status=%r\n", Status)); + goto EXIT_ERROR_UNINSTALL_PROTOCOL; + }*/ + + // To get here, everything must be fine, so just exit + goto EXIT; + +//EXIT_ERROR_UNINSTALL_PROTOCOL: + /* The following function could return an error message, + * however, to get here something must have gone wrong already, + * so preserve the original error, i.e. don't change + * the Status variable, even it fails to uninstall the protocol. + */ +/* gBS->UninstallMultipleProtocolInterfaces ( + Instance->Handle, + &gEfiGraphicsOutputProtocolGuid, &Instance->Gop, // Uninstall Graphics Output protocol + &gEfiDevicePathProtocolGuid, &Instance->DevicePath, // Uninstall device path + NULL + );*/ + +EXIT: + return Status; + +} diff --git a/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h b/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h new file mode 100644 index 000000000..721859724 --- /dev/null +++ b/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.h @@ -0,0 +1,157 @@ +/** @file + + Copyright (c) 2011, ARM Ltd. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __OMAP4_DSS_GRAPHICS__ +#define __OMAP4_DSS_GRAPHICS__ + +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiLib.h> +#include <Library/DebugLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/IoLib.h> + +#include <Protocol/DevicePathToText.h> +#include <Protocol/EmbeddedExternalDevice.h> +#include <Protocol/Cpu.h> + +#include <Guid/GlobalVariable.h> + +#include <Omap4430/Omap4430.h> +#include <TWL6030.h> + +typedef struct { + VENDOR_DEVICE_PATH Guid; + EFI_DEVICE_PATH_PROTOCOL End; +} LCD_GRAPHICS_DEVICE_PATH; + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo; + EFI_GRAPHICS_OUTPUT_PROTOCOL_MODE Mode; + EFI_GRAPHICS_OUTPUT_PROTOCOL Gop; + LCD_GRAPHICS_DEVICE_PATH DevicePath; +// EFI_EVENT ExitBootServicesEvent; +} LCD_INSTANCE; + +#define LCD_INSTANCE_SIGNATURE SIGNATURE_32('l', 'c', 'd', '0') +#define LCD_INSTANCE_FROM_GOP_THIS(a) CR (a, LCD_INSTANCE, Gop, LCD_INSTANCE_SIGNATURE) + +typedef struct { + UINTN Mode; + UINTN HorizontalResolution; + UINTN VerticalResolution; + + UINT32 DssDivisor; + UINT32 DispcDivisor; + + UINT32 HSync; + UINT32 HFrontPorch; + UINT32 HBackPorch; + + UINT32 VSync; + UINT32 VFrontPorch; + UINT32 VBackPorch; +} LCD_MODE; + +EFI_STATUS +InitializeDisplay ( + IN LCD_INSTANCE* Instance +); + +EFI_STATUS +EFIAPI +LcdGraphicsQueryMode ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN UINT32 ModeNumber, + OUT UINTN *SizeOfInfo, + OUT EFI_GRAPHICS_OUTPUT_MODE_INFORMATION **Info +); + +EFI_STATUS +EFIAPI +LcdGraphicsSetMode ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN UINT32 ModeNumber +); + +EFI_STATUS +EFIAPI +LcdGraphicsBlt ( + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *This, + IN OUT EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer, OPTIONAL + IN EFI_GRAPHICS_OUTPUT_BLT_OPERATION BltOperation, + IN UINTN SourceX, + IN UINTN SourceY, + IN UINTN DestinationX, + IN UINTN DestinationY, + IN UINTN Width, + IN UINTN Height, + IN UINTN Delta OPTIONAL // Number of BYTES in a row of the BltBuffer +); + +// HW registers +#define CM_FCLKEN_DSS 0x48004E00 +#define CM_ICLKEN_DSS 0x48004E10 + +#define DSS_CONTROL 0x48050040 +#define DSS_SYSCONFIG 0x48050010 +#define DSS_SYSSTATUS 0x48050014 + +#define DISPC_CONTROL 0x48050440 +#define DISPC_CONFIG 0x48050444 +#define DISPC_SIZE_LCD 0x4805047C +#define DISPC_TIMING_H 0x48050464 +#define DISPC_TIMING_V 0x48050468 + +#define CM_CLKSEL_DSS 0x48004E40 +#define DISPC_DIVISOR 0x48050470 +#define DISPC_POL_FREQ 0x4805046C + +#define DISPC_GFX_TABLE_BA 0x480504B8 +#define DISPC_GFX_BA0 0x48050480 +#define DISPC_GFX_BA1 0x48050484 +#define DISPC_GFX_POS 0x48050488 +#define DISPC_GFX_SIZE 0x4805048C +#define DISPC_GFX_ATTR 0x480504A0 +#define DISPC_GFX_PRELD 0x4805062C + +#define DISPC_DEFAULT_COLOR_0 0x4805044C + +//#define DISPC_IRQSTATUS + +// Bits +#define EN_TV 0x4 +#define EN_DSS2 0x2 +#define EN_DSS1 0x1 +#define EN_DSS 0x1 + +#define DSS_SOFTRESET 0x2 +#define DSS_RESETDONE 0x1 + +#define BYPASS_MODE (BIT15 | BIT16) + +#define LCDENABLE BIT0 +#define ACTIVEMATRIX BIT3 +#define GOLCD BIT5 +#define DATALINES24 (BIT8 | BIT9) +#define LCDENABLESIGNAL BIT28 + +#define GFXENABLE BIT0 +#define RGB16 (0x6 << 1) +#define BURSTSIZE16 (0x2 << 6) + +#define CLEARLOADMODE ~(BIT2 | BIT1) +#define LOAD_FRAME_ONLY BIT2 + +#endif diff --git a/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf b/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf new file mode 100644 index 000000000..f859b28c1 --- /dev/null +++ b/Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf @@ -0,0 +1,52 @@ +#/** @file +# +# Copyright (c) 2011, ARM Ltd. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = LcdGraphicsDxe + FILE_GUID = E68088EF-D1A4-4336-C1DB-4D3A204730A6 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = LcdGraphicsOutputDxeInitialize + +[Sources.common] + LcdGraphicsOutputDxe.c + LcdGraphicsOutputBlt.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + ArmLib + UefiLib + BaseLib + DebugLib + TimerLib + UefiDriverEntryPoint + UefiBootServicesTableLib + IoLib + BaseMemoryLib + +[Protocols] + gEfiDevicePathProtocolGuid + gEfiGraphicsOutputProtocolGuid + gEfiDevicePathToTextProtocolGuid + gEmbeddedExternalDeviceProtocolGuid + +[Depex] + gEfiCpuArchProtocolGuid AND gEfiTimerArchProtocolGuid diff --git a/Omap44xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c b/Omap44xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c new file mode 100755 index 000000000..b57a099c0 --- /dev/null +++ b/Omap44xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.c @@ -0,0 +1,166 @@ +/** @file + Debug Agent timer lib for OMAP. + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#include <Base.h> +#include <Library/BaseLib.h> +#include <Library/IoLib.h> +#include <Library/OmapLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> + +#include <Omap4430/Omap4430.h> + + +volatile UINT32 gVector; + +// Cached registers +volatile UINT32 gTISR; +volatile UINT32 gTCLR; +volatile UINT32 gTLDR; +volatile UINT32 gTCRR; +volatile UINT32 gTIER; + +VOID +EnableInterruptSource ( + VOID + ) +{ + UINTN Bank; + UINTN Bit; + + // Map vector to FIQ, IRQ is default + MmioWrite32 (INTCPS_ILR (gVector), 1); + + Bank = gVector / 32; + Bit = 1UL << (gVector % 32); + + MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit); +} + +VOID +DisableInterruptSource ( + VOID + ) +{ + UINTN Bank; + UINTN Bit; + + Bank = gVector / 32; + Bit = 1UL << (gVector % 32); + + MmioWrite32 (INTCPS_MIR_SET(Bank), Bit); +} + + + +/** + Setup all the hardware needed for the debug agents timer. + + This function is used to set up debug enviroment. It may enable interrupts. + +**/ +VOID +EFIAPI +DebugAgentTimerIntialize ( + VOID + ) +{ + UINT32 TimerBaseAddress; + UINT32 TimerNumber; + + TimerNumber = PcdGet32(PcdOmap44xxDebugAgentTimer); + gVector = InterruptVectorForTimer (TimerNumber); + + // Set up the timer registers + TimerBaseAddress = TimerBase (TimerNumber); + gTISR = TimerBaseAddress + GPTIMER_TISR; + gTCLR = TimerBaseAddress + GPTIMER_TCLR; + gTLDR = TimerBaseAddress + GPTIMER_TLDR; + gTCRR = TimerBaseAddress + GPTIMER_TCRR; + gTIER = TimerBaseAddress + GPTIMER_TIER; + + if ((TimerNumber < 2) || (TimerNumber > 9)) { + // This code assumes one the General Purpose timers is used + // GPT2 - GPT9 + CpuDeadLoop (); + } + // Set source clock for GPT2 - GPT9 to SYS_CLK + MmioOr32 (CM_CLKSEL_PER, 1 << (TimerNumber - 2)); + +} + + +/** + Set the period for the debug agent timer. Zero means disable the timer. + + @param[in] TimerPeriodMilliseconds Frequency of the debug agent timer. + +**/ +VOID +EFIAPI +DebugAgentTimerSetPeriod ( + IN UINT32 TimerPeriodMilliseconds + ) +{ + UINT64 TimerCount; + INT32 LoadValue; + + if (TimerPeriodMilliseconds == 0) { + // Turn off GPTIMER3 + MmioWrite32 (gTCLR, TCLR_ST_OFF); + + DisableInterruptSource (); + } else { + // Calculate required timer count + TimerCount = DivU64x32(TimerPeriodMilliseconds * 1000000, PcdGet32(PcdDebugAgentTimerFreqNanoSeconds)); + + // Set GPTIMER5 Load register + LoadValue = (INT32) -TimerCount; + MmioWrite32 (gTLDR, LoadValue); + MmioWrite32 (gTCRR, LoadValue); + + // Enable Overflow interrupt + MmioWrite32 (gTIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE); + + // Turn on GPTIMER3, it will reload at overflow + MmioWrite32 (gTCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON); + + EnableInterruptSource (); + } +} + + +/** + Perform End Of Interrupt for the debug agent timer. This is called in the + interrupt handler after the interrupt has been processed. + +**/ +VOID +EFIAPI +DebugAgentTimerEndOfInterrupt ( + VOID + ) +{ + // Clear all timer interrupts + MmioWrite32 (gTISR, TISR_CLEAR_ALL); + + // Poll interrupt status bits to ensure clearing + while ((MmioRead32 (gTISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING); + + MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWFIQAGR); + ArmDataSyncronizationBarrier (); + +} + + diff --git a/Omap44xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf b/Omap44xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf new file mode 100755 index 000000000..80ada2137 --- /dev/null +++ b/Omap44xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf @@ -0,0 +1,47 @@ +#/** @file +# Component description file for Base PCI Cf8 Library. +# +# PCI CF8 Library that uses I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles. +# Layers on top of an I/O Library instance. +# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = DebugAgentTimerLibNull + FILE_GUID = E82F99DE-74ED-4e56-BBA1-B143FCA3F69A + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = DebugAgentTimerLib|SEC BASE DXE_CORE + + +[Sources.common] + DebugAgentTimerLib.c + + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + ArmPkg/ArmPkg.dec + + +[LibraryClasses] + BaseLib + IoLib + OmapLib + ArmLib + +[Pcd] + gOmap44xxTokenSpaceGuid.PcdOmap44xxDebugAgentTimer + gOmap44xxTokenSpaceGuid.PcdDebugAgentTimerFreqNanoSeconds +
\ No newline at end of file diff --git a/Omap44xxPkg/Library/EblCmdLib/EblCmdLib.c b/Omap44xxPkg/Library/EblCmdLib/EblCmdLib.c new file mode 100644 index 000000000..5d7d84052 --- /dev/null +++ b/Omap44xxPkg/Library/EblCmdLib/EblCmdLib.c @@ -0,0 +1,72 @@ +/** @file + Add custom commands for PandaBoard development. + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <PiDxe.h> +#include <Library/ArmLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/EblCmdLib.h> +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiRuntimeServicesTableLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/UefiLib.h> +#include <Library/PcdLib.h> +#include <Library/EfiFileLib.h> + + +//PcdEmbeddedFdBaseAddress + +/** + Fill Me In + + Argv[0] - "%CommandName%" + + @param Argc Number of command arguments in Argv + @param Argv Array of strings that represent the parsed command line. + Argv[0] is the command name + + @return EFI_SUCCESS + +**/ +EFI_STATUS +EblEdk2Cmd ( + IN UINTN Argc, + IN CHAR8 **Argv + ) +{ + return EFI_SUCCESS; +} + + +GLOBAL_REMOVE_IF_UNREFERENCED const EBL_COMMAND_TABLE mLibCmdTemplate[] = +{ + { + "edk2", + " filename ; Load FD into memory and boot from it", + NULL, + EblEdk2Cmd + } +}; + + +VOID +EblInitializeExternalCmd ( + VOID + ) +{ + EblAddCommands (mLibCmdTemplate, sizeof (mLibCmdTemplate)/sizeof (EBL_COMMAND_TABLE)); + return; +} diff --git a/Omap44xxPkg/Library/EblCmdLib/EblCmdLib.inf b/Omap44xxPkg/Library/EblCmdLib/EblCmdLib.inf new file mode 100644 index 000000000..456d2c017 --- /dev/null +++ b/Omap44xxPkg/Library/EblCmdLib/EblCmdLib.inf @@ -0,0 +1,48 @@ +#/** @file +# Component description file for the entry point to a EFIDXE Drivers +# +# Library to abstract Framework extensions that conflict with UEFI 2.0 Specification +# Copyright (c) 2007 - 2007, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardEblCmdLib + FILE_GUID = ea62bdc3-1063-425f-8851-98cb47f213a8 + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = EblCmdLib|DXE_DRIVER UEFI_APPLICATION UEFI_DRIVER + + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources.common] + EblCmdLib.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + +[Protocols] + +[Guids] + +[Pcd] diff --git a/Omap44xxPkg/Library/GdbSerialLib/GdbSerialLib.c b/Omap44xxPkg/Library/GdbSerialLib/GdbSerialLib.c new file mode 100644 index 000000000..418db6e9d --- /dev/null +++ b/Omap44xxPkg/Library/GdbSerialLib/GdbSerialLib.c @@ -0,0 +1,102 @@ +/** @file + Basic serial IO abstaction for GDB + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Uefi.h> +#include <Library/GdbSerialLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Library/OmapLib.h> +#include <Omap4430/Omap4430.h> + +RETURN_STATUS +EFIAPI +GdbSerialLibConstructor ( + VOID + ) +{ + return RETURN_SUCCESS; +} + +RETURN_STATUS +EFIAPI +GdbSerialInit ( + IN UINT64 BaudRate, + IN UINT8 Parity, + IN UINT8 DataBits, + IN UINT8 StopBits + ) +{ + return RETURN_SUCCESS; +} + +BOOLEAN +EFIAPI +GdbIsCharAvailable ( + VOID + ) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + + if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) { + return TRUE; + } else { + return FALSE; + } +} + +CHAR8 +EFIAPI +GdbGetChar ( + VOID + ) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + UINT32 RBR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_RBR_REG; + CHAR8 Char; + + while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY); + Char = MmioRead8(RBR); + + return Char; +} + +VOID +EFIAPI +GdbPutChar ( + IN CHAR8 Char + ) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + UINT32 THR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_THR_REG; + + while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY); + MmioWrite8(THR, Char); +} + +VOID +GdbPutString ( + IN CHAR8 *String + ) +{ + while (*String != '\0') { + GdbPutChar (*String); + String++; + } +} + + + + diff --git a/Omap44xxPkg/Library/GdbSerialLib/GdbSerialLib.inf b/Omap44xxPkg/Library/GdbSerialLib/GdbSerialLib.inf new file mode 100644 index 000000000..34d75b1bd --- /dev/null +++ b/Omap44xxPkg/Library/GdbSerialLib/GdbSerialLib.inf @@ -0,0 +1,41 @@ +#/** @file +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = GdbSerialLib + FILE_GUID = E2423349-EF5D-439B-95F5-8B8D8E3B443F + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = GdbSerialLib + + CONSTRUCTOR = GdbSerialLibConstructor + + +[Sources.common] + GdbSerialLib.c + + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + DebugLib + IoLib + OmapLib + +[FixedPcd] + gOmap44xxTokenSpaceGuid.PcdOmap44xxConsoleUart + diff --git a/Omap44xxPkg/Library/Omap44xxTimerLib/Omap44xxTimerLib.inf b/Omap44xxPkg/Library/Omap44xxTimerLib/Omap44xxTimerLib.inf new file mode 100644 index 000000000..11cf1ad49 --- /dev/null +++ b/Omap44xxPkg/Library/Omap44xxTimerLib/Omap44xxTimerLib.inf @@ -0,0 +1,45 @@ +#/** @file +# Timer library implementation +# +# A non-functional instance of the Timer Library that can be used as a template +# for the implementation of a functional timer library instance. This library instance can +# also be used to test build DXE, Runtime, DXE SAL, and DXE SMM modules that require timer +# services as well as EBC modules that require timer services +# Copyright (c) 2007, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardTimerLib + FILE_GUID = fe1d7183-9abb-42ce-9a3b-36d7c6a8959f + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = TimerLib + +[Sources.common] + TimerLib.c + +[Packages] + Omap44xxPkg/Omap44xxPkg.dec + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + DebugLib + OmapLib + IoLib + +[Pcd] + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterPeriodInNanoseconds + gOmap44xxTokenSpaceGuid.PcdOmap44xxFreeTimer + diff --git a/Omap44xxPkg/Library/Omap44xxTimerLib/TimerLib.c b/Omap44xxPkg/Library/Omap44xxTimerLib/TimerLib.c new file mode 100644 index 000000000..55b952a39 --- /dev/null +++ b/Omap44xxPkg/Library/Omap44xxTimerLib/TimerLib.c @@ -0,0 +1,145 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Uefi.h> + +#include <Library/BaseLib.h> +#include <Library/TimerLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/OmapLib.h> +#include <Omap4430/Omap4430.h> + +RETURN_STATUS +EFIAPI +TimerConstructor ( + VOID + ) +{ + UINTN Timer = PcdGet32(PcdOmap44xxFreeTimer); + UINT32 TimerBaseAddress = TimerBase(Timer); + + // If the DMTIMER3 and DMTIMER4 are not enabled it is probably because it is the first call to TimerConstructor + if ((MmioRead32 (0x4A009440) & 0x3) == 0x0) { + // Enable DMTIMER3 with SYS_CLK source + MmioOr32(0x4A009440, 0x2); + + // Enable DMTIMER4 with SYS_CLK source + MmioOr32(0x4A009448, 0x2); + } + + if ((MmioRead32 (TimerBaseAddress + GPTIMER_TCLR) & TCLR_ST_ON) == 0) { + // Set count & reload registers + MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000); + MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000); + + // Disable interrupts + MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE); + + // Start Timer + MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON); + + /* Sending first command to turn off watchdog */ + MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA); + + /* Wait for write to complete */ + while( MmioBitFieldRead32(WDTIMER2_BASE + WWPS, 4, 5) ); + + /* Sending second command to turn off watchdog */ + MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555); + + /* Wait for write to complete */ + while( MmioBitFieldRead32(WDTIMER2_BASE + WWPS, 4, 5) ); + } + return EFI_SUCCESS; +} + +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + UINT64 NanoSeconds; + + NanoSeconds = MultU64x32(MicroSeconds, 1000); + + while (NanoSeconds > (UINTN)-1) { + NanoSecondDelay((UINTN)-1); + NanoSeconds -= (UINTN)-1; + } + + NanoSecondDelay(NanoSeconds); + + return MicroSeconds; +} + +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + UINT32 Delay; + UINT32 StartTime; + UINT32 CurrentTime; + UINT32 ElapsedTime; + UINT32 TimerCountRegister; + + Delay = (NanoSeconds / PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds)) + 1; + + TimerCountRegister = TimerBase(PcdGet32(PcdOmap44xxFreeTimer)) + GPTIMER_TCRR; + + StartTime = MmioRead32 (TimerCountRegister); + + do + { + CurrentTime = MmioRead32 (TimerCountRegister); + ElapsedTime = CurrentTime - StartTime; + } while (ElapsedTime < Delay); + + NanoSeconds = ElapsedTime * PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds); + + return NanoSeconds; +} + +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + return (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap44xxFreeTimer)) + GPTIMER_TCRR); +} + +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue != NULL) { + // Timer starts with the reload value + *StartValue = (UINT64)MmioRead32 (TimerBase(PcdGet32(PcdOmap44xxFreeTimer)) + GPTIMER_TLDR); + } + + if (EndValue != NULL) { + // Timer counts up to 0xFFFFFFFF + *EndValue = 0xFFFFFFFF; + } + + return PcdGet64(PcdEmbeddedPerformanceCounterFrequencyInHz); +} diff --git a/Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.c b/Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.c new file mode 100755 index 000000000..8926d41b5 --- /dev/null +++ b/Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.c @@ -0,0 +1,176 @@ +/** @file + Abstractions for simple OMAP DMA channel. + + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Library/DebugLib.h> +#include <Library/OmapDmaLib.h> +#include <Library/IoLib.h> +#include <Library/BaseMemoryLib.h> +#include <Omap4430/Omap4430.h> + + +/** + Configure OMAP DMA Channel + + @param Channel DMA Channel to configure + @param Dma4 Pointer to structure used to initialize DMA registers for the Channel + + @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. + @retval EFI_INVALID_PARAMETER Channel is not valid + @retval EFI_DEVICE_ERROR The system hardware could not map the requested information. + +**/ +EFI_STATUS +EFIAPI +EnableDmaChannel ( + IN UINTN Channel, + IN OMAP_DMA4 *DMA4 + ) +{ + UINT32 RegVal; + + + if (Channel > DMA4_MAX_CHANNEL) { + return EFI_INVALID_PARAMETER; + } + + /* 1) Configure the transfer parameters in the logical DMA registers */ + /*-------------------------------------------------------------------*/ + + /* a) Set the data type CSDP[1:0], the Read/Write Port access type + CSDP[8:7]/[15:14], the Source/dest endianism CSDP[21]/CSDP[19], + write mode CSDP[17:16], source/dest packed or nonpacked CSDP[6]/CSDP[13] */ + + // Read CSDP + RegVal = MmioRead32 (DMA4_CSDP (Channel)); + + // Build reg + RegVal = ((RegVal & ~ 0x3) | DMA4->DataType ); + RegVal = ((RegVal & ~(0x3 << 7)) | (DMA4->ReadPortAccessType << 7)); + RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessType << 14)); + RegVal = ((RegVal & ~(0x1 << 21)) | (DMA4->SourceEndiansim << 21)); + RegVal = ((RegVal & ~(0x1 << 19)) | (DMA4->DestinationEndianism << 19)); + RegVal = ((RegVal & ~(0x3 << 16)) | (DMA4->WriteMode << 16)); + RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->SourcePacked << 6)); + RegVal = ((RegVal & ~(0x1 << 13)) | (DMA4->DestinationPacked << 13)); + // Write CSDP + MmioWrite32 (DMA4_CSDP (Channel), RegVal); + + /* b) Set the number of element per frame CEN[23:0]*/ + MmioWrite32 (DMA4_CEN (Channel), DMA4->NumberOfElementPerFrame); + + /* c) Set the number of frame per block CFN[15:0]*/ + MmioWrite32 (DMA4_CFN (Channel), DMA4->NumberOfFramePerTransferBlock); + + /* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0]*/ + MmioWrite32 (DMA4_CSSA (Channel), DMA4->SourceStartAddress); + MmioWrite32 (DMA4_CDSA (Channel), DMA4->DestinationStartAddress); + + /* e) Set the Read Port addressing mode CCR[13:12], the Write Port addressing mode CCR[15:14], + read/write priority CCR[6]/CCR[26] + I changed LCH CCR[20:19]=00 and CCR[4:0]=00000 to + LCH CCR[20:19]= DMA4->WriteRequestNumber and CCR[4:0]=DMA4->ReadRequestNumber + */ + + // Read CCR + RegVal = MmioRead32 (DMA4_CCR (Channel)); + + // Build reg + RegVal = ((RegVal & ~0x1f) | DMA4->ReadRequestNumber); + RegVal = ((RegVal & ~(BIT20 | BIT19)) | DMA4->WriteRequestNumber << 19); + RegVal = ((RegVal & ~(0x3 << 12)) | (DMA4->ReadPortAccessMode << 12)); + RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessMode << 14)); + RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->ReadPriority << 6)); + RegVal = ((RegVal & ~(0x1 << 26)) | (DMA4->WritePriority << 26)); + + // Write CCR + MmioWrite32 (DMA4_CCR (Channel), RegVal); + + /* f)- Set the source element index CSEI[15:0]*/ + MmioWrite32 (DMA4_CSEI (Channel), DMA4->SourceElementIndex); + + /* - Set the source frame index CSFI[15:0]*/ + MmioWrite32 (DMA4_CSFI (Channel), DMA4->SourceFrameIndex); + + + /* - Set the destination element index CDEI[15:0]*/ + MmioWrite32 (DMA4_CDEI (Channel), DMA4->DestinationElementIndex); + + /* - Set the destination frame index CDFI[31:0]*/ + MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex); + + MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex); + + // Enable all the status bits since we are polling + MmioWrite32 (DMA4_CICR (Channel), DMA4_CICR_ENABLE_ALL); + MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET); + + /* 2) Start the DMA transfer by Setting the enable bit CCR[7]=1 */ + /*--------------------------------------------------------------*/ + //write enable bit + MmioOr32 (DMA4_CCR(Channel), DMA4_CCR_ENABLE); //Launch transfer + + return EFI_SUCCESS; +} + +/** + Turn of DMA channel configured by EnableDma(). + + @param Channel DMA Channel to configure + @param SuccesMask Bits in DMA4_CSR register indicate EFI_SUCCESS + @param ErrorMask Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR + + @retval EFI_SUCCESS DMA hardware disabled + @retval EFI_INVALID_PARAMETER Channel is not valid + @retval EFI_DEVICE_ERROR The system hardware could not map the requested information. + +**/ +EFI_STATUS +EFIAPI +DisableDmaChannel ( + IN UINTN Channel, + IN UINT32 SuccessMask, + IN UINT32 ErrorMask + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT32 Reg; + + + if (Channel > DMA4_MAX_CHANNEL) { + return EFI_INVALID_PARAMETER; + } + + do { + Reg = MmioRead32 (DMA4_CSR(Channel)); + if ((Reg & ErrorMask) != 0) { + Status = EFI_DEVICE_ERROR; + DEBUG ((EFI_D_ERROR, "DMA Error (%d) %x\n", Channel, Reg)); + break; + } + } while ((Reg & SuccessMask) != SuccessMask); + + + // Disable all status bits and clear them + MmioWrite32 (DMA4_CICR (Channel), 0); + MmioWrite32 (DMA4_CSR (Channel), DMA4_CSR_RESET); + + MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE)); + return Status; +} + + + diff --git a/Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.inf b/Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.inf new file mode 100755 index 000000000..90078e0df --- /dev/null +++ b/Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.inf @@ -0,0 +1,50 @@ +#/** @file +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = OmapDmaLib + FILE_GUID = 09B17D99-BB07-49a8-B0D2-06D6AFCBE3AB + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = OmapDmaLib + + +[Sources.common] + OmapDmaLib.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + DebugLib + UefiBootServicesTableLib + MemoryAllocationLib + UncachedMemoryAllocationLib + IoLib + BaseMemoryLib + ArmLib + + +[Protocols] + gEfiCpuArchProtocolGuid + +[Guids] + +[Pcd] + +[Depex] + gEfiCpuArchProtocolGuid
\ No newline at end of file diff --git a/Omap44xxPkg/Library/OmapLib/OmapLib.c b/Omap44xxPkg/Library/OmapLib/OmapLib.c new file mode 100644 index 000000000..5b7629074 --- /dev/null +++ b/Omap44xxPkg/Library/OmapLib/OmapLib.c @@ -0,0 +1,85 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Library/DebugLib.h> +#include <Library/OmapLib.h> +#include <Omap4430/Omap4430.h> + +UINT32 +GpioBase ( + IN UINTN Port + ) +{ + switch (Port) { + case 1: return GPIO1_BASE; + case 2: return GPIO2_BASE; + case 3: return GPIO3_BASE; + case 4: return GPIO4_BASE; + case 5: return GPIO5_BASE; + case 6: return GPIO6_BASE; + default: ASSERT(FALSE); return 0; + } +} + +UINT32 +TimerBase ( + IN UINTN Timer + ) +{ + switch (Timer) { + case 1: return GPTIMER1_BASE; + case 2: return GPTIMER2_BASE; + case 3: return GPTIMER3_BASE; + case 4: return GPTIMER4_BASE; + case 5: return GPTIMER5_BASE; + case 6: return GPTIMER6_BASE; + case 7: return GPTIMER7_BASE; + case 8: return GPTIMER8_BASE; + case 9: return GPTIMER9_BASE; + case 10: return GPTIMER10_BASE; + case 11: return GPTIMER11_BASE; + case 12: return GPTIMER12_BASE; + default: return 0; + } +} + +UINTN +InterruptVectorForTimer ( + IN UINTN Timer + ) +{ + if ((Timer < 1) || (Timer > 12)) { + ASSERT(FALSE); + return 0xFFFFFFFF; + } + + /* OD: On OMAP4, gic peripheral interrupts start at id 32 */ + /* return 36 + Timer; */ + return 32 + 36 + Timer; +} + +UINT32 +UartBase ( + IN UINTN Uart + ) +{ + switch (Uart) { + case 1: return UART1_BASE; + case 2: return UART2_BASE; + case 3: return UART3_BASE; + default: ASSERT(FALSE); return 0; + } +} + diff --git a/Omap44xxPkg/Library/OmapLib/OmapLib.inf b/Omap44xxPkg/Library/OmapLib/OmapLib.inf new file mode 100644 index 000000000..a92fc7791 --- /dev/null +++ b/Omap44xxPkg/Library/OmapLib/OmapLib.inf @@ -0,0 +1,37 @@ +#/** @file +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = OmapLib + FILE_GUID = d035f5c2-1b92-4746-9f6c-5ff6202970df + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = OmapLib + +[Sources.common] + OmapLib.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + DebugLib + +[Protocols] + +[Guids] + +[Pcd] diff --git a/Omap44xxPkg/Library/RealTimeClockLib/RealTimeClockLib.c b/Omap44xxPkg/Library/RealTimeClockLib/RealTimeClockLib.c new file mode 100644 index 000000000..b215b5512 --- /dev/null +++ b/Omap44xxPkg/Library/RealTimeClockLib/RealTimeClockLib.c @@ -0,0 +1,303 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Uefi.h> + +#include <Library/BaseMemoryLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiRuntimeServicesTableLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> + +#include <Protocol/RealTimeClock.h> +#include <Protocol/EmbeddedExternalDevice.h> + +#include <Omap4430/Omap4430.h> +#include <TWL6030.h> + + +EMBEDDED_EXTERNAL_DEVICE *gTWL6030; +INT16 TimeZone = EFI_UNSPECIFIED_TIMEZONE; + +/** + Returns the current time and date information, and the time-keeping capabilities + of the hardware platform. + + @param Time A pointer to storage to receive a snapshot of the current time. + @param Capabilities An optional pointer to a buffer to receive the real time clock + device's capabilities. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error. + +**/ +EFI_STATUS +EFIAPI +LibGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities + ) +{ + EFI_STATUS Status; + UINT8 Data; + EFI_TPL OldTpl; + + if (Time == NULL) { + return EFI_INVALID_PARAMETER; + } + + OldTpl = gBS->RaiseTPL(TPL_NOTIFY); + + /* Get time and date */ + ZeroMem(Time, sizeof(EFI_TIME)); + + // Latch values + Status = gTWL6030->Read (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, RTC_CTRL_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + Data |= BIT6; + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, RTC_CTRL_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + + // Read registers + Status = gTWL6030->Read (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, YEARS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + Time->Year = 2000 + ((Data >> 4) & 0xF) * 10 + (Data & 0xF); + + Status = gTWL6030->Read (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MONTHS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + Time->Month = ((Data >> 4) & 0x1) * 10 + (Data & 0xF); + + Status = gTWL6030->Read (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, DAYS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + Time->Day = ((Data >> 4) & 0x3) * 10 + (Data & 0xF); + + Status = gTWL6030->Read (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, HOURS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + Time->Hour = ((Data >> 4) & 0x3) * 10 + (Data & 0xF); + + Status = gTWL6030->Read (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MINUTES_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + Time->Minute = ((Data >> 4) & 0x7) * 10 + (Data & 0xF); + + Status = gTWL6030->Read (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, SECONDS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + Time->Second = ((Data >> 4) & 0x7) * 10 + (Data & 0xF); + + Time->TimeZone = TimeZone; + // TODO: check what to use here + Time->Daylight = EFI_TIME_ADJUST_DAYLIGHT; + + // Set capabilities + + // TODO: Set real capabilities + if (Capabilities != NULL) { + Capabilities->Resolution = 1; + Capabilities->Accuracy = 50000000; + Capabilities->SetsToZero = FALSE; + } + +EXIT: + gBS->RestoreTPL(OldTpl); + + return (Status == EFI_SUCCESS) ? Status : EFI_DEVICE_ERROR; +} + +/** + Sets the current local time and date information. + + @param Time A pointer to the current time. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error. + +**/ +EFI_STATUS +EFIAPI +LibSetTime ( + IN EFI_TIME *Time + ) +{ + EFI_STATUS Status; + UINT8 Data; + UINT8 MonthDayCount[12] = { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; + EFI_TPL OldTpl; + + // Input validation according both to UEFI spec and hardware constraints + // UEFI spec says valid year range is 1900-9999 but TPS only supports 2000-2099 + if ( (Time == NULL) + || (Time->Year < 2000 || Time->Year > 2099) + || (Time->Month < 1 || Time->Month > 12) + || (Time->Day < 1 || Time->Day > MonthDayCount[Time->Month]) + || (Time->Hour > 23) + || (Time->Minute > 59) + || (Time->Second > 59) + || (Time->Nanosecond > 999999999) + || ((Time->TimeZone < -1440 || Time->TimeZone > 1440) && Time->TimeZone != 2047) + ) { + return EFI_INVALID_PARAMETER; + } + + OldTpl = gBS->RaiseTPL(TPL_NOTIFY); + + Data = Time->Year - 2000; + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, YEARS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + + Data = ((Time->Month / 10) << 4) | (Time->Month % 10); + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MONTHS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + + Data = ((Time->Day / 10) << 4) | (Time->Day % 10); + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, DAYS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + + Data = ((Time->Hour / 10) << 4) | (Time->Hour % 10); + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, HOURS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + + Data = ((Time->Minute / 10) << 4) | (Time->Minute % 10); + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MINUTES_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + + Data = ((Time->Second / 10) << 4) | (Time->Second % 10); + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, SECONDS_REG), 1, &Data); + if (Status != EFI_SUCCESS) goto EXIT; + + TimeZone = Time->TimeZone; + +EXIT: + gBS->RestoreTPL(OldTpl); + + return (Status == EFI_SUCCESS) ? Status : EFI_DEVICE_ERROR; +} + +/** + Returns the current wakeup alarm clock setting. + + @param Enabled Indicates if the alarm is currently enabled or disabled. + @param Pending Indicates if the alarm signal is pending and requires acknowledgement. + @param Time The current alarm setting. + + @retval EFI_SUCCESS The alarm settings were returned. + @retval EFI_INVALID_PARAMETER Any parameter is NULL. + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error. + +**/ +EFI_STATUS +EFIAPI +LibGetWakeupTime ( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Sets the system wakeup alarm clock time. + + @param Enabled Enable or disable the wakeup alarm. + @param Time If Enable is TRUE, the time to set the wakeup alarm for. + + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If + Enable is FALSE, then the wakeup alarm was disabled. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform. + +**/ +EFI_STATUS +EFIAPI +LibSetWakeupTime ( + IN BOOLEAN Enabled, + OUT EFI_TIME *Time + ) +{ + return EFI_UNSUPPORTED; +} + +/** + This is the declaration of an EFI image entry point. This can be the entry point to an application + written to this specification, an EFI boot service driver, or an EFI runtime driver. + + @param ImageHandle Handle that identifies the loaded image. + @param SystemTable System Table for this image. + + @retval EFI_SUCCESS The operation completed successfully. + +**/ +EFI_STATUS +EFIAPI +LibRtcInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + // TODO: adapt to Panda +#if 0 + UINT8 Data; + EFI_TPL OldTpl; +#endif + + Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTWL6030); + ASSERT_EFI_ERROR(Status); + +#if 0 + OldTpl = gBS->RaiseTPL(TPL_NOTIFY); + Data = 1; + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, RTC_CTRL_REG), 1, &Data); + ASSERT_EFI_ERROR(Status); + gBS->RestoreTPL(OldTpl); +#endif + + // Setup the setters and getters + gRT->GetTime = LibGetTime; + gRT->SetTime = LibSetTime; + gRT->GetWakeupTime = LibGetWakeupTime; + gRT->SetWakeupTime = LibSetWakeupTime; + + // Install the protocol + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiRealTimeClockArchProtocolGuid, NULL, + NULL + ); + + return Status; +} + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +LibRtcVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + return; +} diff --git a/Omap44xxPkg/Library/RealTimeClockLib/RealTimeClockLib.inf b/Omap44xxPkg/Library/RealTimeClockLib/RealTimeClockLib.inf new file mode 100755 index 000000000..b1fa82a33 --- /dev/null +++ b/Omap44xxPkg/Library/RealTimeClockLib/RealTimeClockLib.inf @@ -0,0 +1,38 @@ +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = RealTimeClockLib + FILE_GUID = EC1713DB-7DB5-4c99-8FE2-6F52F95A1132 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = RealTimeClockLib + +[Sources.common] + RealTimeClockLib.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + IoLib + UefiLib + DebugLib + PcdLib + +[Protocols] + gEmbeddedExternalDeviceProtocolGuid + +[depex] + gEmbeddedExternalDeviceProtocolGuid diff --git a/Omap44xxPkg/Library/ResetSystemLib/ResetSystemLib.c b/Omap44xxPkg/Library/ResetSystemLib/ResetSystemLib.c new file mode 100644 index 000000000..a2af61264 --- /dev/null +++ b/Omap44xxPkg/Library/ResetSystemLib/ResetSystemLib.c @@ -0,0 +1,90 @@ +/** @file + Template library implementation to support ResetSystem Runtime call. + + Fill in the templates with what ever makes you system reset. + + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +#include <PiDxe.h> + +#include <Library/PcdLib.h> +#include <Library/ArmLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/DebugLib.h> +#include <Library/EfiResetSystemLib.h> + + +/** + Resets the entire platform. + + @param ResetType The type of reset to perform. + @param ResetStatus The status code for the reset. + @param DataSize The size, in bytes, of WatchdogData. + @param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or + EfiResetShutdown the data buffer starts with a Null-terminated + Unicode string, optionally followed by additional binary data. + +**/ +EFI_STATUS +EFIAPI +LibResetSystem ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN CHAR16 *ResetData OPTIONAL + ) +{ + if (ResetData != NULL) { + DEBUG((EFI_D_ERROR, "%s", ResetData)); + } + + switch (ResetType) { + case EfiResetWarm: + // Map a warm reset into a cold reset + case EfiResetCold: + case EfiResetShutdown: + default: + // Perform cold reset of the system. + MmioOr32 (PRM_RSTCTRL, RST_DPLL3); + while ((MmioRead32 (PRM_RSTST) & GLOBAL_COLD_RST) != 0x1); + break; + } + + // If the reset didn't work, return an error. + ASSERT (FALSE); + return EFI_DEVICE_ERROR; +} + + + +/** + Initialize any infrastructure required for LibResetSystem () to function. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +LibInitializeResetSystem ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return EFI_SUCCESS; +} + diff --git a/Omap44xxPkg/Library/ResetSystemLib/ResetSystemLib.inf b/Omap44xxPkg/Library/ResetSystemLib/ResetSystemLib.inf new file mode 100644 index 000000000..986ddb551 --- /dev/null +++ b/Omap44xxPkg/Library/ResetSystemLib/ResetSystemLib.inf @@ -0,0 +1,40 @@ +#/** @file +# Reset System lib to make it easy to port new platforms +# +# Copyright (c) 2008, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardResetSystemLib + FILE_GUID = 781371a2-3fdd-41d4-96a1-7b34cbc9e895 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = EfiResetSystemLib + + +[Sources.common] + ResetSystemLib.c + +[Packages] + Omap44xxPkg/Omap44xxPkg.dec + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[Pcd.common] + gArmTokenSpaceGuid.PcdCpuResetAddress + gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress + +[LibraryClasses] + DebugLib + PandaBoardSystemLib diff --git a/Omap44xxPkg/Library/SerialPortLib/SerialPortLib.c b/Omap44xxPkg/Library/SerialPortLib/SerialPortLib.c new file mode 100644 index 000000000..9162c6c84 --- /dev/null +++ b/Omap44xxPkg/Library/SerialPortLib/SerialPortLib.c @@ -0,0 +1,155 @@ +/** @file + Serial I/O Port library functions with no library constructor/destructor + + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Base.h> +#include <Library/DebugLib.h> +#include <Library/SerialPortLib.h> +#include <Library/SerialPortExtLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/OmapLib.h> +#include <Omap4430/Omap4430.h> + +/* + + Programmed hardware of Serial port. + + @return Always return EFI_UNSUPPORTED. + +**/ +RETURN_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + UINTN Uart = PcdGet32(PcdOmap44xxConsoleUart); + UINT32 UartBaseAddress = UartBase(Uart); + + // Configure UART3 pads + MmioAnd32(0x4A100144, ~0x70007); + + // Enable UART3 clocks + MmioOr32(0x4A009550, 0x2); + + // Set MODE_SELECT=DISABLE before trying to initialize or modify DLL, DLH registers. + MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE); + + // Put device in configuration mode. + MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE); + + // Programmable divisor N = 48Mhz/16/115200 = 26 + MmioWrite32 (UartBaseAddress + UART_DLL_REG, 3000000 / PcdGet64 (PcdUartDefaultBaudRate)); // low divisor + MmioWrite32 (UartBaseAddress + UART_DLH_REG, 0); // high divisor + + // Enter into UART operational mode. + MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8); + + // Force DTR and RTS output to active + MmioWrite32 (UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE); + + // Clear & enable fifos + MmioWrite32 (UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE); + + // Restore MODE_SELECT + MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X); + + return RETURN_SUCCESS; +} + +/** + Write data to serial device. + + @param Buffer Point of data buffer which need to be writed. + @param NumberOfBytes Number of output bytes which are cached in Buffer. + + @retval 0 Write data failed. + @retval !0 Actual number of bytes writed to serial device. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes +) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + UINT32 THR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_THR_REG; + UINTN Count; + + for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) { + while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY); + MmioWrite8(THR, *Buffer); + } + + return NumberOfBytes; +} + + +/** + Read data from serial device and save the datas in buffer. + + @param Buffer Point of data buffer which need to be writed. + @param NumberOfBytes Number of output bytes which are cached in Buffer. + + @retval 0 Read data failed. + @retval !0 Aactual number of bytes read from serial device. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes +) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + UINT32 RBR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_RBR_REG; + UINTN Count; + + for (Count = 0; Count < NumberOfBytes; Count++, Buffer++) { + while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY); + *Buffer = MmioRead8(RBR); + } + + return NumberOfBytes; +} + + +/** + Check to see if any data is avaiable to be read from the debug device. + + @retval EFI_SUCCESS At least one byte of data is avaiable to be read + @retval EFI_NOT_READY No data is avaiable to be read + @retval EFI_DEVICE_ERROR The serial device is not functioning properly + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + + if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) { + return TRUE; + } else { + return FALSE; + } +} + diff --git a/Omap44xxPkg/Library/SerialPortLib/SerialPortLib.inf b/Omap44xxPkg/Library/SerialPortLib/SerialPortLib.inf new file mode 100644 index 000000000..07db0f837 --- /dev/null +++ b/Omap44xxPkg/Library/SerialPortLib/SerialPortLib.inf @@ -0,0 +1,44 @@ +#/** @file +# EDK Serial port lib +# +# Copyright (c) 2009, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardSerialPortLib + FILE_GUID = 97546cbd-c0ff-4c48-ab0b-e4f58862acd3 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = SerialPortLib + + +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources.common] + SerialPortLib.c + +[LibraryClasses] + DebugLib + IoLib + OmapLib + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[FixedPcd] + gOmap44xxTokenSpaceGuid.PcdOmap44xxConsoleUart + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate diff --git a/Omap44xxPkg/MmcHostDxe/MmcHostDxe.c b/Omap44xxPkg/MmcHostDxe/MmcHostDxe.c new file mode 100644 index 000000000..687428b1e --- /dev/null +++ b/Omap44xxPkg/MmcHostDxe/MmcHostDxe.c @@ -0,0 +1,700 @@ +/** @file +* +* Copyright (c) 2008 - 2009, Apple Inc. All rights reserved. +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "MmcHostDxe.h" + +EMBEDDED_EXTERNAL_DEVICE *gTWL6030; +UINT8 mMaxDataTransferRate = 0; +UINT32 mRca = 0; +BOOLEAN mBitModeSet = FALSE; + + +typedef struct { + VENDOR_DEVICE_PATH Mmc; + EFI_DEVICE_PATH End; +} MMCHS_DEVICE_PATH; + +MMCHS_DEVICE_PATH gMMCDevicePath = { + { + { + HARDWARE_DEVICE_PATH, + HW_VENDOR_DP, + { + (UINT8)(sizeof(VENDOR_DEVICE_PATH)), + (UINT8)((sizeof(VENDOR_DEVICE_PATH)) >> 8) + }, + }, + { 0xb615f1f5, 0x5088, 0x43cd, { 0x80, 0x9c, 0xa1, 0x6e, 0x52, 0x48, 0x7d, 0x00 } } + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } + } +}; + +BOOLEAN +IgnoreCommand ( + UINT32 Command + ) +{ + switch(Command) { + case MMC_CMD12: + return TRUE; + case MMC_CMD13: + return TRUE; + default: + return FALSE; + } +} + +UINT32 +TranslateCommand ( + UINT32 Command + ) +{ + UINT32 Translation; + + switch(Command) { + case MMC_CMD2: + Translation = CMD2; + break; + case MMC_CMD3: + Translation = CMD3; + break; + /*case MMC_CMD6: + Translation = CMD6; + break;*/ + case MMC_CMD7: + Translation = CMD7; + break; + case MMC_CMD8: + Translation = CMD8; + break; + case MMC_CMD9: + Translation = CMD9; + break; + /*case MMC_CMD12: + Translation = CMD12; + break; + case MMC_CMD13: + Translation = CMD13; + break;*/ + case MMC_CMD16: + Translation = CMD16; + break; + case MMC_CMD17: + Translation = 0x113A0014;//CMD17; + break; + case MMC_CMD24: + Translation = CMD24 | 4; + break; + case MMC_CMD55: + Translation = CMD55; + break; + case MMC_ACMD41: + Translation = ACMD41; + break; + default: + Translation = Command; + } + + return Translation; +} + +VOID +CalculateCardCLKD ( + UINTN *ClockFrequencySelect + ) +{ + UINTN TransferRateValue = 0; + UINTN TimeValue = 0 ; + UINTN Frequency = 0; + + DEBUG ((DEBUG_BLKIO, "CalculateCardCLKD()\n")); + + // For SD Cards we would need to send CMD6 to set + // speeds abouve 25MHz. High Speed mode 50 MHz and up + + // Calculate Transfer rate unit (Bits 2:0 of TRAN_SPEED) + switch (mMaxDataTransferRate & 0x7) { // 2 + case 0: + TransferRateValue = 100 * 1000; + break; + + case 1: + TransferRateValue = 1 * 1000 * 1000; + break; + + case 2: + TransferRateValue = 10 * 1000 * 1000; + break; + + case 3: + TransferRateValue = 100 * 1000 * 1000; + break; + + default: + DEBUG ((DEBUG_BLKIO, "Invalid parameter.\n")); + ASSERT(FALSE); + return; + } + + //Calculate Time value (Bits 6:3 of TRAN_SPEED) + switch ((mMaxDataTransferRate >> 3) & 0xF) { // 6 + case 1: + TimeValue = 10; + break; + + case 2: + TimeValue = 12; + break; + + case 3: + TimeValue = 13; + break; + + case 4: + TimeValue = 15; + break; + + case 5: + TimeValue = 20; + break; + + case 6: + TimeValue = 25; + break; + + case 7: + TimeValue = 30; + break; + + case 8: + TimeValue = 35; + break; + + case 9: + TimeValue = 40; + break; + + case 10: + TimeValue = 45; + break; + + case 11: + TimeValue = 50; + break; + + case 12: + TimeValue = 55; + break; + + case 13: + TimeValue = 60; + break; + + case 14: + TimeValue = 70; + break; + + case 15: + TimeValue = 80; + break; + + default: + DEBUG ((DEBUG_BLKIO, "Invalid parameter.\n")); + ASSERT(FALSE); + return; + } + + Frequency = TransferRateValue * TimeValue/10; + + // Calculate Clock divider value to program in MMCHS_SYSCTL[CLKD] field. + *ClockFrequencySelect = ((MMC_REFERENCE_CLK/Frequency) + 1); + + DEBUG ((DEBUG_BLKIO, "mMaxDataTransferRate: 0x%x, Frequency: %d KHz, ClockFrequencySelect: %x\n", mMaxDataTransferRate, Frequency/1000, *ClockFrequencySelect)); +} + +VOID +UpdateMMCHSClkFrequency ( + UINTN NewCLKD + ) +{ + DEBUG ((DEBUG_BLKIO, "UpdateMMCHSClkFrequency()\n")); + + // Set Clock enable to 0x0 to not provide the clock to the card + MmioAnd32 (MMCHS_SYSCTL, ~CEN); + + // Set new clock frequency. + MmioAndThenOr32 (MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6); + + // Poll till Internal Clock Stable + while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) != ICS); + + // Set Clock enable to 0x1 to provide the clock to the card + MmioOr32 (MMCHS_SYSCTL, CEN); +} + +EFI_STATUS +InitializeMMCHS ( + VOID + ) +{ + UINT8 Data; + EFI_STATUS Status; + + DEBUG ((DEBUG_BLKIO, "InitializeMMCHS()\n")); + + // Disconnect PBIAS prior to voltage change + MmioAnd32 (CONTROL_PBIAS_LITE, ~(PBIASPWRDNZ | PBIASLITEPWRDNZ)); + + // Disable VMMC LDO + Data = VMMC_CFG_STATE_OFF; + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID1, VMMC_CFG_STATE), 1, &Data); + ASSERT_EFI_ERROR(Status); + + // Wait for stabilization + gBS->Stall(500); + + // Configure VMMC LDO to output 3.0 voltage. + Data = VSEL_3_00V; + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID1, VMMC_CFG_VOLTAGE), 1, &Data); + ASSERT_EFI_ERROR(Status); + + // Enable VMMC LDO + Data = VMMC_CFG_STATE_ON; + Status = gTWL6030->Write (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID1, VMMC_CFG_STATE), 1, &Data); + ASSERT_EFI_ERROR(Status); + + // Wait for stabilization + gBS->Stall(500); + + // PBIAS in normal operating mode (not HiZ) + MmioAnd32 (CONTROL_PBIAS_LITE, ~PBIASHIZ); + + // Select VMODE=3V and connect VDDS_MMC1 to PBIAS + MmioOr32 (CONTROL_PBIAS_LITE, (PBIASVMODE3V|PBIASLITEPWRDNZ)); + + // Wait for PBIAS supply detection + gBS->Stall(100); + + // Connect pads + MmioOr32 (CONTROL_PBIAS_LITE, PBIASPWRDNZ); + + // Stop here if supply detector did not sense 3V + ASSERT( !(MmioRead32(CONTROL_PBIAS_LITE) & PBIASVMODEERR) ); + + return Status; +} + +BOOLEAN +MMCIsCardPresent ( + IN EFI_MMC_HOST_PROTOCOL *This + ) +{ + EFI_STATUS Status; + UINT8 Data; + + // + // Card detect is a GPIO0 on the TWL6030 + // + Status = gTWL6030->Read (gTWL6030, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID1, MMCCTRL), 1, &Data); + if (EFI_ERROR (Status)) { + return FALSE; + } + + return !(Data & CARD_DET_STS_MMC); + +} + +BOOLEAN +MMCIsReadOnly ( + IN EFI_MMC_HOST_PROTOCOL *This + ) +{ + /* Note: + * On our BeagleBoard the SD card WP pin is always read as TRUE. + * Probably something wrong with GPIO configuration. + * BeagleBoard-xM uses microSD cards so there is no write protect at all. + * Hence commenting out SD card WP pin read status. + */ + //return (MmioRead32 (GPIO1_BASE + GPIO_DATAIN) & BIT23) == BIT23; + return 0; + +} + +// TODO +EFI_GUID mPL180MciDevicePathGuid = EFI_CALLER_ID_GUID; + +EFI_STATUS +MMCBuildDevicePath ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL **DevicePath + ) +{ + EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode; + + NewDevicePathNode = CreateDeviceNode(HARDWARE_DEVICE_PATH,HW_VENDOR_DP,sizeof(VENDOR_DEVICE_PATH)); + CopyGuid(&((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid,&mPL180MciDevicePathGuid); + *DevicePath = NewDevicePathNode; + return EFI_SUCCESS; +} + +EFI_STATUS +MMCSendCommand ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN MMC_CMD MmcCmd, + IN UINT32 Argument + ) +{ + UINTN MmcStatus; + UINTN RetryCount = 0; + + if (IgnoreCommand(MmcCmd)) + return EFI_SUCCESS; + + MmcCmd = TranslateCommand(MmcCmd); + + //DEBUG ((EFI_D_ERROR, "MMCSendCommand(%d)\n", MmcCmd)); + + // Check if command line is in use or not. Poll till command line is available. + while ((MmioRead32 (MMCHS_PSTATE) & DATI_MASK) == DATI_NOT_ALLOWED); + + // Provide the block size. + MmioWrite32 (MMCHS_BLK, BLEN_512BYTES); + + // Setting Data timeout counter value to max value. + MmioAndThenOr32 (MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL); + + // Clear Status register. + MmioWrite32 (MMCHS_STAT, 0xFFFFFFFF); + + // Set command argument register + MmioWrite32 (MMCHS_ARG, Argument); + + //TODO: fix this + //Enable interrupt enable events to occur + //MmioWrite32 (MMCHS_IE, CmdInterruptEnableVal); + + // Send a command + MmioWrite32 (MMCHS_CMD, MmcCmd); + + // Check for the command status. + while (RetryCount < MAX_RETRY_COUNT) { + do { + MmcStatus = MmioRead32 (MMCHS_STAT); + } while (MmcStatus == 0); + + // Read status of command response + if ((MmcStatus & ERRI) != 0) { + + // Perform soft-reset for mmci_cmd line. + MmioOr32 (MMCHS_SYSCTL, SRC); + while ((MmioRead32 (MMCHS_SYSCTL) & SRC)); + + //DEBUG ((EFI_D_INFO, "MmcStatus: 0x%x\n", MmcStatus)); + return EFI_DEVICE_ERROR; + } + + // Check if command is completed. + if ((MmcStatus & CC) == CC) { + MmioWrite32 (MMCHS_STAT, CC); + break; + } + + RetryCount++; + } + + if (RetryCount == MAX_RETRY_COUNT) { + DEBUG ((DEBUG_BLKIO, "MMCSendCommand: Timeout\n")); + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +MMCNotifyState ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN MMC_STATE State + ) +{ + EFI_STATUS Status; + UINTN FreqSel; + + switch(State) { + case MmcInvalidState: + ASSERT(0); + break; + case MmcHwInitializationState: + mBitModeSet = FALSE; + + DEBUG ((DEBUG_BLKIO, "MMCHwInitializationState()\n")); + Status = InitializeMMCHS (); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_BLKIO, "Initialize MMC host controller fails. Status: %x\n", Status)); + return Status; + } + + // Software reset of the MMCHS host controller. + MmioWrite32 (MMCHS_SYSCONFIG, SOFTRESET); + gBS->Stall(1000); + while ((MmioRead32 (MMCHS_SYSSTATUS) & RESETDONE_MASK) != RESETDONE); + + // Soft reset for all. + MmioWrite32 (MMCHS_SYSCTL, SRA); + gBS->Stall(1000); + while ((MmioRead32 (MMCHS_SYSCTL) & SRA) != 0x0); + + //Voltage capabilities initialization. Activate VS18 and VS30. + MmioOr32 (MMCHS_CAPA, (VS30 | VS18)); + + // Wakeup configuration + MmioOr32 (MMCHS_SYSCONFIG, ENAWAKEUP); + MmioOr32 (MMCHS_HCTL, IWE); + + // MMCHS Controller default initialization + MmioOr32 (MMCHS_CON, (OD | DW8_1_4_BIT | CEATA_OFF)); + + MmioWrite32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_OFF)); + + // Enable internal clock + MmioOr32 (MMCHS_SYSCTL, ICE); + + // Set the clock frequency to 80KHz. + UpdateMMCHSClkFrequency (CLKD_80KHZ); + + // Enable SD bus power. + MmioOr32 (MMCHS_HCTL, (SDBP_ON)); + + // Poll till SD bus power bit is set. + while ((MmioRead32 (MMCHS_HCTL) & SDBP_MASK) != SDBP_ON); + + // Enable interrupts. + MmioWrite32 (MMCHS_IE, (BADA_EN | CERR_EN | DEB_EN | DCRC_EN | DTO_EN | CIE_EN | + CEB_EN | CCRC_EN | CTO_EN | BRR_EN | BWR_EN | TC_EN | CC_EN)); + + // Controller INIT procedure start. + MmioOr32 (MMCHS_CON, INIT); + MmioWrite32 (MMCHS_CMD, 0x00000000); + while (!(MmioRead32 (MMCHS_STAT) & CC)); + + // Wait for 1 ms + gBS->Stall (1000); + + // Set CC bit to 0x1 to clear the flag + MmioOr32 (MMCHS_STAT, CC); + + // Retry INIT procedure. + MmioWrite32 (MMCHS_CMD, 0x00000000); + while (!(MmioRead32 (MMCHS_STAT) & CC)); + + // End initialization sequence + MmioAnd32 (MMCHS_CON, ~INIT); + + MmioOr32 (MMCHS_HCTL, (SDVS_3_0_V | DTW_1_BIT | SDBP_ON)); + + // Change clock frequency to 400KHz to fit protocol + UpdateMMCHSClkFrequency(CLKD_400KHZ); + + MmioOr32 (MMCHS_CON, OD); + break; + case MmcIdleState: + break; + case MmcReadyState: + break; + case MmcIdentificationState: + break; + case MmcStandByState: + CalculateCardCLKD (&FreqSel); + UpdateMMCHSClkFrequency (FreqSel); + break; + case MmcTransferState: + if (!mBitModeSet) { + Status = MMCSendCommand (This, CMD55, mRca << 16); + if (!EFI_ERROR (Status)) { + // Set device into 4-bit data bus mode + Status = MMCSendCommand (This, ACMD6, 0x2); + if (!EFI_ERROR (Status)) { + // Set host controler into 4-bit mode + MmioOr32 (MMCHS_HCTL, DTW_4_BIT); + DEBUG ((DEBUG_BLKIO, "SD Memory Card set to 4-bit mode\n")); + mBitModeSet = TRUE; + } + } + } + break; + case MmcSendingDataState: + break; + case MmcReceiveDataState: + break; + case MmcProgrammingState: + break; + case MmcDisconnectState: + default: + ASSERT(0); + } + return EFI_SUCCESS; +} + +EFI_STATUS +MMCReceiveResponse ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN MMC_RESPONSE_TYPE Type, + IN UINT32* Buffer + ) +{ + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (Type == MMC_RESPONSE_TYPE_R2) { + Buffer[0] = MmioRead32 (MMCHS_RSP10); + Buffer[1] = MmioRead32 (MMCHS_RSP32); + Buffer[2] = MmioRead32 (MMCHS_RSP54); + Buffer[3] = MmioRead32 (MMCHS_RSP76); + } else { + Buffer[0] = MmioRead32 (MMCHS_RSP10); + } + + if (Type == MMC_RESPONSE_TYPE_CSD) { + mMaxDataTransferRate = Buffer[3] & 0xFF; + } else if (Type == MMC_RESPONSE_TYPE_RCA) { + mRca = Buffer[0] >> 16; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +MMCReadBlockData ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Length, + IN UINT32* Buffer + ) +{ + UINTN MmcStatus; + UINTN Count; + UINTN RetryCount = 0; + + DEBUG ((DEBUG_BLKIO, "MMCReadBlockData(LBA: 0x%x, Length: 0x%x, Buffer: 0x%x)\n", Lba, Length, Buffer)); + + // Check controller status to make sure there is no error. + while (RetryCount < MAX_RETRY_COUNT) { + do { + // Read Status. + MmcStatus = MmioRead32 (MMCHS_STAT); + } while(MmcStatus == 0); + + // Check if Buffer read ready (BRR) bit is set? + if (MmcStatus & BRR) { + + // Clear BRR bit + MmioOr32 (MMCHS_STAT, BRR); + + for (Count = 0; Count < Length / 4; Count++) { + *Buffer++ = MmioRead32(MMCHS_DATA); + } + break; + } + RetryCount++; + } + + if (RetryCount == MAX_RETRY_COUNT) { + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +MMCWriteBlockData ( + IN EFI_MMC_HOST_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Length, + IN UINT32* Buffer + ) +{ + UINTN MmcStatus; + UINTN Count; + UINTN RetryCount = 0; + + // Check controller status to make sure there is no error. + while (RetryCount < MAX_RETRY_COUNT) { + do { + // Read Status. + MmcStatus = MmioRead32 (MMCHS_STAT); + } while(MmcStatus == 0); + + // Check if Buffer write ready (BWR) bit is set? + if (MmcStatus & BWR) { + + // Clear BWR bit + MmioOr32 (MMCHS_STAT, BWR); + + // Write block worth of data. + for (Count = 0; Count < Length / 4; Count++) { + MmioWrite32 (MMCHS_DATA, *Buffer++); + } + + break; + } + RetryCount++; + } + + if (RetryCount == MAX_RETRY_COUNT) { + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +EFI_MMC_HOST_PROTOCOL gMMCHost = { + MMC_HOST_PROTOCOL_REVISION, + MMCIsCardPresent, + MMCIsReadOnly, + MMCBuildDevicePath, + MMCNotifyState, + MMCSendCommand, + MMCReceiveResponse, + MMCReadBlockData, + MMCWriteBlockData +}; + +EFI_STATUS +MMCInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle = NULL; + + DEBUG ((DEBUG_BLKIO, "MMCInitialize()\n")); + + Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTWL6030); + ASSERT_EFI_ERROR(Status); + + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiMmcHostProtocolGuid, &gMMCHost, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Omap44xxPkg/MmcHostDxe/MmcHostDxe.h b/Omap44xxPkg/MmcHostDxe/MmcHostDxe.h new file mode 100755 index 000000000..4b9da8527 --- /dev/null +++ b/Omap44xxPkg/MmcHostDxe/MmcHostDxe.h @@ -0,0 +1,44 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef _MMC_HOST_DXE_H_ +#define _MMC_HOST_DXE_H_ + +#include <Uefi.h> + +#include <Library/BaseLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/DebugLib.h> +#include <Library/DevicePathLib.h> +#include <Library/IoLib.h> +#include <Library/PcdLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/OmapLib.h> +#include <Library/OmapDmaLib.h> +#include <Library/DmaLib.h> + +#include <Protocol/EmbeddedExternalDevice.h> +#include <Protocol/BlockIo.h> +#include <Protocol/DevicePath.h> +#include <Protocol/MmcHost.h> + +#include <Omap4430/Omap4430.h> +#include <TWL6030.h> + +#define MAX_RETRY_COUNT (100*5) + +extern EFI_BLOCK_IO_PROTOCOL gBlockIo; + +#endif diff --git a/Omap44xxPkg/MmcHostDxe/MmcHostDxe.inf b/Omap44xxPkg/MmcHostDxe/MmcHostDxe.inf new file mode 100755 index 000000000..72a498287 --- /dev/null +++ b/Omap44xxPkg/MmcHostDxe/MmcHostDxe.inf @@ -0,0 +1,53 @@ +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = MMC + FILE_GUID = 100c2cfa-b586-4198-9b4c-1683d195b1da + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = MMCInitialize + + +[Sources.common] + MmcHostDxe.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + PcdLib + UefiLib + UefiDriverEntryPoint + MemoryAllocationLib + IoLib + OmapDmaLib + DmaLib + +[Guids] + +[Protocols] + gEfiBlockIoProtocolGuid + gEfiCpuArchProtocolGuid + gEfiDevicePathProtocolGuid + gEmbeddedExternalDeviceProtocolGuid + gEfiMmcHostProtocolGuid + +[Pcd] + gOmap44xxTokenSpaceGuid.PcdOmap44xxMMCHS1Base + gOmap44xxTokenSpaceGuid.PcdMmchsTimerFreq100NanoSeconds + +[depex] + gEmbeddedExternalDeviceProtocolGuid diff --git a/Omap44xxPkg/Omap44xxPkg.dec b/Omap44xxPkg/Omap44xxPkg.dec new file mode 100644 index 000000000..4a2a47e20 --- /dev/null +++ b/Omap44xxPkg/Omap44xxPkg.dec @@ -0,0 +1,58 @@ +#/** @file +# Omap44xx SoC package. +# +# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = Omap44xxPkg + PACKAGE_GUID = D196A631-B7B7-4953-A3EE-0F773CBABF20 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ +[Includes.common] + Include # Root include for the package + +[LibraryClasses] + ## @libraryclass Abstract location of basic OMAP components + ## + OmapLib|Include/Library/OmapLib.h + + ## @libraryclass Abstract OMAP and ARM DMA, modeled after PCI IO protocol + ## + OmapDmaLib|Include/Library/OmapDmaLib.h + + +[Guids.common] + gOmap44xxTokenSpaceGuid = { 0x24b09abe, 0x4e47, 0x481c, { 0xa9, 0xad, 0xce, 0xf1, 0x2c, 0x39, 0x23, 0x27} } + +[PcdsFeatureFlag.common] + +[PcdsFixedAtBuild.common] + gOmap44xxTokenSpaceGuid.PcdOmap44xxConsoleUart|3|UINT32|0x00000202 + gOmap44xxTokenSpaceGuid.PcdOmap44xxGpmcOffset|0x00000000|UINT32|0x00000203 + gOmap44xxTokenSpaceGuid.PcdOmap44xxMMCHS1Base|0x00000000|UINT32|0x00000204 + gOmap44xxTokenSpaceGuid.PcdOmap44xxArchTimer|3|UINT32|0x00000205 + gOmap44xxTokenSpaceGuid.PcdOmap44xxFreeTimer|4|UINT32|0x00000206 + gOmap44xxTokenSpaceGuid.PcdOmap44xxDebugAgentTimer|5|UINT32|0x00000207 + gOmap44xxTokenSpaceGuid.PcdDebugAgentTimerFreqNanoSeconds|77|UINT32|0x00000208 + gOmap44xxTokenSpaceGuid.PcdMmchsTimerFreq100NanoSeconds|1000000|UINT32|0x00000209 + diff --git a/Omap44xxPkg/Omap44xxPkg.dsc b/Omap44xxPkg/Omap44xxPkg.dsc new file mode 100644 index 000000000..a7fa9375a --- /dev/null +++ b/Omap44xxPkg/Omap44xxPkg.dsc @@ -0,0 +1,183 @@ +#/** @file +# Omap44xx SoC package. +# +# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = Omap44xxPkg + PLATFORM_GUID = D196A631-B7B7-4953-A3EE-0F773CBABF20 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/Omap44xxPkg + SUPPORTED_ARCHITECTURES = ARM + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + DEFINE TARGET_HACK = DEBUG + + +[LibraryClasses.common] + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf + DefaultExceptioHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + + RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf + + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + OmapLib|Omap44xxPkg/Library/OmapLib/OmapLib.inf + OmapDmaLib|Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.inf + + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf + +# +# Assume everything is fixed at build +# + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + + # UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf + UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf + + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + + +[LibraryClasses.common.DXE_DRIVER] + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + + +[LibraryClasses.ARM] + # + # Note: This NULL library feature is not yet in theBaseTools, but it is checked in to + # the BaseTools project. So you need to build with the BaseTools project util this feature gets synced. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + +[BuildOptions] + XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7 + XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7 + XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv7 + + GCC:*_*_ARM_ARCHCC_FLAGS == -march=armv7-a -mthumb + GCC:*_*_ARM_ARCHASM_FLAGS == -march=armv7-a + + RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu 7-A + RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu 7-A + + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + + +[PcdsFixedAtBuild.common] + +# DEBUG_ASSERT_ENABLED 0x01 +# DEBUG_PRINT_ENABLED 0x02 +# DEBUG_CODE_ENABLED 0x04 +# CLEAR_MEMORY_ENABLED 0x08 +# ASSERT_BREAKPOINT_ENABLED 0x10 +# ASSERT_DEADLOOP_ENABLED 0x20 + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f + +# DEBUG_INIT 0x00000001 // Initialization +# DEBUG_WARN 0x00000002 // Warnings +# DEBUG_LOAD 0x00000004 // Load events +# DEBUG_FS 0x00000008 // EFI File system +# DEBUG_POOL 0x00000010 // Alloc & Free's +# DEBUG_PAGE 0x00000020 // Alloc & Free's +# DEBUG_INFO 0x00000040 // Verbose +# DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers +# DEBUG_VARIABLE 0x00000100 // Variable +# DEBUG_BM 0x00000400 // Boot Manager +# DEBUG_BLKIO 0x00001000 // BlkIo Driver +# DEBUG_NET 0x00004000 // SNI Driver +# DEBUG_UNDI 0x00010000 // UNDI Driver +# DEBUG_LOADFILE 0x00020000 // UNDI Driver +# DEBUG_EVENT 0x00080000 // Event messages +# DEBUG_ERROR 0x80000000 // Error + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000004 + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + + gEmbeddedTokenSpaceGuid.PcdPrePiTempMemorySize|0 + gEmbeddedTokenSpaceGuid.PcdPrePiBfvBaseAddress|0 + gEmbeddedTokenSpaceGuid.PcdPrePiBfvSize|0 + gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|0 + gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize|0 + gEmbeddedTokenSpaceGuid.PcdPrePiHobBase|0x80001000 + gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x87FE0000 # stack at top of memory + gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0x20000 # 128K stack + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80000000 + gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000 + + gOmap44xxTokenSpaceGuid.PcdOmap44xxGpmcOffset|0x50000000 + gOmap44xxTokenSpaceGuid.PcdOmap44xxMMCHS1Base|0x4809C000 + + # Console + gOmap44xxTokenSpaceGuid.PcdOmap44xxConsoleUart|3 + + # Timers + gOmap44xxTokenSpaceGuid.PcdOmap44xxArchTimer|3 + gOmap44xxTokenSpaceGuid.PcdOmap44xxFreeTimer|4 + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterPeriodInNanoseconds|26 + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|38400000 + + # + # ARM Pcds + # + gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + Omap44xxPkg/Library/Omap44xxTimerLib/Omap44xxTimerLib.inf + Omap44xxPkg/Library/OmapLib/OmapLib.inf + Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.inf + Omap44xxPkg/SmbusDxe/Smbus.inf + Omap44xxPkg/Gpio/Gpio.inf + Omap44xxPkg/TimerDxe/TimerDxe.inf + Omap44xxPkg/TPS65950Dxe/TPS65950.inf + + + diff --git a/Omap44xxPkg/PciEmulation/PciEmulation.c b/Omap44xxPkg/PciEmulation/PciEmulation.c new file mode 100644 index 000000000..5131394fa --- /dev/null +++ b/Omap44xxPkg/PciEmulation/PciEmulation.c @@ -0,0 +1,504 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PciEmulation.h" + +EMBEDDED_EXTERNAL_DEVICE *gTWL6030; + +#define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44 + +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + PCI_DEVICE_PATH PciDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_IO_DEVICE_PATH; + +typedef struct { + UINT32 Signature; + EFI_PCI_IO_DEVICE_PATH DevicePath; + EFI_PCI_IO_PROTOCOL PciIoProtocol; + PCI_TYPE00 *ConfigSpace; + PCI_ROOT_BRIDGE RootBridge; + UINTN Segment; +} EFI_PCI_IO_PRIVATE_DATA; + +#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', 'o') +#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE) + +EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate = +{ + { + { ACPI_DEVICE_PATH, ACPI_DP, { sizeof (ACPI_HID_DEVICE_PATH), 0 }}, + EISA_PNP_ID(0x0A03), // HID + 0 // UID + }, + { + { HARDWARE_DEVICE_PATH, HW_PCI_DP, { sizeof (PCI_DEVICE_PATH), 0 }}, + 0, + 0 + }, + { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}} +}; + +STATIC +VOID +ConfigureUSBHost ( + VOID + ) +{ + // Take USB host out of force-standby mode + MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_STANDBYMODE_NO_STANDBY + | UHH_SYSCONFIG_IDLEMODE_NO_IDLE); + MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT + | UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT + | UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE + | UHH_HOSTCONFIG_ENA_INCR16_ENABLE + | UHH_HOSTCONFIG_ENA_INCR8_ENABLE + | UHH_HOSTCONFIG_ENA_INCR4_ENABLE + | UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON + | UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE); + + // fref auxclk3 feeds USB3320 ULPI/DPDM converter with 19.2 MHz square clock + MmioWrite32 (SCRM_AUXCLK3, SCRM_AUXCLK3_VAL); + + // USB3320 and LAN9514 reset (HUB_NRESET: GPIO 62 - Port 2 pin 30 output high) + MmioAnd32 (GPIO2_BASE + GPIO_OE, ~BIT30); + MmioOr32 (GPIO2_BASE + GPIO_SETDATAOUT, BIT30); + + // Enable power to USB hub (HUB_NPD: GPIO1 - Port 1 pin 1 output high) + MmioAnd32 (GPIO1_BASE + GPIO_OE, ~BIT1); + MmioOr32 (GPIO1_BASE + GPIO_SETDATAOUT, BIT1); +} + +EFI_STATUS +PciIoPollMem ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoPollIo ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoMemRead ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This); + + return PciRootBridgeIoMemRead (&Private->RootBridge.Io, + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, + Private->ConfigSpace->Device.Bar[BarIndex] + Offset, + Count, + Buffer + ); +} + +EFI_STATUS +PciIoMemWrite ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This); + + return PciRootBridgeIoMemWrite (&Private->RootBridge.Io, + (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, + Private->ConfigSpace->Device.Bar[BarIndex] + Offset, + Count, + Buffer + ); +} + +EFI_STATUS +PciIoIoRead ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoIoWrite ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 BarIndex, + IN UINT64 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoPciRead ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT32 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This); + + return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width, + Count, + TRUE, + (PTR)(UINTN)Buffer, + TRUE, + (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset) + ); +} + +EFI_STATUS +PciIoPciWrite ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT32 Offset, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This); + + return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width, + Count, + TRUE, + (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset), + TRUE, + (PTR)(UINTN)Buffer + ); +} + +EFI_STATUS +PciIoCopyMem ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_WIDTH Width, + IN UINT8 DestBarIndex, + IN UINT64 DestOffset, + IN UINT8 SrcBarIndex, + IN UINT64 SrcOffset, + IN UINTN Count + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoMap ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ) +{ + DMA_MAP_OPERATION DmaOperation; + + if (Operation == EfiPciIoOperationBusMasterRead) { + DmaOperation = MapOperationBusMasterRead; + } else if (Operation == EfiPciIoOperationBusMasterWrite) { + DmaOperation = MapOperationBusMasterWrite; + } else if (Operation == EfiPciIoOperationBusMasterCommonBuffer) { + DmaOperation = MapOperationBusMasterCommonBuffer; + } else { + return EFI_INVALID_PARAMETER; + } + return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping); +} + +EFI_STATUS +PciIoUnmap ( + IN EFI_PCI_IO_PROTOCOL *This, + IN VOID *Mapping + ) +{ + return DmaUnmap (Mapping); +} + +EFI_STATUS +PciIoAllocateBuffer ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT VOID **HostAddress, + IN UINT64 Attributes + ) +{ + if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) { + // Check this + return EFI_UNSUPPORTED; + } + + return DmaAllocateBuffer (MemoryType, Pages, HostAddress); +} + + +EFI_STATUS +PciIoFreeBuffer ( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINTN Pages, + IN VOID *HostAddress + ) +{ + return DmaFreeBuffer (Pages, HostAddress); +} + + +EFI_STATUS +PciIoFlush ( + IN EFI_PCI_IO_PROTOCOL *This + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +PciIoGetLocation ( + IN EFI_PCI_IO_PROTOCOL *This, + OUT UINTN *SegmentNumber, + OUT UINTN *BusNumber, + OUT UINTN *DeviceNumber, + OUT UINTN *FunctionNumber + ) +{ + EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This); + + if (SegmentNumber != NULL) { + *SegmentNumber = Private->Segment; + } + + if (BusNumber != NULL) { + *BusNumber = 0xff; + } + + if (DeviceNumber != NULL) { + *DeviceNumber = 0; + } + + if (FunctionNumber != NULL) { + *FunctionNumber = 0; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +PciIoAttributes ( + IN EFI_PCI_IO_PROTOCOL *This, + IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation, + IN UINT64 Attributes, + OUT UINT64 *Result OPTIONAL + ) +{ + switch (Operation) { + case EfiPciIoAttributeOperationGet: + case EfiPciIoAttributeOperationSupported: + if (Result == NULL) { + return EFI_INVALID_PARAMETER; + } + // We are not a real PCI device so just say things we kind of do + *Result = EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER | EFI_PCI_DEVICE_ENABLE; + break; + + case EfiPciIoAttributeOperationSet: + case EfiPciIoAttributeOperationEnable: + case EfiPciIoAttributeOperationDisable: + // Since we are not a real PCI device no enable/set or disable operations exist. + return EFI_SUCCESS; + + default: + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + }; + return EFI_SUCCESS; +} + +EFI_STATUS +PciIoGetBarAttributes ( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINT8 BarIndex, + OUT UINT64 *Supports, OPTIONAL + OUT VOID **Resources OPTIONAL + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_STATUS +PciIoSetBarAttributes ( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINT64 Attributes, + IN UINT8 BarIndex, + IN OUT UINT64 *Offset, + IN OUT UINT64 *Length + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +EFI_PCI_IO_PROTOCOL PciIoTemplate = +{ + PciIoPollMem, + PciIoPollIo, + { + PciIoMemRead, + PciIoMemWrite + }, + { + PciIoIoRead, + PciIoIoWrite + }, + { + PciIoPciRead, + PciIoPciWrite + }, + PciIoCopyMem, + PciIoMap, + PciIoUnmap, + PciIoAllocateBuffer, + PciIoFreeBuffer, + PciIoFlush, + PciIoGetLocation, + PciIoAttributes, + PciIoGetBarAttributes, + PciIoSetBarAttributes, + 0, + 0 +}; + +EFI_STATUS +EFIAPI +PciEmulationEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + EFI_PCI_IO_PRIVATE_DATA *Private; + UINT8 CapabilityLength; + UINT8 PhysicalPorts; + UINTN Count; + + //Configure USB host for OMAP4430. + ConfigureUSBHost(); + + // Create a private structure + Private = AllocatePool(sizeof(EFI_PCI_IO_PRIVATE_DATA)); + if (Private == NULL) { + Status = EFI_OUT_OF_RESOURCES; + return Status; + } + + Private->Signature = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; // Fill in signature + Private->RootBridge.Signature = PCI_ROOT_BRIDGE_SIGNATURE; // Fake Root Bridge structure needs a signature too + Private->RootBridge.MemoryStart = USB_EHCI_HCCAPBASE; // Get the USB capability register base + Private->Segment = 0; // Default to segment zero + + // Find out the capability register length and number of physical ports. + CapabilityLength = MmioRead8(Private->RootBridge.MemoryStart); + PhysicalPorts = (MmioRead32 (Private->RootBridge.MemoryStart + 0x4)) & 0x0000000F; + + // Calculate the total size of the USB registers. + Private->RootBridge.MemorySize = CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1)); + + // Enable Port Power bit in Port status and control registers in EHCI register space. + // Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates + // host controller implementation includes port power control. + for (Count = 0; Count < PhysicalPorts; Count++) { + MmioOr32 ((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000); + } + + // Create fake PCI config space. + Private->ConfigSpace = AllocateZeroPool(sizeof(PCI_TYPE00)); + if (Private->ConfigSpace == NULL) { + Status = EFI_OUT_OF_RESOURCES; + FreePool(Private); + return Status; + } + + // Configure PCI config space + Private->ConfigSpace->Hdr.VendorId = 0x3530; + Private->ConfigSpace->Hdr.DeviceId = 0x3530; + Private->ConfigSpace->Hdr.ClassCode[0] = 0x20; + Private->ConfigSpace->Hdr.ClassCode[1] = 0x03; + Private->ConfigSpace->Hdr.ClassCode[2] = 0x0C; + Private->ConfigSpace->Device.Bar[0] = Private->RootBridge.MemoryStart; + + Handle = NULL; + + // Unique device path. + CopyMem(&Private->DevicePath, &PciIoDevicePathTemplate, sizeof(PciIoDevicePathTemplate)); + Private->DevicePath.AcpiDevicePath.UID = 0; + + // Copy protocol structure + CopyMem(&Private->PciIoProtocol, &PciIoTemplate, sizeof(PciIoTemplate)); + + Status = gBS->InstallMultipleProtocolInterfaces(&Handle, + &gEfiPciIoProtocolGuid, &Private->PciIoProtocol, + &gEfiDevicePathProtocolGuid, &Private->DevicePath, + NULL); + if (EFI_ERROR(Status)) { + DEBUG((EFI_D_ERROR, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces() failed.\n")); + } + + return Status; +} + diff --git a/Omap44xxPkg/PciEmulation/PciEmulation.h b/Omap44xxPkg/PciEmulation/PciEmulation.h new file mode 100644 index 000000000..ba719e1db --- /dev/null +++ b/Omap44xxPkg/PciEmulation/PciEmulation.h @@ -0,0 +1,292 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCI_ROOT_BRIDGE_H_ +#define _PCI_ROOT_BRIDGE_H_ + +#include <PiDxe.h> + +#include <TWL6030.h> + +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/DxeServicesTableLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PciLib.h> +#include <Library/UefiLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/OmapDmaLib.h> +#include <Library/DmaLib.h> + +#include <Protocol/EmbeddedExternalDevice.h> +#include <Protocol/DevicePath.h> +#include <Protocol/PciIo.h> +#include <Protocol/PciRootBridgeIo.h> +#include <Protocol/PciHostBridgeResourceAllocation.h> + +#include <IndustryStandard/Pci22.h> +#include <IndustryStandard/Acpi.h> + +#include <Omap4430/Omap4430.h> + + + +#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL +#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL +#define EFI_RESOURCE_SATISFIED 0x0000000000000000ULL + + +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; + + +#define ACPI_CONFIG_IO 0 +#define ACPI_CONFIG_MMIO 1 +#define ACPI_CONFIG_BUS 2 + +typedef struct { + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR Desc[3]; + EFI_ACPI_END_TAG_DESCRIPTOR EndDesc; +} ACPI_CONFIG_INFO; + + +#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32 ('P', 'c', 'i', 'F') + +typedef struct { + UINT32 Signature; + EFI_HANDLE Handle; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; + EFI_PCI_ROOT_BRIDGE_DEVICE_PATH DevicePath; + + UINT8 StartBus; + UINT8 EndBus; + UINT16 Type; + UINT32 MemoryStart; + UINT32 MemorySize; + UINTN IoOffset; + UINT32 IoStart; + UINT32 IoSize; + UINT64 PciAttributes; + + ACPI_CONFIG_INFO *Config; + +} PCI_ROOT_BRIDGE; + + +#define INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) CR (a, PCI_ROOT_BRIDGE, Io, PCI_ROOT_BRIDGE_SIGNATURE) + + +typedef union { + UINT8 volatile *buf; + UINT8 volatile *ui8; + UINT16 volatile *ui16; + UINT32 volatile *ui32; + UINT64 volatile *ui64; + UINTN volatile ui; +} PTR; + + + +EFI_STATUS +EFIAPI +PciRootBridgeIoPollMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoPollIo ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoMemRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoMemWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoIoRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN OUT VOID *UserBuffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoIoWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN OUT VOID *UserBuffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoCopyMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 DestAddress, + IN UINT64 SrcAddress, + IN UINTN Count + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoPciRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoPciWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoMap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoUnmap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN VOID *Mapping + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoAllocateBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT VOID **HostAddress, + IN UINT64 Attributes + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoFreeBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINTN Pages, + OUT VOID *HostAddress + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoFlush ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoGetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT UINT64 *Supported, + OUT UINT64 *Attributes + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoSetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINT64 Attributes, + IN OUT UINT64 *ResourceBase, + IN OUT UINT64 *ResourceLength + ); + +EFI_STATUS +EFIAPI +PciRootBridgeIoConfiguration ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT VOID **Resources + ); + +// +// Private Function Prototypes +// +EFI_STATUS +EFIAPI +PciRootBridgeIoMemRW ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINTN Count, + IN BOOLEAN InStrideFlag, + IN PTR In, + IN BOOLEAN OutStrideFlag, + OUT PTR Out + ); + +BOOLEAN +PciIoMemAddressValid ( + IN EFI_PCI_IO_PROTOCOL *This, + IN UINT64 Address + ); + +EFI_STATUS +EmulatePciIoForEhci ( + INTN MvPciIfMaxIf + ); + +#endif + diff --git a/Omap44xxPkg/PciEmulation/PciEmulation.inf b/Omap44xxPkg/PciEmulation/PciEmulation.inf new file mode 100644 index 000000000..5907d9808 --- /dev/null +++ b/Omap44xxPkg/PciEmulation/PciEmulation.inf @@ -0,0 +1,57 @@ +/** @file + + Copyright (c) 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardPciEmulation + FILE_GUID = feaa2e2b-53ac-4d5e-ae10-1efd5da4a2ba + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = PciEmulationEntryPoint + +[Sources.common] + PciRootBridgeIo.c + PciEmulation.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFrameworkPkg/IntelFrameworkPkg.dec + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + BaseLib + DxeServicesTableLib + UefiLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + IoLib + OmapDmaLib + DmaLib + +[Protocols] + gEfiPciRootBridgeIoProtocolGuid + gEfiDevicePathProtocolGuid + gEfiPciHostBridgeResourceAllocationProtocolGuid + gEfiPciIoProtocolGuid + gEmbeddedExternalDeviceProtocolGuid + +[Depex] + gEfiMetronomeArchProtocolGuid AND + gEmbeddedExternalDeviceProtocolGuid +
\ No newline at end of file diff --git a/Omap44xxPkg/PciEmulation/PciRootBridgeIo.c b/Omap44xxPkg/PciEmulation/PciRootBridgeIo.c new file mode 100644 index 000000000..2f5b1aa1d --- /dev/null +++ b/Omap44xxPkg/PciEmulation/PciRootBridgeIo.c @@ -0,0 +1,306 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PciEmulation.h" + +BOOLEAN +PciRootBridgeMemAddressValid ( + IN PCI_ROOT_BRIDGE *Private, + IN UINT64 Address + ) +{ + if ((Address >= Private->MemoryStart) && (Address < (Private->MemoryStart + Private->MemorySize))) { + return TRUE; + } + + return FALSE; +} + + +EFI_STATUS +PciRootBridgeIoMemRW ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINTN Count, + IN BOOLEAN InStrideFlag, + IN PTR In, + IN BOOLEAN OutStrideFlag, + OUT PTR Out + ) +{ + UINTN Stride; + UINTN InStride; + UINTN OutStride; + + + Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03); + Stride = (UINTN)1 << Width; + InStride = InStrideFlag ? Stride : 0; + OutStride = OutStrideFlag ? Stride : 0; + + // + // Loop for each iteration and move the data + // + switch (Width) { + case EfiPciWidthUint8: + for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) { + *In.ui8 = *Out.ui8; + } + break; + case EfiPciWidthUint16: + for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) { + *In.ui16 = *Out.ui16; + } + break; + case EfiPciWidthUint32: + for (;Count > 0; Count--, In.buf += InStride, Out.buf += OutStride) { + *In.ui32 = *Out.ui32; + } + break; + default: + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +PciRootBridgeIoPciRW ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN BOOLEAN Write, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN OUT VOID *UserBuffer + ) +{ + return EFI_SUCCESS; +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the memory operations. + @param Address The base address of the memory operations. + @param Count The number of memory operations to perform. + @param Buffer For read operations, the destination buffer to store the results. For write + operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +EFI_STATUS +EFIAPI +PciRootBridgeIoMemRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + PCI_ROOT_BRIDGE *Private; + UINTN AlignMask; + PTR In; + PTR Out; + + if ( Buffer == NULL ) { + return EFI_INVALID_PARAMETER; + } + + Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + if (!PciRootBridgeMemAddressValid (Private, Address)) { + return EFI_INVALID_PARAMETER; + } + + AlignMask = (1 << (Width & 0x03)) - 1; + if (Address & AlignMask) { + return EFI_INVALID_PARAMETER; + } + + In.buf = Buffer; + Out.buf = (VOID *)(UINTN) Address; + + switch (Width) { + case EfiPciWidthUint8: + case EfiPciWidthUint16: + case EfiPciWidthUint32: + case EfiPciWidthUint64: + return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out); + + case EfiPciWidthFifoUint8: + case EfiPciWidthFifoUint16: + case EfiPciWidthFifoUint32: + case EfiPciWidthFifoUint64: + return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out); + + case EfiPciWidthFillUint8: + case EfiPciWidthFillUint16: + case EfiPciWidthFillUint32: + case EfiPciWidthFillUint64: + return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out); + + default: + break; + } + + return EFI_INVALID_PARAMETER; +} + + + +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the memory operations. + @param Address The base address of the memory operations. + @param Count The number of memory operations to perform. + @param Buffer For read operations, the destination buffer to store the results. For write + operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +EFI_STATUS +EFIAPI +PciRootBridgeIoMemWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + PCI_ROOT_BRIDGE *Private; + UINTN AlignMask; + PTR In; + PTR Out; + + if ( Buffer == NULL ) { + return EFI_INVALID_PARAMETER; + } + + Private = INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + if (!PciRootBridgeMemAddressValid (Private, Address)) { + return EFI_INVALID_PARAMETER; + } + + AlignMask = (1 << (Width & 0x03)) - 1; + if (Address & AlignMask) { + return EFI_INVALID_PARAMETER; + } + + In.buf = (VOID *)(UINTN) Address; + Out.buf = Buffer; + + switch (Width) { + case EfiPciWidthUint8: + case EfiPciWidthUint16: + case EfiPciWidthUint32: + case EfiPciWidthUint64: + return PciRootBridgeIoMemRW (Width, Count, TRUE, In, TRUE, Out); + + case EfiPciWidthFifoUint8: + case EfiPciWidthFifoUint16: + case EfiPciWidthFifoUint32: + case EfiPciWidthFifoUint64: + return PciRootBridgeIoMemRW (Width, Count, FALSE, In, TRUE, Out); + + case EfiPciWidthFillUint8: + case EfiPciWidthFillUint16: + case EfiPciWidthFillUint32: + case EfiPciWidthFillUint64: + return PciRootBridgeIoMemRW (Width, Count, TRUE, In, FALSE, Out); + + default: + break; + } + + return EFI_INVALID_PARAMETER; +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the memory operations. + @param Address The base address of the memory operations. + @param Count The number of memory operations to perform. + @param Buffer For read operations, the destination buffer to store the results. For write + operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +EFI_STATUS +EFIAPI +PciRootBridgeIoPciRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + return PciRootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer); +} + + + +/** + Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Width Signifies the width of the memory operations. + @param Address The base address of the memory operations. + @param Count The number of memory operations to perform. + @param Buffer For read operations, the destination buffer to store the results. For write + operations, the source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the PCI root bridge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + +**/ +EFI_STATUS +EFIAPI +PciRootBridgeIoPciWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + if (Buffer == NULL) { + return EFI_INVALID_PARAMETER; + } + + return PciRootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer); +} + + diff --git a/Omap44xxPkg/SmbusDxe/Smbus.c b/Omap44xxPkg/SmbusDxe/Smbus.c new file mode 100644 index 000000000..bed5121e4 --- /dev/null +++ b/Omap44xxPkg/SmbusDxe/Smbus.c @@ -0,0 +1,325 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Uefi.h> +#include <Omap4430/Omap4430.h> + +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <Protocol/SmbusHc.h> + +#define MAX_RETRY 1000 + +// +// Internal Functions +// +STATIC +EFI_STATUS +WaitForBusBusy ( + VOID + ) +{ + UINTN Retry = 0; + + while (++Retry < MAX_RETRY && (MmioRead16(I2C_STAT) & BB) == 0x1); + + if (Retry == MAX_RETRY) { + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +PollForStatus( + UINT16 StatusBit + ) +{ + UINTN Retry = 0; + + while(Retry < MAX_RETRY) { + if (MmioRead16(I2C_STAT) & StatusBit) { + //Clear particular status bit from Status register. + MmioOr16(I2C_STAT, StatusBit); + break; + } + Retry++; + } + + if (Retry == MAX_RETRY) { + return EFI_TIMEOUT; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +ConfigureI2c ( + VOID + ) +{ + //Program prescaler to obtain 12-MHz clock + MmioWrite16(I2C_PSC, 0x0000); + + //Program SCLL and SCLH + //NOTE: Following values are the register dump after U-Boot code executed. + //We need to figure out how its calculated based on the I2C functional clock and I2C_PSC. + MmioWrite16(I2C_SCLL, 0x0035); + MmioWrite16(I2C_SCLH, 0x0035); + + //Take the I2C controller out of reset. + MmioOr16(I2C_CON, I2C_EN); + + //Initialize the I2C controller. + + //Set I2C controller in Master mode. + MmioOr16(I2C_CON, MST); + + //Enable interrupts for receive/transmit mode. + MmioOr16(I2C_IE, (XRDY_IE | RRDY_IE | ARDY_IE | NACK_IE)); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +I2CReadOneByte ( + UINT8 *Data + ) +{ + EFI_STATUS Status; + + //I2C bus status checking + Status = WaitForBusBusy(); + if (EFI_ERROR(Status)) { + return Status; + } + + //Poll till Receive ready bit is set. + Status = PollForStatus(RRDY); + if (EFI_ERROR(Status)) { + return Status; + } + + *Data = MmioRead8(I2C_DATA); + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +I2CWriteOneByte ( + UINT8 Data + ) +{ + EFI_STATUS Status; + + //I2C bus status checking + Status = WaitForBusBusy(); + if (EFI_ERROR(Status)) { + return Status; + } + + //Data transfer + //Poll till Transmit ready bit is set + Status = PollForStatus(XRDY); + if (EFI_ERROR(Status)) { + return Status; + } + + MmioWrite8(I2C_DATA, Data); + + //Wait and check if the NACK is not set. + gBS->Stall(1000); + if (MmioRead16(I2C_STAT) & NACK) { + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +SmbusBlockRead ( + OUT UINT8 *Buffer, + IN UINTN Length + ) +{ + UINTN Index = 0; + EFI_STATUS Status = EFI_SUCCESS; + + //Transfer configuration for receiving data. + MmioWrite16(I2C_CNT, Length); + //Need stop bit before sending data. + MmioWrite16(I2C_CON, (I2C_EN | MST | STP | STT)); + + while (Index < Length) { + //Read a byte + Status = I2CReadOneByte(&Buffer[Index++]); + if (EFI_ERROR(Status)) { + return Status; + } + } + + //Transfer completion + Status = PollForStatus(ARDY); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} + +STATIC +EFI_STATUS +SmbusBlockWrite ( + IN UINT8 *Buffer, + IN UINTN Length + ) +{ + UINTN Index = 0; + EFI_STATUS Status = EFI_SUCCESS; + + //Transfer configuration for transmitting data + MmioWrite16(I2C_CNT, Length); + MmioWrite16(I2C_CON, (I2C_EN | TRX | MST | STT | STP)); + + while (Index < Length) { + //Send a byte + Status = I2CWriteOneByte(Buffer[Index++]); + if (EFI_ERROR(Status)) { + return Status; + } + } + + //Transfer completion + Status = PollForStatus(ARDY); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} + +// +// Public Functions. +// +EFI_STATUS +EFIAPI +SmbusExecute ( + IN CONST EFI_SMBUS_HC_PROTOCOL *This, + IN CONST EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN CONST EFI_SMBUS_DEVICE_COMMAND Command, + IN CONST EFI_SMBUS_OPERATION Operation, + IN CONST BOOLEAN PecCheck, + IN OUT UINTN *Length, + IN OUT VOID *Buffer + ) +{ + UINT8 *ByteBuffer = Buffer; + EFI_STATUS Status = EFI_SUCCESS; + UINT8 SlaveAddr = (UINT8)(SlaveAddress.SmbusDeviceAddress); + + if (PecCheck) { + return EFI_UNSUPPORTED; + } + + if ((Operation != EfiSmbusWriteBlock) && (Operation != EfiSmbusReadBlock)) { + return EFI_UNSUPPORTED; + } + + //Set the Slave address. + MmioWrite16(I2C_SA, SlaveAddr); + + if (Operation == EfiSmbusReadBlock) { + Status = SmbusBlockRead(ByteBuffer, *Length); + } else if (Operation == EfiSmbusWriteBlock) { + Status = SmbusBlockWrite(ByteBuffer, *Length); + } + + return Status; +} + +EFI_STATUS +EFIAPI +SmbusArpDevice ( + IN CONST EFI_SMBUS_HC_PROTOCOL *This, + IN BOOLEAN ArpAll, + IN EFI_SMBUS_UDID *SmbusUdid OPTIONAL, + IN OUT EFI_SMBUS_DEVICE_ADDRESS *SlaveAddress OPTIONAL + ) +{ + return EFI_UNSUPPORTED; +} + + +EFI_STATUS +EFIAPI +SmbusGetArpMap ( + IN CONST EFI_SMBUS_HC_PROTOCOL *This, + IN OUT UINTN *Length, + IN OUT EFI_SMBUS_DEVICE_MAP **SmbusDeviceMap + ) +{ + return EFI_UNSUPPORTED; +} + + +EFI_STATUS +EFIAPI +SmbusNotify ( + IN CONST EFI_SMBUS_HC_PROTOCOL *This, + IN CONST EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN CONST UINTN Data, + IN CONST EFI_SMBUS_NOTIFY_FUNCTION NotifyFunction + ) +{ + return EFI_UNSUPPORTED; +} + +EFI_SMBUS_HC_PROTOCOL SmbusProtocol = +{ + SmbusExecute, + SmbusArpDevice, + SmbusGetArpMap, + SmbusNotify +}; + +EFI_STATUS +InitializeSmbus ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_HANDLE Handle = NULL; + EFI_STATUS Status; + + //Configure I2C controller. + Status = ConfigureI2c(); + if (EFI_ERROR(Status)) { + DEBUG ((EFI_D_ERROR, "InitializeI2c fails.\n")); + return Status; + } + + // Install the SMBUS interface + Status = gBS->InstallMultipleProtocolInterfaces(&Handle, &gEfiSmbusHcProtocolGuid, &SmbusProtocol, NULL); + ASSERT_EFI_ERROR(Status); + + return Status; +} + diff --git a/Omap44xxPkg/SmbusDxe/Smbus.inf b/Omap44xxPkg/SmbusDxe/Smbus.inf new file mode 100644 index 000000000..b1000501d --- /dev/null +++ b/Omap44xxPkg/SmbusDxe/Smbus.inf @@ -0,0 +1,45 @@ +#/** @file +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = Smbus + FILE_GUID = d5125e0f-1226-444f-a218-0085996ed5da + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = InitializeSmbus + +[Sources.common] + Smbus.c + +[Packages] + MdePkg/MdePkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + PcdLib + UefiLib + UefiDriverEntryPoint + MemoryAllocationLib + IoLib + +[Guids] + +[Protocols] + gEfiSmbusHcProtocolGuid + +[Pcd] + +[depex] + TRUE
\ No newline at end of file diff --git a/Omap44xxPkg/TWL6030Dxe/TWL6030.c b/Omap44xxPkg/TWL6030Dxe/TWL6030.c new file mode 100644 index 000000000..f4027bfa8 --- /dev/null +++ b/Omap44xxPkg/TWL6030Dxe/TWL6030.c @@ -0,0 +1,116 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Uefi.h> + +#include <TWL6030.h> + +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <Protocol/EmbeddedExternalDevice.h> +#include <Protocol/SmbusHc.h> + +EFI_SMBUS_HC_PROTOCOL *Smbus; + +EFI_STATUS +Read ( + IN EMBEDDED_EXTERNAL_DEVICE *This, + IN UINTN Register, + IN UINTN Length, + OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + UINT8 DeviceRegister; + UINTN DeviceRegisterLength = 1; + + SlaveAddress.SmbusDeviceAddress = EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(Register); + DeviceRegister = (UINT8)EXTERNAL_DEVICE_REGISTER_TO_REGISTER(Register); + + //Write DeviceRegister. + Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusWriteBlock, FALSE, &DeviceRegisterLength, &DeviceRegister); + if (EFI_ERROR(Status)) { + return Status; + } + + //Read Data + Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusReadBlock, FALSE, &Length, Buffer); + return Status; +} + +EFI_STATUS +Write ( + IN EMBEDDED_EXTERNAL_DEVICE *This, + IN UINTN Register, + IN UINTN Length, + IN VOID *Buffer + ) +{ + EFI_STATUS Status; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + UINT8 DeviceRegister; + UINTN DeviceBufferLength = Length + 1; + UINT8 *DeviceBuffer; + + SlaveAddress.SmbusDeviceAddress = EXTERNAL_DEVICE_REGISTER_TO_SLAVE_ADDRESS(Register); + DeviceRegister = (UINT8)EXTERNAL_DEVICE_REGISTER_TO_REGISTER(Register); + + //Prepare buffer for writing + DeviceBuffer = (UINT8 *)AllocatePool(DeviceBufferLength); + if (DeviceBuffer == NULL) { + Status = EFI_OUT_OF_RESOURCES; + goto exit; + } + + //Set Device register followed by data to write. + DeviceBuffer[0] = DeviceRegister; + CopyMem(&DeviceBuffer[1], Buffer, Length); + + //Write Data + Status = Smbus->Execute(Smbus, SlaveAddress, 0, EfiSmbusWriteBlock, FALSE, &DeviceBufferLength, DeviceBuffer); + if (EFI_ERROR(Status)) { + goto exit; + } + +exit: + if (DeviceBuffer) { + FreePool(DeviceBuffer); + } + + return Status; +} + +EMBEDDED_EXTERNAL_DEVICE ExternalDevice = { + Read, + Write +}; + +EFI_STATUS +TWL6030Initialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = gBS->LocateProtocol(&gEfiSmbusHcProtocolGuid, NULL, (VOID **)&Smbus); + ASSERT_EFI_ERROR(Status); + + Status = gBS->InstallMultipleProtocolInterfaces(&ImageHandle, &gEmbeddedExternalDeviceProtocolGuid, &ExternalDevice, NULL); + return Status; +} diff --git a/Omap44xxPkg/TWL6030Dxe/TWL6030.inf b/Omap44xxPkg/TWL6030Dxe/TWL6030.inf new file mode 100644 index 000000000..a539bfaae --- /dev/null +++ b/Omap44xxPkg/TWL6030Dxe/TWL6030.inf @@ -0,0 +1,48 @@ +#/** @file +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = TWL6030 + FILE_GUID = 71fe861a-5450-48b6-bfb0-b93522616f99 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = TWL6030Initialize + + +[Sources.common] + TWL6030.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + BaseMemoryLib + PcdLib + UefiLib + UefiDriverEntryPoint + MemoryAllocationLib + +[Guids] + +[Protocols] + gEfiSmbusHcProtocolGuid + gEmbeddedExternalDeviceProtocolGuid + +[Pcd] + +[depex] + gEfiSmbusHcProtocolGuid diff --git a/Omap44xxPkg/TimerDxe/Timer.c b/Omap44xxPkg/TimerDxe/Timer.c new file mode 100644 index 000000000..e297f0ce9 --- /dev/null +++ b/Omap44xxPkg/TimerDxe/Timer.c @@ -0,0 +1,373 @@ +/** @file + Template for Timer Architecture Protocol driver of the ARM flavor + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +#include <PiDxe.h> + +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/OmapLib.h> + +#include <Protocol/Timer.h> +#include <Protocol/HardwareInterrupt.h> + +#include <Omap4430/Omap4430.h> + + +// The notification function to call on every timer interrupt. +volatile EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL; + + +// The current period of the timer interrupt +volatile UINT64 mTimerPeriod = 0; + +// Cached copy of the Hardware Interrupt protocol instance +EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL; + +// Cached registers +volatile UINT32 TISR; +volatile UINT32 TCLR; +volatile UINT32 TLDR; +volatile UINT32 TCRR; +volatile UINT32 TIER; + +// Cached interrupt vector +volatile UINTN gVector; + + +/** + + C Interrupt Handler calledin the interrupt context when Source interrupt is active. + + + @param Source Source of the interrupt. Hardware routing off a specific platform defines + what source means. + + @param SystemContext Pointer to system register context. Mostly used by debuggers and will + update the system context after the return from the interrupt if + modified. Don't change these values unless you know what you are doing + +**/ +VOID +EFIAPI +TimerInterruptHandler ( + IN HARDWARE_INTERRUPT_SOURCE Source, + IN EFI_SYSTEM_CONTEXT SystemContext + ) +{ + EFI_TPL OriginalTPL; + + + + // + // DXE core uses this callback for the EFI timer tick. The DXE core uses locks + // that raise to TPL_HIGH and then restore back to current level. Thus we need + // to make sure TPL level is set to TPL_HIGH while we are handling the timer tick. + // + OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL); + + if (mTimerNotifyFunction) { + mTimerNotifyFunction(mTimerPeriod); + } + + // Clear all timer interrupts + MmioWrite32 (TISR, TISR_CLEAR_ALL); + + // Poll interrupt status bits to ensure clearing + while ((MmioRead32 (TISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING); + + gBS->RestoreTPL (OriginalTPL); +} + +/** + This function registers the handler NotifyFunction so it is called every time + the timer interrupt fires. It also passes the amount of time since the last + handler call to the NotifyFunction. If NotifyFunction is NULL, then the + handler is unregistered. If the handler is registered, then EFI_SUCCESS is + returned. If the CPU does not support registering a timer interrupt handler, + then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler + when a handler is already registered, then EFI_ALREADY_STARTED is returned. + If an attempt is made to unregister a handler when a handler is not registered, + then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to + register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR + is returned. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The function to call when a timer interrupt fires. This + function executes at TPL_HIGH_LEVEL. The DXE Core will + register a handler for the timer interrupt, so it can know + how much time has passed. This information is used to + signal timer based events. NULL will unregister the handler. + @retval EFI_SUCCESS The timer handler was registered. + @retval EFI_UNSUPPORTED The platform does not support timer interrupts. + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a handler is already + registered. + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a handler was not + previously registered. + @retval EFI_DEVICE_ERROR The timer handler could not be registered. + +**/ +EFI_STATUS +EFIAPI +TimerDriverRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction + ) +{ + if ((NotifyFunction == NULL) && (mTimerNotifyFunction == NULL)) { + return EFI_INVALID_PARAMETER; + } + + if ((NotifyFunction != NULL) && (mTimerNotifyFunction != NULL)) { + return EFI_ALREADY_STARTED; + } + + mTimerNotifyFunction = NotifyFunction; + + return EFI_SUCCESS; +} + +/** + + This function adjusts the period of timer interrupts to the value specified + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust the + interrupt controller so that a CPU interrupt is not generated when the timer + interrupt fires. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 nS units. If + the timer hardware is not programmable, then EFI_UNSUPPORTED is + returned. If the timer is programmable, then the timer period + will be rounded up to the nearest timer period that is supported + by the timer hardware. If TimerPeriod is set to 0, then the + timer interrupts will be disabled. + + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period of the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed due to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverSetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ) +{ + EFI_STATUS Status; + UINT64 TimerCount; + INT32 LoadValue; + + if (TimerPeriod == 0) { + // Turn off GPTIMER3 + MmioWrite32 (TCLR, TCLR_ST_OFF); + + Status = gInterrupt->DisableInterruptSource(gInterrupt, gVector); + } else { + // Calculate required timer count + TimerCount = DivU64x32(TimerPeriod * 100, PcdGet32(PcdEmbeddedPerformanceCounterPeriodInNanoseconds)); + + // Set GPTIMER3 Load register + LoadValue = (INT32) -TimerCount; + MmioWrite32 (TLDR, LoadValue); + MmioWrite32 (TCRR, LoadValue); + + // Enable Overflow interrupt + MmioWrite32 (TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE); + + // Turn on GPTIMER3, it will reload at overflow + MmioWrite32 (TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON); + + Status = gInterrupt->EnableInterruptSource(gInterrupt, gVector); + } + + // + // Save the new timer period + // + mTimerPeriod = TimerPeriod; + return Status; +} + + +/** + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is + returned, then the timer is currently disabled. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 ns units. If + 0 is returned, then the timer is currently disabled. + + + @retval EFI_SUCCESS The timer period was returned in TimerPeriod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +{ + if (TimerPeriod == NULL) { + return EFI_INVALID_PARAMETER; + } + + *TimerPeriod = mTimerPeriod; + return EFI_SUCCESS; +} + +/** + This function generates a soft timer interrupt. If the platform does not support soft + timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned. + If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler() + service, then a soft timer interrupt will be generated. If the timer interrupt is + enabled when this service is called, then the registered handler will be invoked. The + registered handler should not be able to distinguish a hardware-generated timer + interrupt from a software-generated timer interrupt. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS The soft timer interrupt was generated. + @retval EFI_UNSUPPORTED The platform does not support the generation of soft timer interrupts. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGenerateSoftInterrupt ( + IN EFI_TIMER_ARCH_PROTOCOL *This + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + Interface stucture for the Timer Architectural Protocol. + + @par Protocol Description: + This protocol provides the services to initialize a periodic timer + interrupt, and to register a handler that is called each time the timer + interrupt fires. It may also provide a service to adjust the rate of the + periodic timer interrupt. When a timer interrupt occurs, the handler is + passed the amount of time that has passed since the previous timer + interrupt. + + @param RegisterHandler + Registers a handler that will be called each time the + timer interrupt fires. TimerPeriod defines the minimum + time between timer interrupts, so TimerPeriod will also + be the minimum time between calls to the registered + handler. + + @param SetTimerPeriod + Sets the period of the timer interrupt in 100 nS units. + This function is optional, and may return EFI_UNSUPPORTED. + If this function is supported, then the timer period will + be rounded up to the nearest supported timer period. + + + @param GetTimerPeriod + Retrieves the period of the timer interrupt in 100 nS units. + + @param GenerateSoftInterrupt + Generates a soft timer interrupt that simulates the firing of + the timer interrupt. This service can be used to invoke the registered handler if the timer interrupt has been masked for + a period of time. + +**/ +EFI_TIMER_ARCH_PROTOCOL gTimer = { + TimerDriverRegisterHandler, + TimerDriverSetTimerPeriod, + TimerDriverGetTimerPeriod, + TimerDriverGenerateSoftInterrupt +}; + + +/** + Initialize the state information for the Timer Architectural Protocol and + the Timer Debug support protocol that allows the debugger to break into a + running program. + + @param ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Protocol registered + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure + @retval EFI_DEVICE_ERROR Hardware problems + +**/ +EFI_STATUS +EFIAPI +TimerInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_HANDLE Handle = NULL; + EFI_STATUS Status; + UINT32 TimerBaseAddress; + + // Find the interrupt controller protocol. ASSERT if not found. + Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt); + ASSERT_EFI_ERROR (Status); + + // Set up the timer registers + TimerBaseAddress = TimerBase (FixedPcdGet32(PcdOmap44xxArchTimer)); + TISR = TimerBaseAddress + GPTIMER_TISR; + TCLR = TimerBaseAddress + GPTIMER_TCLR; + TLDR = TimerBaseAddress + GPTIMER_TLDR; + TCRR = TimerBaseAddress + GPTIMER_TCRR; + TIER = TimerBaseAddress + GPTIMER_TIER; + + // Disable the timer + Status = TimerDriverSetTimerPeriod (&gTimer, 0); + ASSERT_EFI_ERROR (Status); + + // Install interrupt handler + gVector = InterruptVectorForTimer (FixedPcdGet32(PcdOmap44xxArchTimer)); + Status = gInterrupt->RegisterInterruptSource (gInterrupt, gVector, TimerInterruptHandler); + ASSERT_EFI_ERROR (Status); + + // Set up default timer + Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); + ASSERT_EFI_ERROR (Status); + + // Install the Timer Architectural Protocol onto a new handle + Status = gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiTimerArchProtocolGuid, &gTimer, + NULL + ); + ASSERT_EFI_ERROR(Status); + + return Status; +} + diff --git a/Omap44xxPkg/TimerDxe/TimerDxe.inf b/Omap44xxPkg/TimerDxe/TimerDxe.inf new file mode 100644 index 000000000..b607e19b0 --- /dev/null +++ b/Omap44xxPkg/TimerDxe/TimerDxe.inf @@ -0,0 +1,57 @@ +#/** @file +# +# Component discription file for Timer module +# +# Copyright (c) 2009, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardTimerDxe + FILE_GUID = 6ddbf08b-cfc9-43cc-9e81-0784ba312ca0 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = TimerInitialize + +[Sources.common] + Timer.c + +[Packages] + Omap44xxPkg/Omap44xxPkg.dec + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + +[LibraryClasses] + BaseLib + UefiRuntimeServicesTableLib + UefiLib + UefiBootServicesTableLib + BaseMemoryLib + DebugLib + UefiDriverEntryPoint + IoLib + OmapLib + +[Guids] + +[Protocols] + gEfiTimerArchProtocolGuid + gHardwareInterruptProtocolGuid + +[Pcd.common] + gEmbeddedTokenSpaceGuid.PcdTimerPeriod + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterPeriodInNanoseconds + gOmap44xxTokenSpaceGuid.PcdOmap44xxArchTimer + +[Depex] + gHardwareInterruptProtocolGuid
\ No newline at end of file diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index f7064b737..7c666d970 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -541,7 +541,7 @@ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
- PathLib|ShellPkg/Library/BasePathLib/BasePathLib.inf
+ PathLib|MdeModulePkg/Library/BasePathLib/BasePathLib.inf
# SafeBlockIoLib|ShellPkg/Library/SafeBlockIoLib/SafeBlockIoLib.inf
# SafeOpenProtocolLib|ShellPkg/Library/SafeOpenProtocolLib/SafeOpenProtocolLib.inf
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 26d1132a8..e65062646 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -548,7 +548,7 @@ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
- PathLib|ShellPkg/Library/BasePathLib/BasePathLib.inf
+ PathLib|MdeModulePkg/Library/BasePathLib/BasePathLib.inf
# SafeBlockIoLib|ShellPkg/Library/SafeBlockIoLib/SafeBlockIoLib.inf
# SafeOpenProtocolLib|ShellPkg/Library/SafeOpenProtocolLib/SafeOpenProtocolLib.inf
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 66459c217..2b4a63971 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -546,7 +546,7 @@ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf
PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
- PathLib|ShellPkg/Library/BasePathLib/BasePathLib.inf
+ PathLib|MdeModulePkg/Library/BasePathLib/BasePathLib.inf
# SafeBlockIoLib|ShellPkg/Library/SafeBlockIoLib/SafeBlockIoLib.inf
# SafeOpenProtocolLib|ShellPkg/Library/SafeOpenProtocolLib/SafeOpenProtocolLib.inf
diff --git a/PandaBoardPkg/Bds/Bds.inf b/PandaBoardPkg/Bds/Bds.inf new file mode 100644 index 000000000..c2ea26c83 --- /dev/null +++ b/PandaBoardPkg/Bds/Bds.inf @@ -0,0 +1,65 @@ + +#/** @file +# +# Component discription file for Bds module +# +# Copyright (c) 2009, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardBds + FILE_GUID = 934431fe-5745-402e-913d-17b4434eb0f3 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + + ENTRY_POINT = BdsInitialize + +[Sources.common] + BdsEntry.c + FirmwareVolume.c + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + +[LibraryClasses] + DevicePathLib + BaseLib + HobLib + UefiRuntimeServicesTableLib + ReportStatusCodeLib + PerformanceLib + DxeServicesTableLib + MemoryAllocationLib + UefiLib + UefiBootServicesTableLib + BaseMemoryLib + DebugLib + PrintLib + UefiDriverEntryPoint + +[Guids] + + +[Protocols] + gEfiBdsArchProtocolGuid + gEfiSimpleTextInProtocolGuid + gEfiSimpleTextOutProtocolGuid + gEfiSerialIoProtocolGuid + gEfiDevicePathProtocolGuid + gEfiSimpleFileSystemProtocolGuid + gEfiUsbIoProtocolGuid + gEfiFirmwareVolume2ProtocolGuid + +[Depex] + TRUE diff --git a/PandaBoardPkg/Bds/BdsEntry.c b/PandaBoardPkg/Bds/BdsEntry.c new file mode 100644 index 000000000..15fda69d9 --- /dev/null +++ b/PandaBoardPkg/Bds/BdsEntry.c @@ -0,0 +1,246 @@ +/** @file + The entry of the embedded BDS. This BDS does not follow the Boot Manager requirements + of the UEFI specification as it is designed to implement an embedded systmes + propriatary boot scheme. + + This template assume a DXE driver produces a SerialIo protocol not using the EFI + driver module and it will attempt to connect a console on top of this. + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "BdsEntry.h" + + +BOOLEAN gConsolePresent = FALSE; + + +EFI_HANDLE mBdsImageHandle = NULL; +EFI_BDS_ARCH_PROTOCOL gBdsProtocol = { + BdsEntry, +}; + + + + +/** + This function uses policy data from the platform to determine what operating + system or system utility should be loaded and invoked. This function call + also optionally make the use of user input to determine the operating system + or system utility to be loaded and invoked. When the DXE Core has dispatched + all the drivers on the dispatch queue, this function is called. This + function will attempt to connect the boot devices required to load and invoke + the selected operating system or system utility. During this process, + additional firmware volumes may be discovered that may contain addition DXE + drivers that can be dispatched by the DXE Core. If a boot device cannot be + fully connected, this function calls the DXE Service Dispatch() to allow the + DXE drivers from any newly discovered firmware volumes to be dispatched. + Then the boot device connection can be attempted again. If the same boot + device connection operation fails twice in a row, then that boot device has + failed, and should be skipped. This function should never return. + + @param This The EFI_BDS_ARCH_PROTOCOL instance. + + @return None. + +**/ +VOID +EFIAPI +BdsEntry ( + IN EFI_BDS_ARCH_PROTOCOL *This + ) +{ + EFI_STATUS Status; + UINTN NoHandles; + EFI_HANDLE *Buffer; + EFI_HANDLE FvHandle; + EFI_HANDLE ImageHandle; + EFI_HANDLE UsbDeviceHandle; + EFI_GUID NameGuid; + UINTN Size; + UINTN HandleCount; + UINTN OldHandleCount; + EFI_HANDLE *HandleBuffer; + UINTN Index; + EFI_DEVICE_PATH_PROTOCOL *LoadImageDevicePath; + EFI_DEVICE_PATH_PROTOCOL *FileSystemDevicePath; + + PERF_END (NULL, "DXE", NULL, 0); + PERF_START (NULL, "BDS", NULL, 0); + + + // + // Now do the EFI stuff + // + Size = 0x100; + gST->FirmwareVendor = AllocateRuntimePool (Size); + ASSERT (gST->FirmwareVendor != NULL); + + UnicodeSPrint (gST->FirmwareVendor, Size, L"PandaBoard EFI %a %a", __DATE__, __TIME__); + + // + // Now we need to setup the EFI System Table with information about the console devices. + // This code is normally in the console spliter driver on platforms that support multiple + // consoles at the same time + // + Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiSimpleTextOutProtocolGuid, NULL, &NoHandles, &Buffer); + if (!EFI_ERROR (Status)) { + // Use the first SimpleTextOut we find and update the EFI System Table + gST->ConsoleOutHandle = Buffer[0]; + gST->StandardErrorHandle = Buffer[0]; + Status = gBS->HandleProtocol (Buffer[0], &gEfiSimpleTextOutProtocolGuid, (VOID **)&gST->ConOut); + ASSERT_EFI_ERROR (Status); + + gST->StdErr = gST->ConOut; + + gST->ConOut->OutputString (gST->ConOut, L"BDS: Console Started!!!!\n\r"); + FreePool (Buffer); + + gConsolePresent = TRUE; + } + + + Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiSimpleTextInProtocolGuid, NULL, &NoHandles, &Buffer); + if (!EFI_ERROR (Status)) { + // Use the first SimpleTextIn we find and update the EFI System Table + gST->ConsoleInHandle = Buffer[0]; + Status = gBS->HandleProtocol (Buffer[0], &gEfiSimpleTextInProtocolGuid, (VOID **)&gST->ConIn); + ASSERT_EFI_ERROR (Status); + + FreePool (Buffer); + } + + // + // We now have EFI Consoles up and running. Print () will work now. DEBUG () and ASSERT () worked + // prior to this point as they were configured to use a more primative output scheme. + // + + // + //Perform Connect + // + HandleCount = 0; + while (1) { + OldHandleCount = HandleCount; + Status = gBS->LocateHandleBuffer ( + AllHandles, + NULL, + NULL, + &HandleCount, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + break; + } + + if (HandleCount == OldHandleCount) { + break; + } + + for (Index = 0; Index < HandleCount; Index++) { + gBS->ConnectController (HandleBuffer[Index], NULL, NULL, TRUE); + } + } + + EfiSignalEventReadyToBoot (); + + //Locate handles for SimpleFileSystem protocol + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiSimpleFileSystemProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + if (!EFI_ERROR(Status)) { + for (Index = 0; Index < HandleCount; Index++) { + //Get the device path + FileSystemDevicePath = DevicePathFromHandle(HandleBuffer[Index]); + if (FileSystemDevicePath == NULL) { + continue; + } + + //Check if UsbIo is on any handles in the device path. + Status = gBS->LocateDevicePath(&gEfiUsbIoProtocolGuid, &FileSystemDevicePath, &UsbDeviceHandle); + if (EFI_ERROR(Status)) { + continue; + } + + //Check if Usb stick has a magic EBL file. + LoadImageDevicePath = FileDevicePath(HandleBuffer[Index], L"Ebl.efi"); + Status = gBS->LoadImage (TRUE, gImageHandle, LoadImageDevicePath, NULL, 0, &ImageHandle); + if (EFI_ERROR(Status)) { + continue; + } + + //Boot to Shell on USB stick. + Status = gBS->StartImage (ImageHandle, NULL, NULL); + if (EFI_ERROR(Status)) { + continue; + } + } + } + + // + // Normal UEFI behavior is to process Globally Defined Variables as defined in Chapter 3 + // (Boot Manager) of the UEFI specification. For this embedded system we don't do this. + // + + // + // Search all the FVs for an application with a UI Section of Ebl. A .FDF file can be used + // to control the names of UI sections in an FV. + // + Status = FindApplicationMatchingUiSection (L"Ebl", &FvHandle, &NameGuid); + if (!EFI_ERROR (Status)) { + + //Boot to Shell. + Status = LoadPeCoffSectionFromFv (FvHandle, &NameGuid); + + if (EFI_ERROR(Status)) { + DEBUG((EFI_D_ERROR, "Boot from Shell failed. Status: %r\n", Status)); + } + } + + // + // EFI does not define the behaviour if all boot attemps fail and the last one returns. + // So we make a policy choice to reset the system since this BDS does not have a UI. + // + gRT->ResetSystem (EfiResetShutdown, Status, 0, NULL); + + return ; +} + + +EFI_STATUS +EFIAPI +BdsInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mBdsImageHandle = ImageHandle; + + // + // Install protocol interface + // + Status = gBS->InstallMultipleProtocolInterfaces ( + &mBdsImageHandle, + &gEfiBdsArchProtocolGuid, &gBdsProtocol, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + diff --git a/PandaBoardPkg/Bds/BdsEntry.h b/PandaBoardPkg/Bds/BdsEntry.h new file mode 100644 index 000000000..47891c01d --- /dev/null +++ b/PandaBoardPkg/Bds/BdsEntry.h @@ -0,0 +1,66 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __BDS_ENTRY_H__ +#define __BDS_ENTRY_H__ + +#include <PiDxe.h> +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/PrintLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/DxeServicesTableLib.h> +#include <Library/UefiRuntimeServicesTableLib.h> +#include <Library/HobLib.h> +#include <Library/DevicePathLib.h> +#include <Library/PcdLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PrintLib.h> +#include <Library/PerformanceLib.h> + +#include <Protocol/Bds.h> +#include <Protocol/SerialIo.h> +#include <Protocol/FirmwareVolume2.h> +#include <Protocol/SimpleTextIn.h> +#include <Protocol/SimpleTextOut.h> +#include <Protocol/EmbeddedDevice.h> +#include <Protocol/DevicePath.h> +#include <Protocol/SimpleFileSystem.h> +#include <Protocol/UsbIo.h> + + +EFI_STATUS +LoadPeCoffSectionFromFv ( + IN EFI_HANDLE FvHandle, + IN EFI_GUID *NameGuid + ); + +EFI_STATUS +FindApplicationMatchingUiSection ( + IN CHAR16 *UiString, + OUT EFI_HANDLE *FvHandle, + OUT EFI_GUID *NameGuid + ); + +VOID +EFIAPI +BdsEntry ( + IN EFI_BDS_ARCH_PROTOCOL *This + ); + +#endif + diff --git a/PandaBoardPkg/Bds/FirmwareVolume.c b/PandaBoardPkg/Bds/FirmwareVolume.c new file mode 100644 index 000000000..6c891f4e4 --- /dev/null +++ b/PandaBoardPkg/Bds/FirmwareVolume.c @@ -0,0 +1,150 @@ +/** @file + The entry of the embedded BDS. This BDS does not follow the Boot Manager requirements + of the UEFI specification as it is designed to implement an embedded systmes + propriatary boot scheme. + + This template assume a DXE driver produces a SerialIo protocol not using the EFI + driver module and it will attempt to connect a console on top of this. + + + Copyright (c) 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "BdsEntry.h" + + +EFI_STATUS +FindApplicationMatchingUiSection ( + IN CHAR16 *UiString, + OUT EFI_HANDLE *FvHandle, + OUT EFI_GUID *NameGuid + ) +{ + EFI_STATUS Status; + EFI_STATUS NextStatus; + UINTN NoHandles; + EFI_HANDLE *Buffer; + UINTN Index; + EFI_FV_FILETYPE FileType; + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; + VOID *Key; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN UiStringLen; + CHAR16 *UiSection; + UINT32 Authentication; + + + UiStringLen = 0; + if (UiString != NULL) { + DEBUG ((DEBUG_ERROR, "UiString %s\n", UiString)); + UiStringLen = StrLen (UiString); + } + + Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiFirmwareVolume2ProtocolGuid, NULL, &NoHandles, &Buffer); + if (!EFI_ERROR (Status)) { + for (Index = 0; Index < NoHandles; Index++) { + Status = gBS->HandleProtocol (Buffer[Index], &gEfiFirmwareVolume2ProtocolGuid, (VOID **)&Fv); + if (!EFI_ERROR (Status)) { + Key = AllocatePool (Fv->KeySize); + ASSERT (Key != NULL); + ZeroMem (Key, Fv->KeySize); + + FileType = EFI_FV_FILETYPE_APPLICATION; + + do { + NextStatus = Fv->GetNextFile (Fv, Key, &FileType, NameGuid, &Attributes, &Size); + if (!EFI_ERROR (NextStatus)) { + if (UiString == NULL) { + // + // If UiString is NULL match first application we find. + // + *FvHandle = Buffer[Index]; + FreePool (Key); + return Status; + } + + UiSection = NULL; + Status = Fv->ReadSection ( + Fv, + NameGuid, + EFI_SECTION_USER_INTERFACE, + 0, + (VOID **)&UiSection, + &Size, + &Authentication + ); + if (!EFI_ERROR (Status)) { + if (StrnCmp (UiString, UiSection, UiStringLen) == 0) { + // + // We found a UiString match. + // + *FvHandle = Buffer[Index]; + FreePool (Key); + FreePool (UiSection); + return Status; + } + FreePool (UiSection); + } + } + } while (!EFI_ERROR (NextStatus)); + + FreePool (Key); + } + } + + FreePool (Buffer); + } + + return EFI_NOT_FOUND; +} + + +EFI_DEVICE_PATH * +FvFileDevicePath ( + IN EFI_HANDLE FvHandle, + IN EFI_GUID *NameGuid + ) +{ + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH NewNode; + + DevicePath = DevicePathFromHandle (FvHandle); + + EfiInitializeFwVolDevicepathNode (&NewNode, NameGuid); + + return AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&NewNode); +} + + + +EFI_STATUS +LoadPeCoffSectionFromFv ( + IN EFI_HANDLE FvHandle, + IN EFI_GUID *NameGuid + ) +{ + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + EFI_HANDLE ImageHandle; + + DevicePath = FvFileDevicePath (FvHandle, NameGuid); + + Status = gBS->LoadImage (TRUE, gImageHandle, DevicePath, NULL, 0, &ImageHandle); + if (!EFI_ERROR (Status)) { + PERF_END (NULL, "BDS", NULL, 0); + Status = gBS->StartImage (ImageHandle, NULL, NULL); + } + + return Status; +} + diff --git a/PandaBoardPkg/ConfigurationHeader.dat b/PandaBoardPkg/ConfigurationHeader.dat new file mode 100644 index 000000000..ec7dbcd30 --- /dev/null +++ b/PandaBoardPkg/ConfigurationHeader.dat @@ -0,0 +1,64 @@ +TARGET=OMAP4 + +CHSETTINGS +SectionKey=0xC0C0C0C1 +Valid=0x00000001 +Version=0x00000000 +Reserved=0x00000000 +Flags=0x00000BBD +CM_CLKSEL_CORE=0x00000110 +CM_DLL_CTRL=0x00000000 +CM_AUTOIDLE_DPLL_MPU=0x00000000 +CM_CLKSEL_DPLL_MPU=0x00007D05 +CM_DIV_M2_DPLL_MPU=0x00000002 +CM_AUTOIDLE_DPLL_CORE=0x00000000 +CM_CLKSEL_DPLL_CORE=0x00007D05 +CM_DIV_M2_DPLL_CORE=0x00000002 +CM_DIV_M3_DPLL_CORE=0x00000008 +CM_DIV_M4_DPLL_CORE=0x00000008 +CM_DIV_M5_DPLL_CORE=0x00000008 +CM_DIV_M6_DPLL_CORE=0x00000008 +CM_DIV_M7_DPLL_CORE=0x00000010 +CM_AUTOIDLE_DPLL_PER=0x00000000 +CM_CLKSEL_DPLL_PER=0x00001400 +CM_DIV_M2_DPLL_PER=0x00000008 +CM_DIV_M3_DPLL_PER=0x00000008 +CM_DIV_M4_DPLL_PER=0x0000000C +CM_DIV_M5_DPLL_PER=0x00000009 +CM_DIV_M6_DPLL_PER=0x00000008 +CM_DIV_M7_DPLL_PER=0x0000000A +CM_AUTOIDLE_DPLL_USB=0x00000000 +CM_CLKSEL_DPLL_USB=0x00000000 +CM_DIV_M2_DPLL_USB=0x00000000 + +CHRAM +SectionKey=0xC0C0C0C2 +Valid=0x00000001 +Version=0x00000000 +Reserved=0x00000000 +SdramConfigEMIF1=0x80001ab9 +SdramRefreshEMIF1=0x00000618 +SdramTim1EMIF1=0x10eb0662 +SdramTim2EMIF1=0x20370dd2 +SdramTim3EMIF1=0x00b1c33f +PwrMgtCtrlEMIF1=0x000000ff +DdrPhyCtrl1EMIF1=0x049ff418 +DdrPhyCtrl2EMIF1=0x00000004 +ModeReg1EMIF1=0x000000c3 +ModeReg2EMIF1=0x00000004 +ModeReg3EMIF1=0x00000001 +Reserved=0x00000000 +SdramConfigEMIF2=0x80001ab9 +SdramRefreshEMIF2=0x00000618 +SdramTim1EMIF2=0x10eb0662 +SdramTim2EMIF2=0x20370dd2 +SdramTim3EMIF2=0x00b1c33f +PwrMgtCtrlEMIF2=0x000000ff +DdrPhyCtrl1EMIF2=0x049ff418 +DdrPhyCtrl2EMIF2=0x00000004 +ModeReg1EMIF2=0x000000c3 +ModeReg2EMIF2=0x00000004 +ModeReg3EMIF2=0x00000001 +Reserved=0x00000000 +DMMLisaMap0=0x80640300 +Flags=0x0000010f diff --git a/PandaBoardPkg/Debugger_scripts/rvi_boot_from_ram.inc b/PandaBoardPkg/Debugger_scripts/rvi_boot_from_ram.inc new file mode 100644 index 000000000..543ddb7a0 --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/rvi_boot_from_ram.inc @@ -0,0 +1,21 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +error = continue +unload +error = abort + +setreg @CP15_CONTROL = 0x0005107E +setreg @pc=0x80008208 +setreg @cpsr=0x000000D3 +dis/D +readfile,raw,nowarn "ZZZZZZ/FV/PANDABOARD_EFI.fd"=0x80008000 + diff --git a/PandaBoardPkg/Debugger_scripts/rvi_convert_symbols.sh b/PandaBoardPkg/Debugger_scripts/rvi_convert_symbols.sh new file mode 100644 index 000000000..9567f5c62 --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/rvi_convert_symbols.sh @@ -0,0 +1,23 @@ +#!/bin/sh +# +# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http:#opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + + +IN=`/usr/bin/cygpath -u $1` +OUT=`/usr/bin/cygpath -u $2` + +/usr/bin/sed -e "s/\/cygdrive\/\(.\)/load\/a\/ni\/np \"\1:/g" \ + -e 's:\\:/:g' \ + -e "s/^/load\/a\/ni\/np \"/g" \ + -e "s/dll /dll\" \&/g" \ + $IN | /usr/bin/sort.exe --key=3 --output=$OUT + diff --git a/PandaBoardPkg/Debugger_scripts/rvi_dummy.axf b/PandaBoardPkg/Debugger_scripts/rvi_dummy.axf Binary files differnew file mode 100755 index 000000000..17fabaa6c --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/rvi_dummy.axf diff --git a/PandaBoardPkg/Debugger_scripts/rvi_hw_setup.inc b/PandaBoardPkg/Debugger_scripts/rvi_hw_setup.inc new file mode 100644 index 000000000..ea5f8ec15 --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/rvi_hw_setup.inc @@ -0,0 +1,67 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// + +error = continue +unload +error = abort + +setreg @CP15_CONTROL = 0x0005107E +setreg @cpsr=0x000000D3 + +; General clock settings. +setmem /32 0x48307270=0x00000080 +setmem /32 0x48306D40=0x00000003 +setmem /32 0x48005140=0x03020A50 + +;Clock configuration +setmem /32 0x48004A40=0x0000030A +setmem /32 0x48004C40=0x00000015 + +;DPLL3 (Core) settings +setmem /32 0x48004D00=0x00370037 +setmem /32 0x48004D30=0x00000000 +setmem /32 0x48004D40=0x094C0C00 + +;DPLL4 (Peripheral) settings +setmem /32 0x48004D00=0x00370037 +setmem /32 0x48004D30=0x00000000 +setmem /32 0x48004D44=0x0001B00C +setmem /32 0x48004D48=0x00000009 + +;DPLL1 (MPU) settings +setmem /32 0x48004904=0x00000037 +setmem /32 0x48004934=0x00000000 +setmem /32 0x48004940=0x0011F40C +setmem /32 0x48004944=0x00000001 +setmem /32 0x48004948=0x00000000 + +;RAM setup. +setmem /16 0x6D000010=0x0000 +setmem /16 0x6D000040=0x0001 +setmem /16 0x6D000044=0x0100 +setmem /16 0x6D000048=0x0000 +setmem /32 0x6D000060=0x0000000A +setmem /32 0x6D000070=0x00000081 +setmem /16 0x6D000040=0x0003 +setmem /32 0x6D000080=0x02D04011 +setmem /16 0x6D000084=0x0032 +setmem /16 0x6D00008C=0x0000 +setmem /32 0x6D00009C=0xBA9DC4C6 +setmem /32 0x6D0000A0=0x00012522 +setmem /32 0x6D0000A4=0x0004E201 +setmem /16 0x6D000040=0x0003 +setmem /32 0x6D0000B0=0x02D04011 +setmem /16 0x6D0000B4=0x0032 +setmem /16 0x6D0000BC=0x0000 +setmem /32 0x6D0000C4=0xBA9DC4C6 +setmem /32 0x6D0000C8=0x00012522 +setmem /32 0x6D0000D4=0x0004E201
\ No newline at end of file diff --git a/PandaBoardPkg/Debugger_scripts/rvi_load_symbols.inc b/PandaBoardPkg/Debugger_scripts/rvi_load_symbols.inc new file mode 100644 index 000000000..b4a67365d --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/rvi_load_symbols.inc @@ -0,0 +1,23 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// + +include 'ZZZZZZ/rvi_symbols_macros.inc' + +macro write_symbols_file("ZZZZZZ/rvi_symbols.tmp", 0x00000000, 0x10000000) + +host "bash -o igncr ZZZZZZ/rvi_convert_symbols.sh ZZZZZZ/rvi_symbols.tmp ZZZZZZ/rvi_symbols.inc" +include 'ZZZZZZ/rvi_symbols.inc' +load /NI /NP 'ZZZZZZ/rvi_dummy.axf' ;.constdata +unload rvi_dummy.axf +delfile rvi_dummy.axf + + diff --git a/PandaBoardPkg/Debugger_scripts/rvi_symbols_macros.inc b/PandaBoardPkg/Debugger_scripts/rvi_symbols_macros.inc new file mode 100644 index 000000000..9e7f42774 --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/rvi_symbols_macros.inc @@ -0,0 +1,194 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// + +define /R int compare_guid(guid1, guid2) + unsigned char *guid1; + unsigned char *guid2; +{ + return strncmp(guid1, guid2, 16); +} +. + +define /R unsigned char * find_system_table(mem_start, mem_size) + unsigned char *mem_start; + unsigned long mem_size; +{ + unsigned char *mem_ptr; + + mem_ptr = mem_start + mem_size; + + do + { + mem_ptr -= 0x400000; // 4 MB + + if (strncmp(mem_ptr, "IBI SYST", 8) == 0) + { + return *(unsigned long *)(mem_ptr + 8); // EfiSystemTableBase + } + + } while (mem_ptr > mem_start); + + return 0; +} +. + +define /R unsigned char * find_debug_info_table_header(system_table) + unsigned char *system_table; +{ + unsigned long configuration_table_entries; + unsigned char *configuration_table; + unsigned long index; + unsigned char debug_table_guid[16]; + + // Fill in the debug table's guid + debug_table_guid[ 0] = 0x77; + debug_table_guid[ 1] = 0x2E; + debug_table_guid[ 2] = 0x15; + debug_table_guid[ 3] = 0x49; + debug_table_guid[ 4] = 0xDA; + debug_table_guid[ 5] = 0x1A; + debug_table_guid[ 6] = 0x64; + debug_table_guid[ 7] = 0x47; + debug_table_guid[ 8] = 0xB7; + debug_table_guid[ 9] = 0xA2; + debug_table_guid[10] = 0x7A; + debug_table_guid[11] = 0xFE; + debug_table_guid[12] = 0xFE; + debug_table_guid[13] = 0xD9; + debug_table_guid[14] = 0x5E; + debug_table_guid[15] = 0x8B; + + configuration_table_entries = *(unsigned long *)(system_table + 64); + configuration_table = *(unsigned long *)(system_table + 68); + + for (index = 0; index < configuration_table_entries; index++) + { + if (compare_guid(configuration_table, debug_table_guid) == 0) + { + return *(unsigned long *)(configuration_table + 16); + } + + configuration_table += 20; + } + + return 0; +} +. + +define /R int valid_pe_header(header) + unsigned char *header; +{ + if ((header[0x00] == 'M') && + (header[0x01] == 'Z') && + (header[0x80] == 'P') && + (header[0x81] == 'E')) + { + return 1; + } + + return 0; +} +. + +define /R unsigned long pe_headersize(header) + unsigned char *header; +{ + unsigned long *size; + + size = header + 0x00AC; + + return *size; +} +. + +define /R unsigned char *pe_filename(header) + unsigned char *header; +{ + unsigned long *debugOffset; + unsigned char *stringOffset; + + if (valid_pe_header(header)) + { + debugOffset = header + 0x0128; + stringOffset = header + *debugOffset + 0x002C; + + return stringOffset; + } + + return 0; +} +. + +define /R int char_is_valid(c) + unsigned char c; +{ + if (c >= 32 && c < 127) + return 1; + + return 0; +} +. + +define /R write_symbols_file(filename, mem_start, mem_size) + unsigned char *filename; + unsigned char *mem_start; + unsigned long mem_size; +{ + unsigned char *system_table; + unsigned char *debug_info_table_header; + unsigned char *debug_info_table; + unsigned long debug_info_table_size; + unsigned long index; + unsigned char *debug_image_info; + unsigned char *loaded_image_protocol; + unsigned char *image_base; + unsigned char *debug_filename; + unsigned long header_size; + int status; + + system_table = find_system_table(mem_start, mem_size); + if (system_table == 0) + { + return; + } + + status = fopen(88, filename, "w"); + + debug_info_table_header = find_debug_info_table_header(system_table); + + debug_info_table = *(unsigned long *)(debug_info_table_header + 8); + debug_info_table_size = *(unsigned long *)(debug_info_table_header + 4); + + for (index = 0; index < (debug_info_table_size * 4); index += 4) + { + debug_image_info = *(unsigned long *)(debug_info_table + index); + + if (debug_image_info == 0) + { + break; + } + + loaded_image_protocol = *(unsigned long *)(debug_image_info + 4); + + image_base = *(unsigned long *)(loaded_image_protocol + 32); + + debug_filename = pe_filename(image_base); + header_size = pe_headersize(image_base); + + $fprintf 88, "%s 0x%08x\n", debug_filename, image_base + header_size$; + } + + + fclose(88); +} +. + diff --git a/PandaBoardPkg/Debugger_scripts/rvi_unload_symbols.inc b/PandaBoardPkg/Debugger_scripts/rvi_unload_symbols.inc new file mode 100644 index 000000000..546c4f960 --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/rvi_unload_symbols.inc @@ -0,0 +1,118 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// + +error = continue + +unload + +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 +delfile 1 + +error = abort diff --git a/PandaBoardPkg/Debugger_scripts/trace32_load_symbols.cmm b/PandaBoardPkg/Debugger_scripts/trace32_load_symbols.cmm new file mode 100644 index 000000000..c70a67393 --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/trace32_load_symbols.cmm @@ -0,0 +1,215 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// + + ENTRY &ram_start &ram_size + + ;If system is running then stop the execution so we can load symbols. + break + + ;Reset all windows + WINPAGE.RESET + + ;Create AREA to display the symbols we are loading. + AREA.Reset + AREA.Create SYMBOL 300. 100. + AREA.View SYMBOL + AREA.Select SYMBOL + + // SYS.Option BE OFF + + ;Added based on suggestion from Lauterbach support. + MMU.TABLEWALK ON + MMU.ON + + ;Load symbols. + GOSUB load_symbols &ram_start &ram_size + + ;Open some windows and enable semihosting. + TOOLBAR ON + STATUSBAR ON + WINPAGE.RESET + + WINCLEAR + WINPOS 0.0 17.0 72. 13. 0. 0. W000 + SYStem + + WINPOS 0.0 0.0 110. 55. 13. 1. W001 + WINTABS 10. 10. 25. 62. + Data.List + + WINPAGE.SELECT P000 + + //Enable semihosting + // System.Option.BigEndian OFF + + tronchip.set swi on // ARM9/10/11 variant + + // configure and open semihosting channel + winpos 50% 50% 50% 50% + term.heapinfo 0 0x20000 0x30000 0x20000 + term.method armswi + term.mode string + term.gate + + WINPOS 115.0 0. 70. 35. 0. 1. W002 + Var.Local %HEX + + WINPOS 115.10 45. 48. 9. 0. 0. W003 + Register + + END + +find_system_table: + ENTRY &mem_start &mem_size + &mem_ptr=&mem_start+&mem_size + RPT + ( + &mem_ptr=&mem_ptr-0x400000 // 4 MB + &word1=Data.LONG(D:&mem_ptr) + &word2=Data.LONG(D:&mem_ptr+0x04) + IF &word1==0x20494249 + ( + IF &word2==0x54535953 + ( + &result=Data.LONG(D:&mem_ptr+0x08) + RETURN &result + ) + ) + ) + WHILE &mem_ptr>&mem_start + &result=0 + RETURN &result + +compare_guid: + ENTRY &guid + IF Data.LONG(D:&guid)==0x49152E77 + ( + IF Data.LONG(D:&guid+0x04)==0x47641ADA + ( + IF Data.LONG(D:&guid+0x08)==0xFE7AA2B7 + ( + IF Data.LONG(D:&guid+0x0C)==0x8B5ED9FE + ( + RETURN 0 + ) + ) + ) + ) + RETURN 1 + +find_debug_info_table_header: + ENTRY &system_table + &config_table_entries=Data.LONG(D:&system_table+0x40) + &config_table_pointer=Data.LONG(D:&system_table+0x44) + RPT &config_table_entries + ( + GOSUB compare_guid &config_table_pointer + ENTRY &result + IF &result==0 + ( + &result=Data.LONG(D:&config_table_pointer+0x10) + RETURN &result + ) + &config_table_pointer=&config_table_pointer+0x14 + ) + RETURN 0; + +valid_pe_header: + ENTRY &header + IF Data.BYTE(D:&header+0x00)==0x4D + ( + IF Data.BYTE(D:&header+0x01)==0x5A + ( + IF Data.BYTE(D:&header+0x80)==0x50 + ( + IF Data.BYTE(D:&header+0x81)==0x45 + ( + RETURN 1 + ) + ) + ) + ) + RETURN 0 + +get_file_string: + ENTRY &stringOffset + + local &string + + &more_string=data.string(d:&stringOffset) + + if (string.len("&more_string")>=128.) + ( + &string="&string"+"&more_string" + &stringOffset=&stringOffset+string.len("&more_string") + + //Get remaining file string + GOSUB get_file_string &stringOffset + ENTRY &more_string + &string="&string"+"&more_string" + ) + else + ( + &string="&string"+"&more_string" + &more_string="" + ) + RETURN &string + +load_symbol_file: + ENTRY &header &load_address + GOSUB valid_pe_header &header + ENTRY &result + + IF &result==1 + ( + &debugOffset=Data.LONG(D:&header+0x0128) + &stringOffset=&header+&debugOffset+0x002C + + GOSUB get_file_string &stringOffset + ENTRY &filestring + + // the below has to be customized per your environment + &filestring="x:"+string.mid("&filestring", 36., string.len("&filestring")) + + PRINT "&filestring 0x" &load_address + TDIAG Data.load.elf &filestring &load_address /nocode /noclear + ) + RETURN + +pe_headersize: + ENTRY &header; + RETURN Data.LONG(D:&header+0x00AC) + +load_symbols: + ENTRY &mem_start &mem_size + GOSUB find_system_table &mem_start &mem_size + ENTRY &system_table + GOSUB find_debug_info_table_header &system_table + ENTRY &debug_info_table_header + &debug_info_table=Data.LONG(D:&debug_info_table_header+0x08) + &debug_info_table_size=Data.LONG(D:&debug_info_table_header+0x04) + &index=0 + RPT &debug_info_table_size + ( + &debug_image_info=Data.LONG(D:&debug_info_table+&index) + IF &debug_image_info==0 + RETURN + &loaded_image_protocol=Data.LONG(D:&debug_image_info+0x04); + &image_base=Data.LONG(D:&loaded_image_protocol+0x20); + GOSUB pe_headersize &image_base + ENTRY &header_size + &image_load_address=&image_base+&header_size + GOSUB load_symbol_file &image_base &image_load_address + &index=&index+0x4 + ) + + RETURN diff --git a/PandaBoardPkg/Debugger_scripts/trace32_load_symbols_cygwin.cmm b/PandaBoardPkg/Debugger_scripts/trace32_load_symbols_cygwin.cmm new file mode 100644 index 000000000..13943aad6 --- /dev/null +++ b/PandaBoardPkg/Debugger_scripts/trace32_load_symbols_cygwin.cmm @@ -0,0 +1,188 @@ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// + + ENTRY &ram_start &ram_size + + ;If system is running then stop the execution so we can load symbols. + break + + ;Reset all windows + WINPAGE.RESET + + AREA.Reset + AREA.Create SYMBOL 300. 100. + AREA.View SYMBOL + AREA.Select SYMBOL + SYS.Option BE OFF + + ; Added based on suggestion from Lauterbach support. + MMU.TABLEWALK ON + MMU.ON + + GOSUB load_symbols &ram_start &ram_size + + ;Open some windows. + WINPOS 83.125 29.063 48. 9. 0. 0. W003 + Register + + WINPOS 83.25 10. 48. 9. 0. 1. W002 + Var.Local + + END + +find_system_table: + ENTRY &mem_start &mem_size + &mem_ptr=&mem_start+&mem_size + RPT + ( + &mem_ptr=&mem_ptr-0x400000 // 4 MB + &word1=Data.LONG(D:&mem_ptr) + &word2=Data.LONG(D:&mem_ptr+0x04) + IF &word1==0x20494249 + ( + IF &word2==0x54535953 + ( + &result=Data.LONG(D:&mem_ptr+0x08) + RETURN &result + ) + ) + ) + WHILE &mem_ptr>&mem_start + &result=0 + RETURN &result + +compare_guid: + ENTRY &guid + IF Data.LONG(D:&guid)==0x49152E77 + ( + IF Data.LONG(D:&guid+0x04)==0x47641ADA + ( + IF Data.LONG(D:&guid+0x08)==0xFE7AA2B7 + ( + IF Data.LONG(D:&guid+0x0C)==0x8B5ED9FE + ( + RETURN 0 + ) + ) + ) + ) + RETURN 1 + +find_debug_info_table_header: + ENTRY &system_table + &config_table_entries=Data.LONG(D:&system_table+0x40) + &config_table_pointer=Data.LONG(D:&system_table+0x44) + RPT &config_table_entries + ( + GOSUB compare_guid &config_table_pointer + ENTRY &result + IF &result==0 + ( + &result=Data.LONG(D:&config_table_pointer+0x10) + RETURN &result + ) + &config_table_pointer=&config_table_pointer+0x14 + ) + RETURN 0; + +valid_pe_header: + ENTRY &header + IF Data.BYTE(D:&header+0x00)==0x4D + ( + IF Data.BYTE(D:&header+0x01)==0x5A + ( + IF Data.BYTE(D:&header+0x80)==0x50 + ( + IF Data.BYTE(D:&header+0x81)==0x45 + ( + RETURN 1 + ) + ) + ) + ) + RETURN 0 + +get_file_string: + ENTRY &stringOffset + + local &string + + &more_string=data.string(d:&stringOffset) + + if (string.len("&more_string")>=128.) + ( + &string="&string"+"&more_string" + &stringOffset=&stringOffset+string.len("&more_string") + + //Get remaining file string + GOSUB get_file_string &stringOffset + ENTRY &more_string + &string="&string"+"&more_string" + ) + else + ( + &string="&string"+"&more_string" + &more_string="" + ) + RETURN &string + +load_symbol_file: + ENTRY &header &load_address + GOSUB valid_pe_header &header + ENTRY &result + + IF &result==1 + ( + &debugOffset=Data.LONG(D:&header+0x0128) + &stringOffset=&header+&debugOffset+0x002C + + &stringOffset=&stringOffset+11. + + GOSUB get_file_string &stringOffset + ENTRY &filestring + + &filestring="c:"+"&filestring" + + PRINT "&filestring 0x" &load_address + Data.load.elf &filestring &load_address /nocode /noclear + ) + RETURN + +pe_headersize: + ENTRY &header; + RETURN Data.LONG(D:&header+0x00AC) + +load_symbols: + ENTRY &mem_start &mem_size + GOSUB find_system_table &mem_start &mem_size + ENTRY &system_table + GOSUB find_debug_info_table_header &system_table + ENTRY &debug_info_table_header + &debug_info_table=Data.LONG(D:&debug_info_table_header+0x08) + &debug_info_table_size=Data.LONG(D:&debug_info_table_header+0x04) + &index=0 + RPT &debug_info_table_size + ( + &debug_image_info=Data.LONG(D:&debug_info_table+&index) + IF &debug_image_info==0 + RETURN + &loaded_image_protocol=Data.LONG(D:&debug_image_info+0x04); + &image_base=Data.LONG(D:&loaded_image_protocol+0x20); + GOSUB pe_headersize &image_base + ENTRY &header_size + &image_load_address=&image_base+&header_size + GOSUB load_symbol_file &image_base &image_load_address + &index=&index+0x4 + ) + + RETURN +
\ No newline at end of file diff --git a/PandaBoardPkg/Include/PandaBoard.h b/PandaBoardPkg/Include/PandaBoard.h new file mode 100644 index 000000000..3f806e8e2 --- /dev/null +++ b/PandaBoardPkg/Include/PandaBoard.h @@ -0,0 +1,182 @@ +/** @file +* Header defining the PandaBoard constants (Base addresses, sizes, flags) +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __PANDABOARD_PLATFORM_H__ +#define __PANDABOARD_PLATFORM_H__ + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED + +#if 0 +// SoC registers. L3 interconnects +#define SOC_REGISTERS_L3_PHYSICAL_BASE 0x68000000 +#define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000 +#define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE +#endif + +// GPMC +#define SOC_REGISTERS_L3_PHYSICAL_BASE 0x50000000 +#define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000 +#define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE + +// SoC registers. L4 interconnects +#define SOC_REGISTERS_L4_PHYSICAL_BASE 0x48000000 +#define SOC_REGISTERS_L4_PHYSICAL_LENGTH 0x08000000 +#define SOC_REGISTERS_L4_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE + + +#if 0 +/******************************************* +// Platform Memory Map +*******************************************/ + +// Can be NOR, DOC, DRAM, SRAM +#define ARM_EB_REMAP_BASE 0x00000000 +#define ARM_EB_REMAP_SZ 0x04000000 + +// Motherboard Peripheral and On-chip peripheral +#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000 +#define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x00100000 +#define ARM_EB_BOARD_PERIPH_BASE 0x10000000 +//#define ARM_EB_CHIP_PERIPH_BASE 0x10020000 + +// SMC +#define ARM_EB_SMC_BASE 0x40000000 +#define ARM_EB_SMC_SZ 0x20000000 + +// NOR Flash 1 +#define ARM_EB_SMB_NOR_BASE 0x40000000 +#define ARM_EB_SMB_NOR_SZ 0x04000000 /* 64 MB */ +// DOC Flash +#define ARM_EB_SMB_DOC_BASE 0x44000000 +#define ARM_EB_SMB_DOC_SZ 0x04000000 /* 64 MB */ +// SRAM +#define ARM_EB_SMB_SRAM_BASE 0x48000000 +#define ARM_EB_SMB_SRAM_SZ 0x02000000 /* 32 MB */ +// USB, Ethernet, VRAM +#define ARM_EB_SMB_PERIPH_BASE 0x4E000000 +//#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000 +#define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */ + +// DRAM +#define ARM_EB_DRAM_BASE 0x70000000 +#define ARM_EB_DRAM_SZ 0x10000000 + +// Logic Tile +#define ARM_EB_LOGIC_TILE_BASE 0xC0000000 +#define ARM_EB_LOGIC_TILE_SZ 0x40000000 + +/******************************************* +// Motherboard peripherals +*******************************************/ + +// Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE) +#define ARM_EB_SYS_FLAGS_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030) +#define ARM_EB_SYS_FLAGS_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030) +#define ARM_EB_SYS_FLAGS_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00034) +#define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038) +#define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038) +#define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C) +#define ARM_EB_SYS_CLCD (ARM_EB_BOARD_PERIPH_BASE + 0x00050) +#define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084) +#define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088) +#define ARM_EB_SYS_CFGDATA_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A0) +#define ARM_EB_SYS_CFGCTRL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A4) +#define ARM_EB_SYS_CFGSTAT_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A8) + +// SP810 Controller +#define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000) + +// SYSTRCL Register +#define ARM_EB_SYSCTRL 0x10001000 + +// Uart0 +#define PL011_CONSOLE_UART_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x09000) +#define PL011_CONSOLE_UART_SPEED 115200 + +// SP804 Timer Bases +#define SP804_TIMER0_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11000) +#define SP804_TIMER1_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11020) +#define SP804_TIMER2_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12000) +#define SP804_TIMER3_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12020) + +// PL301 RTC +#define PL031_RTC_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x17000) + +// Dynamic Memory Controller Base +#define ARM_EB_DMC_BASE 0x10018000 + +// Static Memory Controller Base +#define ARM_EB_SMC_CTRL_BASE 0x10080000 + +#define PL111_CLCD_BASE 0x10020000 +//TODO: FIXME ... Reserved the memory in UEFI !!! Otherwise risk of corruption +#define PL111_CLCD_VRAM_BASE 0x78000000 + +#define ARM_EB_SYS_OSCCLK4 0x1000001C + + +/*// System Configuration Controller register Base addresses +//#define ARM_EB_SYS_CFG_CTRL_BASE 0x100E2000 +#define ARM_EB_SYS_CFGRW0_REG 0x100E2000 +#define ARM_EB_SYS_CFGRW1_REG 0x100E2004 +#define ARM_EB_SYS_CFGRW2_REG 0x100E2008 + +#define ARM_EB_CFGRW1_REMAP_NOR0 0 +#define ARM_EB_CFGRW1_REMAP_NOR1 (1 << 28) +#define ARM_EB_CFGRW1_REMAP_EXT_AXI (1 << 29) +#define ARM_EB_CFGRW1_REMAP_DRAM (1 << 30) + +// PL301 Fast AXI Base Address +#define ARM_EB_FAXI_BASE 0x100E9000 + +// L2x0 Cache Controller Base Address +//#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/ + + +// PL031 RTC - Other settings +#define PL031_PPM_ACCURACY 300000000 + +/******************************************* +// Interrupt Map +*******************************************/ + +// Timer Interrupts +#define TIMER01_INTERRUPT_NUM 34 +#define TIMER23_INTERRUPT_NUM 35 + + +/******************************************* +// EFI Memory Map in Permanent Memory (DRAM) +*******************************************/ + +// This region is allocated at the bottom of the DRAM. It will be used +// for fixed address allocations such as Vector Table +#define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB + +// This region is the memory declared to PEI as permanent memory for PEI +// and DXE. EFI stacks and heaps will be declared in this region. +#define ARM_EB_EFI_MEMORY_REGION_SZ 0x1000000 +#endif + +#endif + +typedef enum { + PANDABOARD_REVISION_UNKNOWN=0, + PANDABOARD_REVISION_PANDA, + PANDABOARD_REVISION_PANDAES + +} PANDABOARD_REVISION; diff --git a/PandaBoardPkg/Library/EblCmdLib/EblCmdLib.c b/PandaBoardPkg/Library/EblCmdLib/EblCmdLib.c new file mode 100644 index 000000000..a303e606b --- /dev/null +++ b/PandaBoardPkg/Library/EblCmdLib/EblCmdLib.c @@ -0,0 +1,299 @@ +/** @file + Add custom commands for PandaBoard development. + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <PiDxe.h> +#include <Library/ArmLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/EblCmdLib.h> +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiRuntimeServicesTableLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/UefiLib.h> +#include <Library/PcdLib.h> +#include <Library/EfiFileLib.h> +#include <Library/ArmDisassemblerLib.h> +#include <Library/PeCoffGetEntryPointLib.h> +#include <Library/PerformanceLib.h> +#include <Library/TimerLib.h> + +#include <Guid/DebugImageInfoTable.h> + +#include <Protocol/DebugSupport.h> +#include <Protocol/LoadedImage.h> + +/** + Simple arm disassembler via a library + + Argv[0] - symboltable + Argv[1] - Optional quoted format string + Argv[2] - Optional flag + + @param Argc Number of command arguments in Argv + @param Argv Array of strings that represent the parsed command line. + Argv[0] is the command name + + @return EFI_SUCCESS + +**/ +EFI_STATUS +EblSymbolTable ( + IN UINTN Argc, + IN CHAR8 **Argv + ) +{ + EFI_STATUS Status; + EFI_DEBUG_IMAGE_INFO_TABLE_HEADER *DebugImageTableHeader = NULL; + EFI_DEBUG_IMAGE_INFO *DebugTable; + UINTN Entry; + CHAR8 *Format; + CHAR8 *Pdb; + UINT32 PeCoffSizeOfHeaders; + UINT32 ImageBase; + BOOLEAN Elf; + + // Need to add lots of error checking on the passed in string + // Default string is for RealView debugger or gdb depending on toolchain used. + if (Argc > 1) { + Format = Argv[1]; + } else { +#if __GNUC__ + // Assume gdb + Format = "add-symbol-file %a 0x%x"; +#else + // Default to RVCT + Format = "load /a /ni /np %a &0x%x"; +#endif + } + Elf = (Argc > 2) ? FALSE : TRUE; + + Status = EfiGetSystemConfigurationTable (&gEfiDebugImageInfoTableGuid, (VOID **)&DebugImageTableHeader); + if (EFI_ERROR (Status)) { + return Status; + } + + DebugTable = DebugImageTableHeader->EfiDebugImageInfoTable; + if (DebugTable == NULL) { + return EFI_SUCCESS; + } + + for (Entry = 0; Entry < DebugImageTableHeader->TableSize; Entry++, DebugTable++) { + if (DebugTable->NormalImage != NULL) { + if ((DebugTable->NormalImage->ImageInfoType == EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL) && (DebugTable->NormalImage->LoadedImageProtocolInstance != NULL)) { + ImageBase = (UINT32)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase; + PeCoffSizeOfHeaders = PeCoffGetSizeOfHeaders ((VOID *)(UINTN)ImageBase); + Pdb = PeCoffLoaderGetPdbPointer (DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase); + if (Pdb != NULL) { + if (Elf) { + // ELF and Mach-O images don't include the header so the linked address does not include header + ImageBase += PeCoffSizeOfHeaders; + } + AsciiPrint (Format, Pdb, ImageBase); + AsciiPrint ("\n"); + } else { + } + } + } + } + + return EFI_SUCCESS; +} + + +/** + Simple arm disassembler via a library + + Argv[0] - disasm + Argv[1] - Address to start disassembling from + ARgv[2] - Number of instructions to disassembly (optional) + + @param Argc Number of command arguments in Argv + @param Argv Array of strings that represent the parsed command line. + Argv[0] is the command name + + @return EFI_SUCCESS + +**/ +EFI_STATUS +EblDisassembler ( + IN UINTN Argc, + IN CHAR8 **Argv + ) +{ + UINT8 *Ptr, *CurrentAddress; + UINT32 Address; + UINT32 Count; + CHAR8 Buffer[80]; + UINT32 ItBlock; + + if (Argc < 2) { + return EFI_INVALID_PARAMETER; + } + + Address = AsciiStrHexToUintn (Argv[1]); + Count = (Argc > 2) ? (UINT32)AsciiStrHexToUintn (Argv[2]) : 20; + + Ptr = (UINT8 *)(UINTN)Address; + ItBlock = 0; + do { + CurrentAddress = Ptr; + DisassembleInstruction (&Ptr, TRUE, TRUE, &ItBlock, Buffer, sizeof (Buffer)); + AsciiPrint ("0x%08x: %a\n", CurrentAddress, Buffer); + } while (Count-- > 0); + + + return EFI_SUCCESS; +} + + +CHAR8 * +ImageHandleToPdbFileName ( + IN EFI_HANDLE Handle + ) +{ + EFI_STATUS Status; + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; + CHAR8 *Pdb; + CHAR8 *StripLeading; + + Status = gBS->HandleProtocol (Handle, &gEfiLoadedImageProtocolGuid, (VOID **)&LoadedImage); + if (EFI_ERROR (Status)) { + return ""; + } + + Pdb = PeCoffLoaderGetPdbPointer (LoadedImage->ImageBase); + StripLeading = AsciiStrStr (Pdb, "\\ARM\\"); + if (StripLeading == NULL) { + StripLeading = AsciiStrStr (Pdb, "/ARM/"); + if (StripLeading == NULL) { + return Pdb; + } + } + // Hopefully we hacked off the unneeded part + return (StripLeading + 5); +} + + +CHAR8 *mTokenList[] = { + "SEC", + "PEI", + "DXE", + "BDS", + NULL +}; + +/** + Simple arm disassembler via a library + + Argv[0] - disasm + Argv[1] - Address to start disassembling from + ARgv[2] - Number of instructions to disassembly (optional) + + @param Argc Number of command arguments in Argv + @param Argv Array of strings that represent the parsed command line. + Argv[0] is the command name + + @return EFI_SUCCESS + +**/ +EFI_STATUS +EblPerformance ( + IN UINTN Argc, + IN CHAR8 **Argv + ) +{ + UINTN Key; + CONST VOID *Handle; + CONST CHAR8 *Token, *Module; + UINT64 Start, Stop, TimeStamp; + UINT64 Delta, TicksPerSecond, Milliseconds, Microseconds; + UINTN Index; + + TicksPerSecond = GetPerformanceCounterProperties (NULL, NULL); + + Key = 0; + do { + Key = GetPerformanceMeasurement (Key, (CONST VOID **)&Handle, &Token, &Module, &Start, &Stop); + if (Key != 0) { + if (AsciiStriCmp ("StartImage:", Token) == 0) { + if (Stop == 0) { + // The entry for EBL is still running so the stop time will be zero. Skip it + AsciiPrint (" running %a\n", ImageHandleToPdbFileName ((EFI_HANDLE)Handle)); + } else { + Delta = Stop - Start; + Microseconds = DivU64x64Remainder (MultU64x32 (Delta, 1000000), TicksPerSecond, NULL); + AsciiPrint ("%10ld us %a\n", Microseconds, ImageHandleToPdbFileName ((EFI_HANDLE)Handle)); + } + } + } + } while (Key != 0); + + AsciiPrint ("\n"); + + TimeStamp = 0; + Key = 0; + do { + Key = GetPerformanceMeasurement (Key, (CONST VOID **)&Handle, &Token, &Module, &Start, &Stop); + if (Key != 0) { + for (Index = 0; mTokenList[Index] != NULL; Index++) { + if (AsciiStriCmp (mTokenList[Index], Token) == 0) { + Delta = Stop - Start; + TimeStamp += Delta; + Milliseconds = DivU64x64Remainder (MultU64x32 (Delta, 1000), TicksPerSecond, NULL); + AsciiPrint ("%6a %6ld ms\n", Token, Milliseconds); + break; + } + } + } + } while (Key != 0); + + AsciiPrint ("Total Time = %ld ms\n\n", DivU64x64Remainder (MultU64x32 (TimeStamp, 1000), TicksPerSecond, NULL)); + + return EFI_SUCCESS; +} + + +GLOBAL_REMOVE_IF_UNREFERENCED const EBL_COMMAND_TABLE mLibCmdTemplate[] = +{ + { + "disasm address [count]", + " disassemble count instructions", + NULL, + EblDisassembler + }, + { + "performance", + " Display boot performance info", + NULL, + EblPerformance + }, + { + "symboltable [\"format string\"] [PECOFF]", + " show symbol table commands for debugger", + NULL, + EblSymbolTable + } +}; + + +VOID +EblInitializeExternalCmd ( + VOID + ) +{ + EblAddCommands (mLibCmdTemplate, sizeof (mLibCmdTemplate)/sizeof (EBL_COMMAND_TABLE)); + return; +} diff --git a/PandaBoardPkg/Library/EblCmdLib/EblCmdLib.inf b/PandaBoardPkg/Library/EblCmdLib/EblCmdLib.inf new file mode 100644 index 000000000..594956eb7 --- /dev/null +++ b/PandaBoardPkg/Library/EblCmdLib/EblCmdLib.inf @@ -0,0 +1,53 @@ +#/** @file +# Component description file for the entry point to a EFIDXE Drivers +# +# Library to abstract Framework extensions that conflict with UEFI 2.0 Specification +# Copyright (c) 2007 - 2007, Intel Corporation. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardEblCmdLib + FILE_GUID = ea62bdc3-1063-425f-8851-98cb47f213a8 + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = EblCmdLib|DXE_DRIVER UEFI_APPLICATION UEFI_DRIVER + + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF EBC +# + +[Sources.common] + EblCmdLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + ArmDisassemblerLib + PerformanceLib + TimerLib + +[Protocols] + gEfiDebugSupportProtocolGuid + gEfiLoadedImageProtocolGuid + +[Guids] + gEfiDebugImageInfoTableGuid diff --git a/PandaBoardPkg/Library/GdbSerialLib/GdbSerialLib.c b/PandaBoardPkg/Library/GdbSerialLib/GdbSerialLib.c new file mode 100644 index 000000000..9072c5856 --- /dev/null +++ b/PandaBoardPkg/Library/GdbSerialLib/GdbSerialLib.c @@ -0,0 +1,103 @@ +/** @file + Basic serial IO abstaction for GDB + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Uefi.h> +#include <Library/GdbSerialLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Library/OmapLib.h> +#include <Omap4430/Omap4430.h> + +RETURN_STATUS +EFIAPI +GdbSerialLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return RETURN_SUCCESS; +} + +RETURN_STATUS +EFIAPI +GdbSerialInit ( + IN UINT64 BaudRate, + IN UINT8 Parity, + IN UINT8 DataBits, + IN UINT8 StopBits + ) +{ + return RETURN_SUCCESS; +} + +BOOLEAN +EFIAPI +GdbIsCharAvailable ( + VOID + ) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + + if ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_NOT_EMPTY) { + return TRUE; + } else { + return FALSE; + } +} + +CHAR8 +EFIAPI +GdbGetChar ( + VOID + ) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + UINT32 RBR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_RBR_REG; + CHAR8 Char; + + while ((MmioRead8(LSR) & UART_LSR_RX_FIFO_E_MASK) == UART_LSR_RX_FIFO_E_EMPTY); + Char = MmioRead8(RBR); + + return Char; +} + +VOID +EFIAPI +GdbPutChar ( + IN CHAR8 Char + ) +{ + UINT32 LSR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_LSR_REG; + UINT32 THR = UartBase(PcdGet32(PcdOmap44xxConsoleUart)) + UART_THR_REG; + + while ((MmioRead8(LSR) & UART_LSR_TX_FIFO_E_MASK) == UART_LSR_TX_FIFO_E_NOT_EMPTY); + MmioWrite8(THR, Char); +} + +VOID +GdbPutString ( + IN CHAR8 *String + ) +{ + while (*String != '\0') { + GdbPutChar (*String); + String++; + } +} + + + + diff --git a/PandaBoardPkg/Library/GdbSerialLib/GdbSerialLib.inf b/PandaBoardPkg/Library/GdbSerialLib/GdbSerialLib.inf new file mode 100644 index 000000000..a9eb2a745 --- /dev/null +++ b/PandaBoardPkg/Library/GdbSerialLib/GdbSerialLib.inf @@ -0,0 +1,41 @@ +#/** @file +# +# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = GdbSerialLib + FILE_GUID = E2423349-EF5D-439B-95F5-8B8D8E3B443F + MODULE_TYPE = UEFI_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = GdbSerialLib + + CONSTRUCTOR = GdbSerialLibConstructor + + +[Sources.common] + GdbSerialLib.c + + +[Packages] + MdePkg/MdePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[LibraryClasses] + DebugLib + IoLib + OmapLib + +[FixedPcd] + gOmap44xxTokenSpaceGuid.PcdOmap44xxConsoleUart + diff --git a/PandaBoardPkg/Library/PandaBoardLib/Clock.c b/PandaBoardPkg/Library/PandaBoardLib/Clock.c new file mode 100644 index 000000000..6e3ffbf47 --- /dev/null +++ b/PandaBoardPkg/Library/PandaBoardLib/Clock.c @@ -0,0 +1,257 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Library/IoLib.h> +#include <Library/DebugLib.h> + +#include <PandaBoard.h> +#include <Omap4430/Omap4430.h> + +VOID +VolConSetup ( + IN UINTN PmcSlaveAddr, + IN UINTN SmpsAddr, + IN UINTN Data + ) +{ + // Setup VolCon command + MmioWrite32 (PRM_VC_VAL_BYPASS, + ((Data<<PRM_VC_VAL_BYPASS_DATA_POS)| + (SmpsAddr<<PRM_VC_VAL_BYPASS_REGADDR_POS)| + (PmcSlaveAddr)) ); + + // Validate command + MmioOr32 (PRM_VC_VAL_BYPASS, BIT24); + + // Wait for command completion + while( MmioRead32(PRM_VC_VAL_BYPASS) & BIT24 ); +} + +VOID +VolConInit ( + VOID + ) +{ + // Sram Ldo Voltage Control Override (MPU, CORE, IVA) + MmioWrite32 (CONTROL_CORE_LDOSRAM_IVA_VOLTAGE_CTRL, + CONTROL_CORE_LDOSRAM_VOLTAGE_CTRL_VAL); + MmioWrite32 (CONTROL_CORE_LDOSRAM_MPU_VOLTAGE_CTRL, + CONTROL_CORE_LDOSRAM_VOLTAGE_CTRL_VAL); + MmioWrite32 (CONTROL_CORE_LDOSRAM_CORE_VOLTAGE_CTRL, + CONTROL_CORE_LDOSRAM_VOLTAGE_CTRL_VAL); + + // Voltage controller setup + MmioWrite32 (PRM_VC_CFG_I2C_MODE, VC_CFG_I2C_MODE_VAL); + MmioWrite32 (PRM_VC_CFG_I2C_CLK, VC_CFG_I2C_CLK_VAL); +} + +VOID +ClockModuleEnable ( + IN UINTN Addr, + IN UINTN Mode + ) +{ + MmioOr32 (Addr, Mode); + while( (MmioRead32(Addr) & (BIT16|BIT17)) != 0 ); +} + +VOID +ClockInit ( + PANDABOARD_REVISION BoardRevision + ) +{ + // Init Voltage Controller + VolConInit (); + + // Setup CORE, MPU, IVA voltages for OPP100 operation + + ClockModuleEnable (0x4A307838, 0x1); //cm_wkup_gpio1_clkctrl: AUTO + + if( BoardRevision == PANDABOARD_REVISION_PANDAES ) { + // TPS62361 => VDD_MPU + // TWL6030 VCORE2 => VDD_IVA + // TWL6030 VCORE1 => VDD_CORE + + // Setup CORE voltage + VolConSetup(PMIC_SMPS_ID0_SLAVE_ADDR, + PMIC_VCORE1_CFG_FORCE_REGADDR, + PMIC_VCORE1_CFG_FORCE_VSEL_VDD_CORE_4460); + + // Clear TPS VSEL0 + MmioAnd32 (GPIO1_BASE + GPIO_OE, ~BIT7); + MmioOr32 (GPIO1_BASE + GPIO_CLEARDATAOUT, BIT7); + + // Setup MPU voltage + VolConSetup(TPS62361_SLAVE_ADDR, + TPS62361_SET1_REG_ADDR, + TPS62361_SET1_REG_VAL); + + // Set TPS VSEL0 + MmioOr32 (GPIO1_BASE + GPIO_SETDATAOUT, BIT7); + } + else { + // TWL6030 VCORE1 => VDD_MPU + // TWL6030 VCORE2 => VDD_IVA + // TWL6030 VCORE3 => VDD_CORE + + // Setup CORE voltage + VolConSetup(PMIC_SMPS_ID0_SLAVE_ADDR, + PMIC_VCORE3_CFG_FORCE_REGADDR, + PMIC_VCORE3_CFG_FORCE_VSEL); + + // Setup MPU voltage + VolConSetup(PMIC_SMPS_ID0_SLAVE_ADDR, + PMIC_VCORE1_CFG_FORCE_REGADDR, + PMIC_VCORE1_CFG_FORCE_VSEL_VDD_MPU_4430); + } + + // Setup IVA voltage + VolConSetup(PMIC_SMPS_ID0_SLAVE_ADDR, + PMIC_VCORE2_CFG_FORCE_REGADDR, + PMIC_VCORE2_CFG_FORCE_VSEL); + + // Accelerate MPU frequency + MmioWrite32 (CKGEN_CM1_CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_MPU_OPP100_VAL); + + // Accelerate CORE clocks + MmioWrite32 (CKGEN_CM1_CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_CORE_OPP100_VAL); + MmioWrite32 (CKGEN_CM1_CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_OPP100_VAL); + MmioWrite32 (CKGEN_CM1_CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_OPP100_VAL); + MmioWrite32 (CKGEN_CM1_CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_OPP100_VAL); + MmioWrite32 (CKGEN_CM1_CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_OPP100_VAL); + + // Start core frequency update + MmioWrite32 ( CKGEN_CM1_CM_SHADOW_FREQ_CONFIG1, + (CM_SHADOW_FREQ_CONFIG1_DPLL_CORE_M2_DIV_OPP100| + CM_SHADOW_FREQ_CONFIG1_DPLL_CORE_DPLL_EN_LOCK| + CM_SHADOW_FREQ_CONFIG1_DLL_RESET_RST| + CM_SHADOW_FREQ_CONFIG1_FREQ_UPDATE_START)); + + // Wait for core frequency update completion + while( (MmioRead32(CKGEN_CM1_CM_SHADOW_FREQ_CONFIG1) & (BIT0)) != 0 ); + + // Setup and lock IVA DPLL + MmioWrite32 (CKGEN_CM1_CM_CLKSEL_DPLL_IVA, + CKGEN_CM1_CM_CLKSEL_DPLL_IVA_CLKSEL_VAL); + MmioWrite32 (CKGEN_CM1_CM_DIV_M4_DPLL_IVA, + CKGEN_CM1_CM_CLKSEL_DPLL_IVA_M4_VAL); + MmioWrite32 (CKGEN_CM1_CM_DIV_M5_DPLL_IVA, + CKGEN_CM1_CM_CLKSEL_DPLL_IVA_M5_VAL); + MmioWrite32 (CKGEN_CM1_CM_BYPCLK_DPLL_IVA, + CKGEN_CM1_CM_CLKSEL_DPLL_IVA_BYCLK_VAL); + MmioWrite32 (CKGEN_CM1_CM_CLKMODE_DPLL_IVA, + CKGEN_CM1_CM_CLKSEL_DPLL_IVA_CLKMODE_VAL); + + // Setup and lock ABE DPLL + MmioWrite32 (CKGEN_CM1_CM_CLKSEL_DPLL_ABE, + CKGEN_CM1_CM_CLKSEL_DPLL_ABE_VAL); + MmioWrite32 (CKGEN_CM1_CM_DIV_M2_DPLL_ABE, + CKGEN_CM1_CM_DIV_M2_DPLL_ABE_VAL); + MmioWrite32 (CKGEN_CM1_CM_DIV_M3_DPLL_ABE, + CKGEN_CM1_CM_DIV_M3_DPLL_ABE_VAL); + MmioWrite32 (CKGEN_CM1_CM_CLKMODE_DPLL_ABE, + CKGEN_CM1_CM_CLKMODE_DPLL_ABE_VAL); + + // Setup and lock USB DPLL + MmioWrite32 (CKGEN_CM2_CM_CLKSEL_DPLL_USB, + CKGEN_CM2_CM_CLKSEL_DPLL_USB_VAL); + MmioWrite32 (CKGEN_CM2_CM_DIV_M2_DPLL_USB, + CKGEN_CM2_CM_DIV_M2_DPLL_USB_VAL); + MmioWrite32 (CKGEN_CM2_CM_CLKMODE_DPLL_USB, + CKGEN_CM2_CM_CLKMODE_DPLL_USB_VAL); + + MmioOr32 (0x4A009020, 0x100); //ISS_CLKCTRL_OPTFCLKEN + MmioOr32 (0x4A009120, 0xF00); //DSS_CLKCTRL_OPTFCLKEN + + MmioWrite32 (0x4A008900, 0x2); //cm_mpu_m3_clkstctrl: SW_WKUP + MmioWrite32 (0x4A008F00, 0x2); //cm_ivahd_clkstctrl: SW_WKUP + MmioWrite32 (0x4A004400, 0x2); //cm_dsp_clkstctrl: SW_WKUP + MmioWrite32 (0x4A009100, 0x2); //cm_dss_clkstctrl: SW_WKUP + MmioWrite32 (0x4A009200, 0x2); //cm_sgx_clkstctrl: SW_WKUP + MmioWrite32 (0x4A004500, 0x2); //cm1_abe_clkstctrl: SW_WKUP + MmioWrite32 (0x4A008C00, 0x2); //cm_c2c_clkstctrl: SW_WKUP + MmioWrite32 (0x4A009000, 0x2); //cm_cam_clkstctrl: SW_WKUP + MmioWrite32 (0x4A008A00, 0x2); //cm_sdma_clkstctrl: SW_WKUP + + MmioWrite32 (0x4A008E20, 0x1); //cm_l3instr_l3_3_clkctrl: AUTO + MmioWrite32 (0x4A008E28, 0x1); //cm_l3instr_l3_instr_clkctrl: AUTO + MmioWrite32 (0x4A008E40, 0x1); //cm_l3instr_intrconn_wp1_clkctrl: AUTO + MmioWrite32 (0x4A009338, 0x1); //cm_l3init_hsi_clkctrl: AUTO + + ClockModuleEnable (0x4A004528, 0x2); //cm1_abe_aess_clkctrl: ENABLE + + // TODO: pdm needs clock enabled externally to make it functional + MmioWrite32 (0x4A004530, 0x2); //cm1_abe_pdm_clkctrl: ENABLE + + ClockModuleEnable (0x4A004538, 0x2); //cm1_abe_dmic_clkctrl: ENABLE + ClockModuleEnable (0x4A004540, 0x2); //cm1_abe_mcasp_clkctrl: ENABLE + ClockModuleEnable (0x4A004548, 0x2); //cm1_abe_mcbsp1_clkctrl: ENABLE + ClockModuleEnable (0x4A004550, 0x2); //cm1_abe_mcbsp2_clkctrl: ENABLE + ClockModuleEnable (0x4A004558, 0x2); //cm1_abe_mcbsp3_clkctrl: ENABLE + ClockModuleEnable (0x4A004560, 0x2); //cm1_abe_slimbus_clkctrl: ENABLE + ClockModuleEnable (0x4A004568, 0x2); //cm1_abe_timer5_clkctrl: ENABLE + ClockModuleEnable (0x4A004570, 0x2); //cm1_abe_timer6_clkctrl: ENABLE + ClockModuleEnable (0x4A004578, 0x2); //cm1_abe_timer7_clkctrl: ENABLE + ClockModuleEnable (0x4A004580, 0x2); //cm1_abe_timer8_clkctrl: ENABLE + ClockModuleEnable (0x4A004588, 0x2); //cm1_abe_wdt3_clkctrl: ENABLE + ClockModuleEnable (0x4A009450, 0x2); //cm_l4per_gptimer9_clkctrl: ENABLE + ClockModuleEnable (0x4A009428, 0x2); //cm_l4per_gptimer10_clkctrl: ENABLE + ClockModuleEnable (0x4A009430, 0x2); //cm_l4per_gptimer11_clkctrl: ENABLE + ClockModuleEnable (0x4A009440, 0x2); //cm_l4per_gptimer3_clkctrl: ENABLE + ClockModuleEnable (0x4A009448, 0x2); //cm_l4per_gptimer4_clkctrl: ENABLE + ClockModuleEnable (0x4A009488, 0x2); //cm_l4per_hdq1w_clkctrl: ENABLE + ClockModuleEnable (0x4A0094E0, 0x2); //cm_l4per_mcbsp4_clkctrl: ENABLE + ClockModuleEnable (0x4A0094F8, 0x2); //cm_l4per_mcspi2_clkctrl: ENABLE + ClockModuleEnable (0x4A009500, 0x2); //cm_l4per_mcspi3_clkctrl: ENABLE + ClockModuleEnable (0x4A009508, 0x2); //cm_l4per_mcspi4_clkctrl: ENABLE + ClockModuleEnable (0x4A009520, 0x2); //cm_l4per_mmcsd3_clkctrl: ENABLE + ClockModuleEnable (0x4A009528, 0x2); //cm_l4per_mmcsd4_clkctrl: ENABLE + ClockModuleEnable (0x4A009560, 0x2); //cm_l4per_mmcsd5_clkctrl: ENABLE + ClockModuleEnable (0x4A009540, 0x2); //cm_l4per_uart1_clkctrl: ENABLE + ClockModuleEnable (0x4A009548, 0x2); //cm_l4per_uart2_clkctrl: ENABLE + ClockModuleEnable (0x4A009558, 0x2); //cm_l4per_uart4_clkctrl: ENABLE + ClockModuleEnable (0x4A009438, 0x2); //gptimer2: ENABLE + ClockModuleEnable (0x4A009460, 0x1); //gpio2: AUTO + ClockModuleEnable (0x4A009468, 0x1); //gpio3: AUTO + ClockModuleEnable (0x4A009470, 0x101); //gpio4: AUTO+FCLK + ClockModuleEnable (0x4A009478, 0x1); //gpio5: AUTO + ClockModuleEnable (0x4A009480, 0x1); //gpio6: AUTO + ClockModuleEnable (0x4A0094A8, 0x2); //i2c2: ENABLE + ClockModuleEnable (0x4A0094B0, 0x2); //i2c3: ENABLE + ClockModuleEnable (0x4A0094B8, 0x2); //i2c4: ENABLE + ClockModuleEnable (0x4A0094F0, 0x2); //mcspi1: ENABLE + ClockModuleEnable (0x4A307878, 0x2); //cm_wkup_keyboard_clkctrl: ENABLE + ClockModuleEnable (0x4A009020, 0x2); //cm_cam_iss_clkctrl: ENABLE + ClockModuleEnable (0x4A009028, 0x2); //cm_cam_fdif_clkctrl: ENABLE + ClockModuleEnable (0x4A009120, 0x2); //cm_dss_dss_clkctrl: ENABLE + ClockModuleEnable (0x4A009220, 0x2); //cm_sgx_sgx_clkctrl: ENABLE + ClockModuleEnable (0x4A009328, 0x1040002); //mmchs1: ENABLE + ClockModuleEnable (0x4A009330, 0x1040002); //mmchs2: ENABLE + ClockModuleEnable (0x4A009358, 0xFF02); //cm_l3init_hsusbhost_clkctrl: ENABLE + ClockModuleEnable (0x4A009368, 0x1); //usbtll: AUTO + + MmioWrite32 (0x4A008900, 0x3); //cm_mpu_m3_clkstctrl: HW_AUTO + MmioWrite32 (0x4A008F00, 0x3); //cm_ivahd_clkstctrl: HW_AUTO + MmioWrite32 (0x4A004400, 0x3); //cm_dsp_clkstctrl: HW_AUTO + MmioWrite32 (0x4A009100, 0x3); //cm_dss_clkstctrl: HW_AUTO + MmioWrite32 (0x4A009200, 0x3); //cm_sgx_clkstctrl: HW_AUTO + MmioWrite32 (0x4A004500, 0x3); //cm1_abe_clkstctrl: HW_AUTO + MmioWrite32 (0x4A008C00, 0x3); //cm_c2c_clkstctrl: HW_AUTO + MmioWrite32 (0x4A008A00, 0x3); //cm_sdma_clkstctrl: HW_AUTO + MmioWrite32 (0x4A009400, 0x3); //l4per: HW_AUTO + MmioWrite32 (0x4A009300, 0x3); //l3init: HW_AUTO + MmioWrite32 (0x4A008B00, 0x3); //memif: HW_AUTO + MmioWrite32 (0x4A008D00, 0x3); //l4cfg: HW_AUTO + MmioWrite32 (0x4A009000, 0x0); //cm_cam_clkstctrl: NO_SLEEP +} diff --git a/PandaBoardPkg/Library/PandaBoardLib/PadConfiguration.c b/PandaBoardPkg/Library/PandaBoardLib/PadConfiguration.c new file mode 100644 index 000000000..41dae5b4e --- /dev/null +++ b/PandaBoardPkg/Library/PandaBoardLib/PadConfiguration.c @@ -0,0 +1,343 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <PiPei.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Omap4430/Omap4430.h> +#include <PandaBoard.h> + +PAD_CONFIGURATION PadConfigurationTableSharedCore[] = { + {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ + {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ + {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ + {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ + {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ + {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ + {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ + {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ + {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ + {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ + {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ + {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ + {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ + {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ + {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ + {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ + {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ + {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ + {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ + {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ + {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ + {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ + {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ + {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ + {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ + {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ + {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ + {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ + {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ + {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ + {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ + {UART3_TX_IRTX, (M0)}, /* uart3_tx */ + {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ + {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ + {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ + {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ + {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ + {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ + {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ + {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ + {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ + {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ + {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ + {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ + {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ + {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ + {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ + {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ + {UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */ + {GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */ + {FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182: BOARD_ID0 */ + {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ + {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ + {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ + {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ + {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ + {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ + {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ + {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ + {GPMC_A16, (M3)}, /* gpio_40 */ + {GPMC_A17, (PTD | M3)}, /* gpio_41 */ + {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ + {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ + {GPMC_A20, (IEN | M3)}, /* gpio_44 */ + {GPMC_A21, (M3)}, /* gpio_45 */ + {GPMC_A22, (M3)}, /* gpio_46 */ + {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ + {GPMC_A24, (PTD | M3)}, /* gpio_48: BOARD_ID1 (Panda ES only) */ + {GPMC_A25, (PTD | M3)}, /* gpio_49 */ + {GPMC_NCS0, (M3)}, /* gpio_50 */ + {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ + {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ + {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ + {GPMC_NWP, (M3)}, /* gpio_54 */ + {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ + {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ + {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ + {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ + {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ + {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ + {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101: BOARD_ID1 (Panda only) */ + {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ + {C2C_DATA14, (M1)}, /* dsi2_te0 */ + {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ + {HDMI_HPD, (M0)}, /* hdmi_hpd */ + {HDMI_CEC, (M0)}, /* hdmi_cec */ + {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ + {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ + {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ + {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ + {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ + {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ + {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ + {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ + {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ + {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ + {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ + {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ + {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ + {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ + {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ + {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ + {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ + {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ + {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ + {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ + {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ + {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ + {ABE_MCBSP1_CLKX, (IEN | M0)}, /* abe_mcbsp1_clkx */ + {ABE_MCBSP1_DR, (IEN | M0)}, /* abe_mcbsp1_dr */ + {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ + {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ + {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ + {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ + {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ + {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ + {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ + {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ + {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ + {ABE_DMIC_DIN2, (PTU | IEN | M3)}, /* gpio_121 */ + {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ + {UART2_CTS, (PTU | IEN | M7)}, /* uart2_cts */ + {UART2_RTS, (M7)}, /* uart2_rts */ + {UART2_RX, (PTU | IEN | M7)}, /* uart2_rx */ + {UART2_TX, (M7)}, /* uart2_tx */ + {HDQ_SIO, (M3)}, /* gpio_127 */ + {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ + {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ + {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ + {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ + {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ + {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ + {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ + {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ + {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ + {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ + {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ + {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ + {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ + {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ + {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ + {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ + {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ + {UART4_RX, (IEN | M0)}, /* uart4_rx */ + {UART4_TX, (M0)}, /* uart4_tx */ + {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */ + {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ + {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ + {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ + {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ + {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ + {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ + {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ + {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ + {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ + {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ + {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ + {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ + {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ + {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */ + {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ + {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ + {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3: BOARD_ID2 (gpio_171) */ + {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */ + {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ + {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3 | DIS)}, /* kpd_row1: BOARD_ID4 (gpio_2) */ + {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3 | DIS)}, /* kpd_row2: BOARD_ID3 (gpio_3) */ + {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ + {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ + {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ + {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ + {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ + {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ + {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ + {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ + {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ + {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ + {SYS_BOOT1, (M3)}, /* gpio_185 */ + {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ + {SYS_BOOT3, (M3)}, /* gpio_187 */ + {SYS_BOOT4, (M3)}, /* gpio_188 */ + {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ + {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ + {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ + {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ + {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ + {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ + {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ + {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ + {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ + {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ + {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ + {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ + {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ + {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ + {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ + {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ + {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ + {DPM_EMU16, (M3)}, /* gpio_27 */ + {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ + {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ + {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ +}; + +PAD_CONFIGURATION PadConfigurationTableSharedWkup[] = { + {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ + {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ + {PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */ + {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ + {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ + {PAD1_SIM_CLK, (M0)}, /* sim_clk */ + {PAD0_SIM_RESET, (M0)}, /* sim_reset */ + {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ + {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ + {PAD1_FREF_XTAL_IN, (M0)}, /* # */ + {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ + {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ + {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ + {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ + {PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */ + {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ + {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ + {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ + {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ + {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ + {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ +}; + +PAD_CONFIGURATION PadConfigurationTable4430Core[] = { + {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ +}; + +PAD_CONFIGURATION PadConfigurationTable4430Wkup[] = { + {PAD1_FREF_CLK4_REQ, (PTU | M3)}, /* led status_1 */ +}; + +PAD_CONFIGURATION PadConfigurationTable4460Core[] = { + {ABE_MCBSP2_CLKX, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */ +}; + +PAD_CONFIGURATION PadConfigurationTable4460Wkup[] = { + {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */ +}; + +VOID +PadConfiguration ( + PANDABOARD_REVISION BoardRevision + ) +{ + UINTN Index; + UINTN NumPinsToConfigure; + + // Calculate number of pins for core domain + NumPinsToConfigure = sizeof(PadConfigurationTableSharedCore) / sizeof(PAD_CONFIGURATION); + + for (Index = 0; Index < NumPinsToConfigure; Index++) { + // Configure the pin with specific Pad configuration. + MmioWrite16((OMAP4430_CONTROL_MODULE_CORE_BASE+PadConfigurationTableSharedCore[Index].Off), + PadConfigurationTableSharedCore[Index].Val); + } + + // Calculate number of pins for wkup domain + NumPinsToConfigure = sizeof(PadConfigurationTableSharedWkup) / sizeof(PAD_CONFIGURATION); + + for (Index = 0; Index < NumPinsToConfigure; Index++) { + // Configure the pin with specific Pad configuration. + MmioWrite16((OMAP4430_CONTROL_MODULE_WKUP_BASE+PadConfigurationTableSharedWkup[Index].Off), + PadConfigurationTableSharedWkup[Index].Val); + } + + // If PandaBoard-ES + if( BoardRevision == PANDABOARD_REVISION_PANDAES ) { + // Calculate number of pins for core domain + NumPinsToConfigure = sizeof(PadConfigurationTable4460Core) / sizeof(PAD_CONFIGURATION); + + for (Index = 0; Index < NumPinsToConfigure; Index++) { + // Configure the pin with specific Pad configuration. + MmioWrite16((OMAP4430_CONTROL_MODULE_CORE_BASE+PadConfigurationTable4460Core[Index].Off), + PadConfigurationTable4460Core[Index].Val); + } + + // Calculate number of pins for wkup domain + NumPinsToConfigure = sizeof(PadConfigurationTable4460Wkup) / sizeof(PAD_CONFIGURATION); + + for (Index = 0; Index < NumPinsToConfigure; Index++) { + // Configure the pin with specific Pad configuration. + MmioWrite16((OMAP4430_CONTROL_MODULE_WKUP_BASE+PadConfigurationTable4460Wkup[Index].Off), + PadConfigurationTable4460Wkup[Index].Val); + } + } + else { + // Calculate number of pins for core domain + NumPinsToConfigure = sizeof(PadConfigurationTable4430Core) / sizeof(PAD_CONFIGURATION); + + for (Index = 0; Index < NumPinsToConfigure; Index++) { + // Configure the pin with specific Pad configuration. + MmioWrite16((OMAP4430_CONTROL_MODULE_CORE_BASE+PadConfigurationTable4430Core[Index].Off), + PadConfigurationTable4430Core[Index].Val); + } + + // Calculate number of pins for wkup domain + NumPinsToConfigure = sizeof(PadConfigurationTable4430Wkup) / sizeof(PAD_CONFIGURATION); + + for (Index = 0; Index < NumPinsToConfigure; Index++) { + // Configure the pin with specific Pad configuration. + MmioWrite16((OMAP4430_CONTROL_MODULE_WKUP_BASE+PadConfigurationTable4430Wkup[Index].Off), + PadConfigurationTable4430Wkup[Index].Val); + } + } + + // EMIF pads + MmioWrite32 (0x4A100638, 0x7c7c7c7c); + MmioWrite32 (0x4A10063C, 0x7c7c7c7c); + MmioWrite32 (0x4A100640, 0x7C787C00); + MmioWrite32 (0x4A100644, 0xA0888C0F); + + MmioWrite32 (0x4A100648, 0x7C7C7C7C); + MmioWrite32 (0x4A10064C, 0x7C7C7C7C); + MmioWrite32 (0x4A100650, 0x7C787C00); + MmioWrite32 (0x4A100654, 0xA0888C0F); + +} diff --git a/PandaBoardPkg/Library/PandaBoardLib/PandaBoard.c b/PandaBoardPkg/Library/PandaBoardLib/PandaBoard.c new file mode 100644 index 000000000..cec10b1a3 --- /dev/null +++ b/PandaBoardPkg/Library/PandaBoardLib/PandaBoard.c @@ -0,0 +1,200 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/IoLib.h> +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> + +#include <Ppi/ArmMpCoreInfo.h> + +#include <Omap4430/Omap4430.h> +#include <PandaBoard.h> + +ARM_CORE_INFO mVersatileExpressMpCoreInfoPandaBoard[] = { + { + // Cluster 0, Core 0 + 0x0, 0x0, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0x80000000, + (EFI_PHYSICAL_ADDRESS)0x80000000, + (EFI_PHYSICAL_ADDRESS)0x80000000, + (UINT64)0 + }, + { + // Cluster 0, Core 1 + 0x0, 0x1, + + // MP Core MailBox Set/Get/Clear Addresses and Clear Value + (EFI_PHYSICAL_ADDRESS)0x80000000, + (EFI_PHYSICAL_ADDRESS)0x80000000, + (EFI_PHYSICAL_ADDRESS)0x80000000, + (UINT64)0 + } +}; + +VOID +PadConfiguration ( + PANDABOARD_REVISION BoardRevision + ); + +VOID +ClockInit ( + PANDABOARD_REVISION BoardRevision + ); + +/** + Detect board revision + + @return Board revision +**/ +PANDABOARD_REVISION +PandaBoardGetBoardRevision ( + VOID + ) +{ + UINT32 Revision; + + // If Chip Id code matches 4460 processor + if( ((MmioRead32(CONTROL_CORE_ID_CODE)>>16)&0xFFF) == 0xb94 ) { + Revision = PANDABOARD_REVISION_PANDAES; + } + else { + // Assume 4430 + Revision = PANDABOARD_REVISION_PANDA; + } + + return Revision; +} + +/** + Remap the memory at 0x0 + + Some platform requires or gives the ability to remap the memory at the address 0x0. + This function can do nothing if this feature is not relevant to your platform. + +**/ +VOID +ArmPlatformBootRemapping ( + VOID + ) +{ + // Do nothing for the PandaBoard +} + +/** + Return the current Boot Mode + + This function returns the boot reason on the platform + +**/ +EFI_BOOT_MODE +ArmPlatformGetBootMode ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + +/** + Early board setup + +**/ +RETURN_STATUS +ArmPlatformInitialize ( + IN UINTN MpId + ) +{ + PANDABOARD_REVISION Revision; + + // Get chip version + Revision = PandaBoardGetBoardRevision(); + + // Set up Pin muxing. + PadConfiguration (Revision); + + // Set up system clocking + ClockInit (Revision); + + // Make sure GPMC region region 0 is disabled + // Not doing so makes gpmc_init hang early in kernel init + MmioAnd32 (GPMC_CONFIG7_0, ~CSVALID); + + return RETURN_SUCCESS; +} + +/** + Initialize the system (or sometimes called permanent) memory + + This memory is generally represented by the DRAM. + +**/ +VOID +ArmPlatformInitializeSystemMemory ( + VOID + ) +{ + // Nothing done here, handled by the ROM Configuration Header + +} + +EFI_STATUS +PrePeiCoreGetMpCoreInfo ( + OUT UINTN *CoreCount, + OUT ARM_CORE_INFO **ArmCoreTable + ) +{ + *CoreCount = sizeof(mVersatileExpressMpCoreInfoPandaBoard) / sizeof(ARM_CORE_INFO); + *ArmCoreTable = mVersatileExpressMpCoreInfoPandaBoard; + + return EFI_SUCCESS; +} + +// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore +EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID; +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; + +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &mArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi + } +}; + +VOID +ArmPlatformGetPlatformPpiList ( + OUT UINTN *PpiListSize, + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList + ) +{ + *PpiListSize = sizeof(gPlatformPpiTable); + *PpiList = gPlatformPpiTable; +} + +/** + Initialize the Secure peripherals and memory regions + + If Trustzone is supported by your platform then this function makes the required initialization + of the secure peripherals and memory regions. + +**/ +VOID +ArmPlatformSecTrustzoneInit ( + IN UINTN MpId + ) +{ +} + diff --git a/PandaBoardPkg/Library/PandaBoardLib/PandaBoardHelper.S b/PandaBoardPkg/Library/PandaBoardLib/PandaBoardHelper.S new file mode 100644 index 000000000..6f21ed08a --- /dev/null +++ b/PandaBoardPkg/Library/PandaBoardLib/PandaBoardHelper.S @@ -0,0 +1,129 @@ +// +// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include <AsmMacroIoLib.h> +#include <Base.h> +#include <Library/PcdLib.h> +#include <PandaBoard.h> +#include <AutoGen.h> + +.text +.align 3 + +GCC_ASM_EXPORT(ArmPlatformPrePiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) + +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) + +/** + ArmPlatformPrePiBootAction + +**/ +ASM_PFX(ArmPlatformPrePiBootAction): + //relocate the relocator + sub r12,r12 + orr r12,r12,#0x80000000 + mov r3,r12 // relocator target address (0x80000000) + ldr r0, =relocator_start // relocator code start addr + ldr r1, =relocator_end // relocator end addr + sub r1,r1,r0 // compute relocator code size + lsr r1,r1,#0x2 // size in words +reloc_loop_reloc: // copy relocator + ldm r0!,{r2} + stm r3!,{r2} + subs r1,r1,#0x1 + bne reloc_loop_reloc + + // get chip id code + ldr r2,=0x4a002206 // control module id code address + ldrh r2,[r2] // get higher order 16b + lsl r2,r2,#0x14 + ldr r1,=0xb9400000 // compare with 4460 id + cmp r1,r2 // Z bit set if 4460 + + // update dmm conf + mov r0,#0x4e + lsl r0,r0,#0x18 // load DMM LISA base address + ldr r2,=0x482af000 // load MA LISA base address + ldr r1,[r0,#0x40] // get DMM LISA section 0 + str r1,[r0,#0x4c] // update DMM LISA section 3 + streq r1,[r2,#0x4c] // update MA LISA section 3 (when Z=1: 4460 only) + ldr r1,=0xff020100 // prepare LISA section 0 + str r1,[r0,#0x40] // update DMM LISA section 0 + streq r1,[r2,#0x40] // update MA LISA section 0 (when Z set: 4460 only) + bx r12 // jump to relocator + +relocator_start: + // update emif conf. + sub r2,r0,#0x1000000 + sub r1,r2,#0x1000000 + mov r0,#0x10 + str r0,[r1,#0xc] + str r0,[r2,#0xc] + ldr r0,[r1,#0x8] + orr r0,r0,#0x8 + str r0,[r1,#0x8] + str r0,[r2,#0x8] + + // copy + add r1,r12,#0x8000 + add r0,r1,#0x8000 + mov r10,#0x1 + lsl r11,r10,#0x5 +reloc_loop_1M: + lsl r10,r10,#0xA +reloc_loop_4K: + ldm r0!,{r2-r9} + stm r1!,{r2-r9} + subs r10,r10,#1 + bne reloc_loop_4K + add r0,r0,#0x8000 + subs r11,r11,#1 + add r10,r10,#0x1 + bne reloc_loop_1M + bx lr +relocator_end: + +//UINTN +//ArmPlatformGetCorePosition ( +// IN UINTN MpId +// ); +ASM_PFX(ArmPlatformGetCorePosition): + bx lr + +ASM_PFX(ArmPlatformIsPrimaryCore): + #Bits 8 through 11 are CPU ID + ldr r1, =0xf00 + and r0, r0, r1 + #id for core0 should be 0 + ldr r1, =0x0 + cmp r0, r1 + moveq r0, #1 + movne r0, #0 + mov pc, lr + +ASM_PFX(ArmPlatformPeiBootAction): + mov pc, lr + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED + +//UINTN +//ArmPlatformGetPrimaryCoreMpId ( +// VOID +// ); +ASM_PFX(ArmPlatformGetPrimaryCoreMpId): + LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0) + ldr r0, [r0] + bx lr diff --git a/PandaBoardPkg/Library/PandaBoardLib/PandaBoardHelper.asm b/PandaBoardPkg/Library/PandaBoardLib/PandaBoardHelper.asm new file mode 100755 index 000000000..f5fb53ab5 --- /dev/null +++ b/PandaBoardPkg/Library/PandaBoardLib/PandaBoardHelper.asm @@ -0,0 +1,58 @@ +// +// Copyright (c) 2011, ARM Limited. All rights reserved. +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +// + +#include <AsmMacroIoLib.h> +#include <Base.h> +#include <Library/PcdLib.h> +#include <PandaBoard.h> +#include <AutoGen.h> + + INCLUDE AsmMacroIoLib.inc + + EXPORT ArmPlatformIsBootMemoryInitialized + EXPORT ArmPlatformInitializeBootMemory + + PRESERVE8 + AREA PandaBoardHelper, CODE, READONLY + +/** + Called at the early stage of the Boot phase to know if the memory has already been initialized + + Running the code from the reset vector does not mean we start from cold boot. In some case, we + can go through this code with the memory already initialized. + Because this function is called at the early stage, the implementation must not use the stack. + Its implementation must probably done in assembly to ensure this requirement. + + @return Return a non zero value if initialized + +**/ +ArmPlatformIsBootMemoryInitialized + // The system memory is initialized by the PandaBoard firmware + mov r0, #1 + bx lr + +/** + Initialize the memory where the initial stacks will reside + + This memory can contain the initial stacks (Secure and Secure Monitor stacks). + In some platform, this region is already initialized and the implementation of this function can + do nothing. This memory can also represent the Secure RAM. + This function is called before the satck has been set up. Its implementation must ensure the stack + pointer is not used (probably required to use assembly language) + +**/ +ArmPlatformInitializeBootMemory + // We must need to go into this function + bx lr + + END diff --git a/PandaBoardPkg/Library/PandaBoardLib/PandaBoardLib.inf b/PandaBoardPkg/Library/PandaBoardLib/PandaBoardLib.inf new file mode 100755 index 000000000..3028cba23 --- /dev/null +++ b/PandaBoardPkg/Library/PandaBoardLib/PandaBoardLib.inf @@ -0,0 +1,55 @@ +#/* @file +# Copyright (c) 2011, ARM Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#*/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardLib + FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmPlatformLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + PandaBoardPkg/PandaBoardPkg.dec + +[LibraryClasses] + IoLib + ArmLib +# OmapLib + MemoryAllocationLib + +[Sources.common] + PandaBoard.c + PandaBoardMem.c + PandaBoardHelper.asm | RVCT + PandaBoardHelper.S | GCC + PadConfiguration.c + Clock.c + +[Protocols] + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + + gArmTokenSpaceGuid.PcdSystemMemoryBase + gArmTokenSpaceGuid.PcdSystemMemorySize diff --git a/PandaBoardPkg/Library/PandaBoardLib/PandaBoardMem.c b/PandaBoardPkg/Library/PandaBoardLib/PandaBoardMem.c new file mode 100755 index 000000000..fe082c2a6 --- /dev/null +++ b/PandaBoardPkg/Library/PandaBoardLib/PandaBoardMem.c @@ -0,0 +1,102 @@ +/** @file +* +* Copyright (c) 2011, ARM Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include <Library/ArmPlatformLib.h> +#include <Library/DebugLib.h> +#include <Library/PcdLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/IoLib.h> + +#include <PandaBoard.h> + +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 4 + +/** + Return the Virtual Memory Map of your platform + + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. + + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- + Virtual Memory mapping. This array must be ended by a zero-filled + entry + +**/ +VOID +ArmPlatformGetVirtualMemoryMap ( + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap + ) +{ + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; + UINTN Index = 0; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + ASSERT(VirtualMemoryMap != NULL); + + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); + if (VirtualMemoryTable == NULL) { + return; + } + + if (FeaturePcdGet(PcdCacheEnable) == TRUE) { + CacheAttributes = DDR_ATTRIBUTES_CACHED; + } else { + CacheAttributes = DDR_ATTRIBUTES_UNCACHED; + } + + // ReMap (Either NOR Flash or DRAM) + VirtualMemoryTable[Index].PhysicalBase = PcdGet64(PcdSystemMemoryBase); + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdSystemMemoryBase); + VirtualMemoryTable[Index].Length = PcdGet64(PcdSystemMemorySize); + VirtualMemoryTable[Index].Attributes = CacheAttributes; + + // SOC Registers. L3 interconnects + VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE; + VirtualMemoryTable[Index].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE; + VirtualMemoryTable[Index].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH; + VirtualMemoryTable[Index].Attributes = SOC_REGISTERS_L3_ATTRIBUTES; + + // SOC Registers. L4 interconnects + VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE; + VirtualMemoryTable[Index].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE; + VirtualMemoryTable[Index].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH; + VirtualMemoryTable[Index].Attributes = SOC_REGISTERS_L4_ATTRIBUTES; + + // End of Table + VirtualMemoryTable[++Index].PhysicalBase = 0; + VirtualMemoryTable[Index].VirtualBase = 0; + VirtualMemoryTable[Index].Length = 0; + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); + + *VirtualMemoryMap = VirtualMemoryTable; +} + +/** + Return the EFI Memory Map of your platform + + This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource + Descriptor HOBs used by DXE core. + + @param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an + EFI Memory region. This array must be ended by a zero-filled entry + +**/ +EFI_STATUS +ArmPlatformGetAdditionalSystemMemory ( + OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap + ) +{ + return EFI_UNSUPPORTED; +} diff --git a/PandaBoardPkg/Library/ResetSystemLib/ResetSystemLib.c b/PandaBoardPkg/Library/ResetSystemLib/ResetSystemLib.c new file mode 100644 index 000000000..fa0877a5e --- /dev/null +++ b/PandaBoardPkg/Library/ResetSystemLib/ResetSystemLib.c @@ -0,0 +1,165 @@ +/** @file + Do a generic Cold Reset for PandaBoard specific Warm reset + + Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + + +#include <Uefi.h> + +#include <Library/ArmLib.h> +#include <Library/CacheMaintenanceLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/IoLib.h> +#include <Library/PcdLib.h> +#include <Library/DebugLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#include <Omap4430/Omap4430.h> + + +VOID +ShutdownEfi ( + VOID + ) +{ + EFI_STATUS Status; + UINTN MemoryMapSize; + EFI_MEMORY_DESCRIPTOR *MemoryMap; + UINTN MapKey; + UINTN DescriptorSize; + UINTN DescriptorVersion; + UINTN Pages; + + MemoryMap = NULL; + MemoryMapSize = 0; + do { + Status = gBS->GetMemoryMap ( + &MemoryMapSize, + MemoryMap, + &MapKey, + &DescriptorSize, + &DescriptorVersion + ); + if (Status == EFI_BUFFER_TOO_SMALL) { + + Pages = EFI_SIZE_TO_PAGES (MemoryMapSize) + 1; + MemoryMap = AllocatePages (Pages); + + // + // Get System MemoryMap + // + Status = gBS->GetMemoryMap ( + &MemoryMapSize, + MemoryMap, + &MapKey, + &DescriptorSize, + &DescriptorVersion + ); + // Don't do anything between the GetMemoryMap() and ExitBootServices() + if (!EFI_ERROR (Status)) { + Status = gBS->ExitBootServices (gImageHandle, MapKey); + if (EFI_ERROR (Status)) { + FreePages (MemoryMap, Pages); + MemoryMap = NULL; + MemoryMapSize = 0; + } + } + } + } while (EFI_ERROR (Status)); + + //Clean and invalidate caches. + WriteBackInvalidateDataCache(); + InvalidateInstructionCache(); + + //Turning off Caches and MMU + ArmDisableDataCache (); + ArmDisableInstructionCache (); + ArmDisableMmu (); +} + +typedef +VOID +(EFIAPI *CALL_STUB)( + VOID +); + + +/** + Resets the entire platform. + + @param ResetType The type of reset to perform. + @param ResetStatus The status code for the reset. + @param DataSize The size, in bytes, of WatchdogData. + @param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or + EfiResetShutdown the data buffer starts with a Null-terminated + Unicode string, optionally followed by additional binary data. + +**/ +EFI_STATUS +EFIAPI +LibResetSystem ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN CHAR16 *ResetData OPTIONAL + ) +{ + CALL_STUB StartOfFv; + + if (ResetData != NULL) { + DEBUG((EFI_D_ERROR, "%s", ResetData)); + } + + ShutdownEfi (); + + switch (ResetType) { + case EfiResetWarm: + //Perform warm reset of the system by jumping to the begining of the FV + StartOfFv = (CALL_STUB)(UINTN)PcdGet32(PcdFvBaseAddress); + StartOfFv (); + break; + case EfiResetCold: + case EfiResetShutdown: + default: + //Perform cold reset of the system. + MmioOr32 (PRM_RSTCTRL, PRM_RSTCTRL_RST_GLOBAL_COLD_SW_VAL); + while ((MmioRead32(PRM_RSTST) & PRM_RSTST_GLOBAL_COLD_RST_MASK) != 0x1); + break; + } + + // If the reset didn't work, return an error. + ASSERT (FALSE); + return EFI_DEVICE_ERROR; +} + + + +/** + Initialize any infrastructure required for LibResetSystem () to function. + + @param ImageHandle The firmware allocated handle for the EFI image. + @param SystemTable A pointer to the EFI System Table. + + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS. + +**/ +EFI_STATUS +EFIAPI +LibInitializeResetSystem ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + return EFI_SUCCESS; +} + diff --git a/PandaBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf b/PandaBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf new file mode 100644 index 000000000..31f7e094c --- /dev/null +++ b/PandaBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf @@ -0,0 +1,49 @@ +#/** @file +# Reset System lib to make it easy to port new platforms +# +# Copyright (c) 2008, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardResetSystemLib + FILE_GUID = 781371a2-3fdd-41d4-96a1-7b34cbc9e895 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = EfiResetSystemLib + + +[Sources.common] + ResetSystemLib.c + +[Packages] + MdePkg/MdePkg.dec + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + +[Pcd.common] + gArmTokenSpaceGuid.PcdCpuResetAddress + gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress + +[LibraryClasses] + DebugLib + ArmLib + CacheMaintenanceLib + MemoryAllocationLib + UefiRuntimeServicesTableLib + TimerLib + UefiLib + UefiBootServicesTableLib + +[Pcd] + gArmTokenSpaceGuid.PcdFvBaseAddress diff --git a/PandaBoardPkg/PandaBoardPkg.dec b/PandaBoardPkg/PandaBoardPkg.dec new file mode 100644 index 000000000..595bcc68d --- /dev/null +++ b/PandaBoardPkg/PandaBoardPkg.dec @@ -0,0 +1,36 @@ +#/** @file +# Panda board package. +# +# Copyright (c) 2009, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials are licensed and made available under +# the terms and conditions of the BSD License which accompanies this distribution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = PandaBoardPkg + PACKAGE_GUID = 6eba6648-d853-4eb3-9761-528b82d5ab04 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ +[Includes.common] + Include # Root include for the package + +[Guids.common] + gPandaBoardTokenSpaceGuid = { 0x6834fe45, 0x4aee, 0x4fc6, { 0xbc, 0xb5, 0xff, 0x45, 0xb7, 0xa8, 0x71, 0xe2 } } + diff --git a/PandaBoardPkg/PandaBoardPkg.dsc b/PandaBoardPkg/PandaBoardPkg.dsc new file mode 100644 index 000000000..f6d05c4c0 --- /dev/null +++ b/PandaBoardPkg/PandaBoardPkg.dsc @@ -0,0 +1,495 @@ +#/** @file +# Panda board package. +# +# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PLATFORM_NAME = PandaBoardPkg + PLATFORM_GUID = 49aefbb9-652c-4396-ac95-b9363cffce92 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010005 + OUTPUT_DIRECTORY = Build/PandaBoard + SUPPORTED_ARCHITECTURES = ARM + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = PandaBoardPkg/PandaBoardPkg.fdf + + +[LibraryClasses.common] + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf + ArmPlatformLib|PandaBoardPkg/Library/PandaBoardLib/PandaBoardLib.inf + ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf + ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf + ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf + ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf + + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf + +!if $(TARGET) == RELEASE + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf +# UncachedMemoryAllocationLib|ArmPkg/Library/DebugUncachedMemoryAllocationLib/DebugUncachedMemoryAllocationLib.inf +!endif + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf + + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|ArmPkg/Library/BaseMemoryLibStm/BaseMemoryLibStm.inf + + EfiResetSystemLib|PandaBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf + + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + + EblCmdLib|ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.inf + FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf + + EfiFileLib|EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf + + + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf + + # + # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window + # in the debugger will show load and unload commands for symbols. You can cut and paste this + # into the command window to load symbols. We should be able to use a script to do this, but + # the version of RVD I have does not support scipts accessing system memory. + # +# PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf + PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf +# PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf + + + CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf + DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf + CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibNull.inf + PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf + + SerialPortLib|Omap44xxPkg/Library/SerialPortLib/SerialPortLib.inf + SerialPortExtLib|EmbeddedPkg/Library/TemplateSerialPortExtLib/TemplateSerialPortExtLib.inf + SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf + + RealTimeClockLib|Omap44xxPkg/Library/RealTimeClockLib/RealTimeClockLib.inf + + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf + + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf + +# +# Assume everything is fixed at build +# + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + EblAddExternalCommandLib|EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf + + + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + + TimerLib|Omap44xxPkg/Library/Omap44xxTimerLib/Omap44xxTimerLib.inf + OmapLib|Omap44xxPkg/Library/OmapLib/OmapLib.inf + OmapDmaLib|Omap44xxPkg/Library/OmapDmaLib/OmapDmaLib.inf + EblNetworkLib|EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf + DebugAgentTimerLib|Omap44xxPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf + + GdbSerialLib|Omap44xxPkg/Library/GdbSerialLib/GdbSerialLib.inf + ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf + DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf + + BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf + +[LibraryClasses.common.SEC] + ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf + ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf + LzmaDecompressLib|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + + # Temp work around for Movt relocation issue. + #PeCoffLib|ArmPkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + + HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf + PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf + MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf + PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf + MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf + + # 1/123 faster than Stm or Vstm version + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + + # Uncomment to turn on GDB stub in SEC. + #DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf + +[LibraryClasses.common.PEI_CORE] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf + +[LibraryClasses.common.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf +# PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeCoffLib|EmbeddedPkg/Library/DxeHobPeCoffLib/DxeHobPeCoffLib.inf + + PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf + + +[LibraryClasses.common.DXE_DRIVER] + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/Dxe/DxeArmPlatformGlobalVariableLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf + PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf + ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf +# PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeCoffLib|EmbeddedPkg/Library/DxeHobPeCoffLib/DxeHobPeCoffLib.inf + + +[LibraryClasses.ARM] + # + # It is not possible to prevent the ARM compiler for generic intrinsic functions. + # This library provides the instrinsic functions generate by a given compiler. + # [LibraryClasses.ARM] and NULL mean link this library into all ARM images. + # + NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf + + +[BuildOptions] + XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7 + + GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a + + RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8 + +################################################################################ +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +################################################################################ + +[PcdsFeatureFlag.common] + gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE + gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE + + # + # Control what commands are supported from the UI + # Turn these on and off to add features or save size + # + gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE + gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE + gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE + + gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE + + # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress + gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE + + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE + gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE + + ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe. + # It could be set FALSE to save size. + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + +[PcdsFixedAtBuild.common] + gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Panda Board" + + gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"PandaEdk2" + gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|32 + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0 + gArmPlatformTokenSpaceGuid.PcdCoreCount|2 + gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 + gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000 + gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1 + gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0 + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320 + +# DEBUG_ASSERT_ENABLED 0x01 +# DEBUG_PRINT_ENABLED 0x02 +# DEBUG_CODE_ENABLED 0x04 +# CLEAR_MEMORY_ENABLED 0x08 +# ASSERT_BREAKPOINT_ENABLED 0x10 +# ASSERT_DEADLOOP_ENABLED 0x20 +!if $(TARGET) == RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f +!endif + +# DEBUG_INIT 0x00000001 // Initialization +# DEBUG_WARN 0x00000002 // Warnings +# DEBUG_LOAD 0x00000004 // Load events +# DEBUG_FS 0x00000008 // EFI File system +# DEBUG_POOL 0x00000010 // Alloc & Free's +# DEBUG_PAGE 0x00000020 // Alloc & Free's +# DEBUG_INFO 0x00000040 // Verbose +# DEBUG_DISPATCH 0x00000080 // PEI/DXE Dispatchers +# DEBUG_VARIABLE 0x00000100 // Variable +# DEBUG_BM 0x00000400 // Boot Manager +# DEBUG_BLKIO 0x00001000 // BlkIo Driver +# DEBUG_NET 0x00004000 // SNI Driver +# DEBUG_UNDI 0x00010000 // UNDI Driver +# DEBUG_LOADFILE 0x00020000 // UNDI Driver +# DEBUG_EVENT 0x00080000 // Event messages +# DEBUG_ERROR 0x80000000 // Error + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + + gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|"" + gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07 + gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000 + +# +# Optional feature to help prevent EFI memory map fragments +# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob +# Values are in EFI Pages (4K). DXE Core will make sure that +# at least this much of each type of memory can be allocated +# from a single memory range. This way you only end up with +# maximum of two fragements for each type in the memory map +# (the memory used, and the free memory that was prereserved +# but not used). +# + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|40 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|3000 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|10 + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0 + + +# +# Panda board Specific PCDs +# + gArmTokenSpaceGuid.PcdVFPEnabled|1 + + gEmbeddedTokenSpaceGuid.PcdPrePiHobBase|0x80001000 + gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x87FE0000 # stack at top of memory + gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0x20000 # 128K stack + + # ARM Gic base addresses + gArmTokenSpaceGuid.PcdGicDistributorBase|0x48241000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x48240100 + + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x08000000 + + # Size of the region used by UEFI in permanent memory (Reserved 16MB) + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x01000000 + + # Size of the region reserved for fixed address allocations (Reserved 32MB) + gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x02000000 + + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80008000 + gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000 + + gEmbeddedTokenSpaceGuid.PcdTimerPeriod|100000 + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterPeriodInNanoseconds|26 + gEmbeddedTokenSpaceGuid.PcdEmbeddedPerformanceCounterFrequencyInHz|38400000 + + # + # ARM Pcds + # + gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000 + + gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from SD" + gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uImage" + gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/board.dtb" + gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/uInitrd" + gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"console=ttyO2,115200n8 root=/dev/mmcblk0p2 rootwait ro fixrtc nocompcache vram=48M omapfb.vram=0:24M" + + gArmPlatformTokenSpaceGuid.PcdDefaultBootType|2 + gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|3 + + gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(E68088EF-D1A4-4336-C1DB-4D3A204730A6)" + gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()" + + # + # ARM OS Loader + # + # PandaBoard machine type required for ARM Linux: + gArmTokenSpaceGuid.PcdArmMachineType|2791 + +################################################################################ +# +# Components Section - list of all EDK II Modules needed by this Platform +# +################################################################################ +[Components.common] + + # + # SEC + # + ArmPlatformPkg/PrePi/PeiMPCore.inf + + # + # DXE + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + <LibraryClasses> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf +# NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf + NULL|EmbeddedPkg/Library/LzmaHobCustomDecompressLib/LzmaHobCustomDecompressLib.inf + } + + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + EmbeddedPkg/SerialDxe/SerialDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf +# +# This version uses semi-hosting console +# EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf { +# <LibraryClasses> +# SerialPortLib|ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf +# } + + EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # USB + # + Omap44xxPkg/PciEmulation/PciEmulation.inf + + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf { + <PcdsFixedAtBuild> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x800fffff + } + + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # MMC/SD + # + EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf + Omap44xxPkg/MmcHostDxe/MmcHostDxe.inf + + # + # I2C + # + Omap44xxPkg/SmbusDxe/Smbus.inf + + # + # SoC Drivers + # + Omap44xxPkg/Gpio/Gpio.inf + Omap44xxPkg/TimerDxe/TimerDxe.inf + Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf + + # + # Power IC + # + Omap44xxPkg/TWL6030Dxe/TWL6030.inf + + # + # Application + # + EmbeddedPkg/Ebl/Ebl.inf + + # + # Bds + # + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + ArmPlatformPkg/Bds/Bds.inf + + # + # Example Application + # + MdeModulePkg/Application/HelloWorld/HelloWorld.inf + diff --git a/PandaBoardPkg/PandaBoardPkg.fdf b/PandaBoardPkg/PandaBoardPkg.fdf new file mode 100644 index 000000000..d78dea9d3 --- /dev/null +++ b/PandaBoardPkg/PandaBoardPkg.fdf @@ -0,0 +1,300 @@ +# FLASH layout file for Panda board. +# +# Copyright (c) 2009, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + + +[FD.PandaBoard_EFI] +BaseAddress = 0x80008000|gArmTokenSpaceGuid.PcdFdBaseAddress #The base address of the FLASH Device. +Size = 0x00100000|gArmTokenSpaceGuid.PcdFdSize #The size in bytes of the FLASH Device +ErasePolarity = 1 +BlockSize = 0x1 +NumBlocks = 0x100000 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType <FV, DATA, or FILE> +# +################################################################################ +!if $(EDK2_SECOND_STAGE_BOOTOLADER) == 1 +0x00000000|0x00100000 +!else +# 512 bytes of configuration header & 8 bytes of image header +0x00000000|0x00000208 + +0x00000208|0x000FFDF8 +!endif +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x1 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF EmbeddedPkg/SerialDxe/SerialDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + + INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + # + # MMC/SD + # + INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf + INF Omap44xxPkg/MmcHostDxe/MmcHostDxe.inf + + # + # I2C + # + INF Omap44xxPkg/SmbusDxe/Smbus.inf + + # + # SoC Drivers + # + INF Omap44xxPkg/Gpio/Gpio.inf + INF Omap44xxPkg/TimerDxe/TimerDxe.inf + INF Omap44xxPkg/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf + + # + # Power IC + # + INF Omap44xxPkg/TWL6030Dxe/TWL6030.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatBinPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + + # + # USB Support (not supported currently) + # + + INF Omap44xxPkg/PciEmulation/PciEmulation.inf + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # UEFI application (Shell Embedded Boot Loader) + # + INF ShellBinPkg/UefiShell/UefiShell.inf + + # + # Bds + # + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF ArmPlatformPkg/Bds/Bds.inf + + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF ArmPlatformPkg/PrePi/PeiMPCore.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + + +############################################################################ +# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section # +############################################################################ +# +#[Rule.Common.DXE_DRIVER] +# FILE DRIVER = $(NAMED_GUID) { +# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex +# COMPRESS PI_STD { +# GUIDED { +# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi +# UI STRING="$(MODULE_NAME)" Optional +# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) +# } +# } +# } +# +############################################################################ + +[Rule.Common.SEC] + FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED { + TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE = $(NAMED_GUID) { + TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING ="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM] + FILE PEIM = $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.PEIM.TIANOCOMPRESSED] + FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE = $(NAMED_GUID) { + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING="$(MODULE_NAME)" Optional + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION = $(NAMED_GUID) { + UI STRING ="$(MODULE_NAME)" Optional + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION = $(NAMED_GUID) { + PE32 PE32 |.efi + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } diff --git a/PandaBoardPkg/Sec/Arm/ModuleEntryPoint.S b/PandaBoardPkg/Sec/Arm/ModuleEntryPoint.S new file mode 100644 index 000000000..24714969c --- /dev/null +++ b/PandaBoardPkg/Sec/Arm/ModuleEntryPoint.S @@ -0,0 +1,85 @@ +#------------------------------------------------------------------------------ +# +# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#------------------------------------------------------------------------------ + +#include <AsmMacroIoLib.h> +#include <Library/PcdLib.h> + +.text +.align 3 + +.globl ASM_PFX(CEntryPoint) +GCC_ASM_EXPORT(_ModuleEntryPoint) + +ASM_PFX(_ModuleEntryPoint): + + // TODO: Disable L2 cache (need handle PL310) +// mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register +// bic r0, r0, #0x00000002 // disable L2 cache +// mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register + + //Enable Strict alignment checking & Instruction cache + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */ + orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ + orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */ + mcr p15, 0, r0, c1, c0, 0 + + // Enable NEON register in case folks want to use them for optimizations (CopyMem) + mrc p15, 0, r0, c1, c0, 2 + orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions) + mcr p15, 0, r0, c1, c0, 2 + mov r0, #0x40000000 // Set EN bit in FPEXC + mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly + + + // Set CPU vectors to start of DRAM + LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base + mcr p15, 0, r0, c12, c0, 0 + isb // Sync changes to control registers + + // Fill vector table with branchs to current pc (jmp $) + ldr r1, ShouldNeverGetHere + movs r2, #0 +FillVectors: + str r1, [r0, r2] + adds r2, r2, #4 + cmp r2, #32 + bne FillVectors + + /* before we call C code, lets setup the stack pointer in internal RAM */ +stack_pointer_setup: + + // + // Set stack based on PCD values. Need to do it this way to make C code work + // when it runs from FLASH. + // + LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) /* stack base arg2 */ + LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) /* stack size arg3 */ + add r4, r2, r3 + + //Enter SVC mode and set up SVC stack pointer + mov r0,#0x13|0x80|0x40 + msr CPSR_c,r0 + mov r13,r4 + + // Call C entry point + LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) /* memory size arg1 */ + LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) /* memory size arg0 */ + blx ASM_PFX(CEntryPoint) /* Assume C code is thumb */ + +ShouldNeverGetHere: + /* _CEntryPoint should never return */ + b ShouldNeverGetHere + diff --git a/PandaBoardPkg/Sec/Arm/ModuleEntryPoint.asm b/PandaBoardPkg/Sec/Arm/ModuleEntryPoint.asm new file mode 100644 index 000000000..81dfeda4a --- /dev/null +++ b/PandaBoardPkg/Sec/Arm/ModuleEntryPoint.asm @@ -0,0 +1,89 @@ +//------------------------------------------------------------------------------ +// +// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +// +// This program and the accompanying materials +// are licensed and made available under the terms and conditions of the BSD License +// which accompanies this distribution. The full text of the license may be found at +// http://opensource.org/licenses/bsd-license.php +// +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +// +//------------------------------------------------------------------------------ + +#include <AsmMacroIoLib.h> +#include <Library/PcdLib.h> +#include <AutoGen.h> + INCLUDE AsmMacroIoLib.inc + + IMPORT CEntryPoint + EXPORT _ModuleEntryPoint + + PRESERVE8 + AREA ModuleEntryPoint, CODE, READONLY + + +_ModuleEntryPoint + + // TODO: Disable L2 cache (need handle PL310) +// mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register +// bic r0, r0, #0x00000002 // disable L2 cache +// mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register + + //Enable Strict alignment checking & Instruction cache + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ + bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */ + orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ + orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */ + mcr p15, 0, r0, c1, c0, 0 + + // Enable NEON register in case folks want to use them for optimizations (CopyMem) + mrc p15, 0, r0, c1, c0, 2 + orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions) + mcr p15, 0, r0, c1, c0, 2 + mov r0, #0x40000000 // Set EN bit in FPEXC + msr FPEXC,r0 + + // Set CPU vectors to start of DRAM + LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base + mcr p15, 0, r0, c12, c0, 0 + isb // Sync changes to control registers + + // Fill vector table with branchs to current pc (jmp $) + ldr r1, ShouldNeverGetHere + movs r2, #0 +FillVectors + str r1, [r0, r2] + adds r2, r2, #4 + cmp r2, #32 + bne FillVectors + + /* before we call C code, lets setup the stack pointer in internal RAM */ +stack_pointer_setup + + // + // Set stack based on PCD values. Need to do it this way to make C code work + // when it runs from FLASH. + // + LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) // stack base arg2 + LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) // stack size arg3 + add r4, r2, r3 + + //Enter SVC mode and set up SVC stack pointer + mov r5,#0x13|0x80|0x40 + msr CPSR_c,r5 + mov r13,r4 + + // Call C entry point + LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) // memory size arg1 + LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) // memory start arg0 + blx CEntryPoint // Assume C code is thumb + +ShouldNeverGetHere + /* _CEntryPoint should never return */ + b ShouldNeverGetHere + + END + diff --git a/PandaBoardPkg/Sec/Cache.c b/PandaBoardPkg/Sec/Cache.c new file mode 100644 index 000000000..8c85b898c --- /dev/null +++ b/PandaBoardPkg/Sec/Cache.c @@ -0,0 +1,79 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <PiPei.h> + +#include <Library/ArmLib.h> +#include <Library/PrePiLib.h> +#include <Library/PcdLib.h> + +// DDR attributes +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED + +// SoC registers. L3 interconnects +#define SOC_REGISTERS_L3_PHYSICAL_BASE 0x68000000 +#define SOC_REGISTERS_L3_PHYSICAL_LENGTH 0x08000000 +#define SOC_REGISTERS_L3_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE + +// SoC registers. L4 interconnects +#define SOC_REGISTERS_L4_PHYSICAL_BASE 0x48000000 +#define SOC_REGISTERS_L4_PHYSICAL_LENGTH 0x08000000 +#define SOC_REGISTERS_L4_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE + +VOID +InitCache ( + IN UINT32 MemoryBase, + IN UINT32 MemoryLength + ) +{ + UINT32 CacheAttributes; + ARM_MEMORY_REGION_DESCRIPTOR MemoryTable[5]; + VOID *TranslationTableBase; + UINTN TranslationTableSize; + + if (FeaturePcdGet(PcdCacheEnable) == TRUE) { + CacheAttributes = DDR_ATTRIBUTES_CACHED; + } else { + CacheAttributes = DDR_ATTRIBUTES_UNCACHED; + } + + // DDR + MemoryTable[0].PhysicalBase = MemoryBase; + MemoryTable[0].VirtualBase = MemoryBase; + MemoryTable[0].Length = MemoryLength; + MemoryTable[0].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes; + + // SOC Registers. L3 interconnects + MemoryTable[1].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE; + MemoryTable[1].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE; + MemoryTable[1].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH; + MemoryTable[1].Attributes = SOC_REGISTERS_L3_ATTRIBUTES; + + // SOC Registers. L4 interconnects + MemoryTable[2].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE; + MemoryTable[2].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE; + MemoryTable[2].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH; + MemoryTable[2].Attributes = SOC_REGISTERS_L4_ATTRIBUTES; + + // End of Table + MemoryTable[3].PhysicalBase = 0; + MemoryTable[3].VirtualBase = 0; + MemoryTable[3].Length = 0; + MemoryTable[3].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; + + ArmConfigureMmu (MemoryTable, &TranslationTableBase, &TranslationTableSize); + + BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData); +} diff --git a/PandaBoardPkg/Sec/Clock.c b/PandaBoardPkg/Sec/Clock.c new file mode 100644 index 000000000..9d5a73a51 --- /dev/null +++ b/PandaBoardPkg/Sec/Clock.c @@ -0,0 +1,44 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Omap4430/Omap4430.h> +#include <Omap4430/Omap4430Rom.h> + +VOID +ClockInit ( + VOID + ) +{ + // TODO: clocks configuration code clean up + + // CORE, PER DPLLs are configured part of Configuration header which OMAP4 ROM parses. + + // Turn on functional & interface clocks to MMC1 and I2C1 modules. + MmioOr32(0x4a009328, 0x03070002); + + //Enable DMTIMER3 with SYS_CLK source + MmioOr32(0x4A009440, 0x2); + + //Enable DMTIMER4 with SYS_CLK source + MmioOr32(0x4A009448, 0x2); + + // Enable UART3 clocks + RomEnableClocks (2, 2); + + // Enable watchdog interface clocks + RomEnableClocks (6, 1); + +} diff --git a/PandaBoardPkg/Sec/LzmaDecompress.h b/PandaBoardPkg/Sec/LzmaDecompress.h new file mode 100644 index 000000000..2216cac86 --- /dev/null +++ b/PandaBoardPkg/Sec/LzmaDecompress.h @@ -0,0 +1,103 @@ +/** @file + LZMA Decompress Library header file + + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __LZMA_DECOMPRESS_H___ +#define __LZMA_DECOMPRESS_H___ + +/** + Examines a GUIDed section and returns the size of the decoded buffer and the + size of an scratch buffer required to actually decode the data in a GUIDed section. + + Examines a GUIDed section specified by InputSection. + If GUID for InputSection does not match the GUID that this handler supports, + then RETURN_UNSUPPORTED is returned. + If the required information can not be retrieved from InputSection, + then RETURN_INVALID_PARAMETER is returned. + If the GUID of InputSection does match the GUID that this handler supports, + then the size required to hold the decoded buffer is returned in OututBufferSize, + the size of an optional scratch buffer is returned in ScratchSize, and the Attributes field + from EFI_GUID_DEFINED_SECTION header of InputSection is returned in SectionAttribute. + + If InputSection is NULL, then ASSERT(). + If OutputBufferSize is NULL, then ASSERT(). + If ScratchBufferSize is NULL, then ASSERT(). + If SectionAttribute is NULL, then ASSERT(). + + + @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file. + @param[out] OutputBufferSize A pointer to the size, in bytes, of an output buffer required + if the buffer specified by InputSection were decoded. + @param[out] ScratchBufferSize A pointer to the size, in bytes, required as scratch space + if the buffer specified by InputSection were decoded. + @param[out] SectionAttribute A pointer to the attributes of the GUIDed section. See the Attributes + field of EFI_GUID_DEFINED_SECTION in the PI Specification. + + @retval RETURN_SUCCESS The information about InputSection was returned. + @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports. + @retval RETURN_INVALID_PARAMETER The information can not be retrieved from the section specified by InputSection. + +**/ +RETURN_STATUS +EFIAPI +LzmaGuidedSectionGetInfo ( + IN CONST VOID *InputSection, + OUT UINT32 *OutputBufferSize, + OUT UINT32 *ScratchBufferSize, + OUT UINT16 *SectionAttribute + ); + +/** + Decompress a LZAM compressed GUIDed section into a caller allocated output buffer. + + Decodes the GUIDed section specified by InputSection. + If GUID for InputSection does not match the GUID that this handler supports, then RETURN_UNSUPPORTED is returned. + If the data in InputSection can not be decoded, then RETURN_INVALID_PARAMETER is returned. + If the GUID of InputSection does match the GUID that this handler supports, then InputSection + is decoded into the buffer specified by OutputBuffer and the authentication status of this + decode operation is returned in AuthenticationStatus. If the decoded buffer is identical to the + data in InputSection, then OutputBuffer is set to point at the data in InputSection. Otherwise, + the decoded data will be placed in caller allocated buffer specified by OutputBuffer. + + If InputSection is NULL, then ASSERT(). + If OutputBuffer is NULL, then ASSERT(). + If ScratchBuffer is NULL and this decode operation requires a scratch buffer, then ASSERT(). + If AuthenticationStatus is NULL, then ASSERT(). + + + @param[in] InputSection A pointer to a GUIDed section of an FFS formatted file. + @param[out] OutputBuffer A pointer to a buffer that contains the result of a decode operation. + @param[out] ScratchBuffer A caller allocated buffer that may be required by this function + as a scratch buffer to perform the decode operation. + @param[out] AuthenticationStatus + A pointer to the authentication status of the decoded output buffer. + See the definition of authentication status in the EFI_PEI_GUIDED_SECTION_EXTRACTION_PPI + section of the PI Specification. EFI_AUTH_STATUS_PLATFORM_OVERRIDE must + never be set by this handler. + + @retval RETURN_SUCCESS The buffer specified by InputSection was decoded. + @retval RETURN_UNSUPPORTED The section specified by InputSection does not match the GUID this handler supports. + @retval RETURN_INVALID_PARAMETER The section specified by InputSection can not be decoded. + +**/ +RETURN_STATUS +EFIAPI +LzmaGuidedSectionExtraction ( + IN CONST VOID *InputSection, + OUT VOID **OutputBuffer, + OUT VOID *ScratchBuffer, OPTIONAL + OUT UINT32 *AuthenticationStatus + ); + +#endif // __LZMADECOMPRESS_H__ + diff --git a/PandaBoardPkg/Sec/PadConfiguration.c b/PandaBoardPkg/Sec/PadConfiguration.c new file mode 100644 index 000000000..796571192 --- /dev/null +++ b/PandaBoardPkg/Sec/PadConfiguration.c @@ -0,0 +1,31 @@ +/** @file + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <PiPei.h> +#include <Library/IoLib.h> +#include <Library/DebugLib.h> +#include <Omap4430/Omap4430.h> +#include <Omap4430/Omap4430Rom.h> + +VOID +PadConfiguration ( + VOID + ) +{ + // TODO: pad configuration + + // Configure UART3 pads + RomCtrlConfigurePads (2, 2); + +} diff --git a/PandaBoardPkg/Sec/Sec.c b/PandaBoardPkg/Sec/Sec.c new file mode 100644 index 000000000..4046c9b47 --- /dev/null +++ b/PandaBoardPkg/Sec/Sec.c @@ -0,0 +1,204 @@ +/** @file + C Entry point for the SEC. First C code after the reset vector. + + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include <PiPei.h> + +#include <Library/DebugLib.h> +#include <Library/PrePiLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/OmapLib.h> +#include <Library/ArmLib.h> +#include <Library/PeCoffGetEntryPointLib.h> +#include <Library/DebugAgentLib.h> +#include <Ppi/GuidedSectionExtraction.h> +#include <Guid/LzmaDecompress.h> +#include <Omap4430/Omap4430.h> +#include <Omap4430/Omap4430Rom.h> +#include "LzmaDecompress.h" + +VOID +PadConfiguration ( + VOID + ); + +VOID +ClockInit ( + VOID + ); + +VOID +TimerInit ( + VOID + ) +{ + UINTN Timer = FixedPcdGet32(PcdOmap44xxFreeTimer); + UINT32 TimerBaseAddress = TimerBase(Timer); + + // Un-register USB IRQs + RomIrqUnRegister (92); + RomIrqUnRegister (93); + + // Register Timer3 Irq + RomIrqRegister (0x55aa55aa, 39, 0); + + // Register Timer4 Irq + RomIrqRegister (0x55aa55aa, 40, 0); + + // Set count & reload registers + MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000); + MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000); + + // Disable interrupts + MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE); + + // Start Timer + MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON); + +} + +VOID +UartInit ( + VOID + ) +{ + UINTN Uart = FixedPcdGet32(PcdOmap44xxConsoleUart); + UINT32 UartBaseAddress = UartBase(Uart); + + // Set MODE_SELECT=DISABLE before trying to initialize or modify DLL, DLH registers. + MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_DISABLE); + + // Put device in configuration mode. + MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_ENABLE); + + // Programmable divisor N = 48Mhz/16/115200 = 26 + MmioWrite32 (UartBaseAddress + UART_DLL_REG, 3000000/FixedPcdGet64 (PcdUartDefaultBaudRate)); // low divisor + MmioWrite32 (UartBaseAddress + UART_DLH_REG, 0); // high divisor + + // Enter into UART operational mode. + MmioWrite32 (UartBaseAddress + UART_LCR_REG, UART_LCR_DIV_EN_DISABLE | UART_LCR_CHAR_LENGTH_8); + + // Force DTR and RTS output to active + MmioWrite32 (UartBaseAddress + UART_MCR_REG, UART_MCR_RTS_FORCE_ACTIVE | UART_MCR_DTR_FORCE_ACTIVE); + + // Clear & enable fifos + MmioWrite32 (UartBaseAddress + UART_FCR_REG, UART_FCR_TX_FIFO_CLEAR | UART_FCR_RX_FIFO_CLEAR | UART_FCR_FIFO_ENABLE); + + // Restore MODE_SELECT + MmioWrite32 (UartBaseAddress + UART_MDR1_REG, UART_MDR1_MODE_SELECT_UART_16X); +} + +VOID +GpmcConfiguration ( + VOID + ) +{ + // Make sure all chip selects are disabled + // Kernel makes a wrong assumption about CS0 being already configured by ROM + MmioWrite32 (0x50000078, 0xF00); + +} + +VOID +InitCache ( + IN UINT32 MemoryBase, + IN UINT32 MemoryLength + ); + +EFI_STATUS +EFIAPI +ExtractGuidedSectionLibConstructor ( + VOID + ); + +EFI_STATUS +EFIAPI +LzmaDecompressLibConstructor ( + VOID + ); + +UINTN mGlobalVariableBase = 0; + +VOID +CEntryPoint ( + IN VOID *MemoryBase, + IN UINTN MemorySize, + IN VOID *StackBase, + IN UINTN StackSize + ) +{ + VOID *HobBase; + + // Set up system clocking + ClockInit (); + + // Disable watchdog timer + RomWdtimerDisable (); + + // Build a basic HOB list + HobBase = (VOID *)(UINTN)(FixedPcdGet32(PcdEmbeddedFdBaseAddress) + FixedPcdGet32(PcdEmbeddedFdSize)); + CreateHobList (MemoryBase, MemorySize, HobBase, StackBase); + + // Set up Pin muxing + PadConfiguration (); + + // Setup gpmc + GpmcConfiguration (); + + // Start up a free running timer so that the timer lib will work + TimerInit (); + + // Enable program flow prediction, if supported. + ArmEnableBranchPrediction (); + + // Initialize CPU cache + InitCache ((UINT32)MemoryBase, (UINT32)MemorySize); + + // Add memory allocation hob for relocated FD + BuildMemoryAllocationHob (FixedPcdGet32(PcdEmbeddedFdBaseAddress), FixedPcdGet32(PcdEmbeddedFdSize), EfiBootServicesData); + + // Add the FVs to the hob list + BuildFvHob (PcdGet32(PcdFlashFvMainBase), PcdGet32(PcdFlashFvMainSize)); + + // Start talking + UartInit (); + + InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL); + SaveAndSetDebugTimerInterrupt (TRUE); + + DEBUG ((EFI_D_ERROR, "UART Enabled\n")); + + // SEC phase needs to run library constructors by hand. + ExtractGuidedSectionLibConstructor (); + LzmaDecompressLibConstructor (); + + // Build HOBs to pass up our version of stuff the DXE Core needs to save space + BuildPeCoffLoaderHob (); + BuildExtractSectionHob ( + &gLzmaCustomDecompressGuid, + LzmaGuidedSectionGetInfo, + LzmaGuidedSectionExtraction + ); + + // Assume the FV that contains the SEC (our code) also contains a compressed FV. + DecompressFirstFv (); + + // Load the DXE Core and transfer control to it + LoadDxeCoreFromFv (NULL, 0); + + // DXE Core should always load and never return + ASSERT (FALSE); +} + diff --git a/PandaBoardPkg/Sec/Sec.inf b/PandaBoardPkg/Sec/Sec.inf new file mode 100644 index 000000000..ec8834e47 --- /dev/null +++ b/PandaBoardPkg/Sec/Sec.inf @@ -0,0 +1,73 @@ + +#/** @file +# SEC - Reset vector code that jumps to C and loads DXE core +# +# Copyright (c) 2008, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PandaBoardSec + FILE_GUID = d959e387-7b91-452c-90e0-a1dbac90ddb8 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + + +[Sources.ARM] + Arm/ModuleEntryPoint.S | GCC + Arm/ModuleEntryPoint.asm | RVCT + +[Sources.ARM] + Sec.c + Cache.c + PadConfiguration.c + Clock.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + Omap44xxPkg/Omap44xxPkg.dec + IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec + +[LibraryClasses] + BaseLib + DebugLib + ArmLib + IoLib + ExtractGuidedSectionLib + LzmaDecompressLib + OmapLib + PeCoffGetEntryPointLib + DebugAgentLib + MemoryAllocationLib + PrePiHobListPointerLib + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdCacheEnable + +[FixedPcd] + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate + gEmbeddedTokenSpaceGuid.PcdEmbeddedFdBaseAddress + gEmbeddedTokenSpaceGuid.PcdEmbeddedFdSize + gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase + gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize + gEmbeddedTokenSpaceGuid.PcdPrePiStackSize + gEmbeddedTokenSpaceGuid.PcdPrePiStackBase + gEmbeddedTokenSpaceGuid.PcdMemoryBase + gEmbeddedTokenSpaceGuid.PcdMemorySize + + gOmap44xxTokenSpaceGuid.PcdOmap44xxConsoleUart + gOmap44xxTokenSpaceGuid.PcdOmap44xxFreeTimer + + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress + diff --git a/PandaBoardPkg/Tools/GNUmakefile b/PandaBoardPkg/Tools/GNUmakefile new file mode 100644 index 000000000..b86a1d6bf --- /dev/null +++ b/PandaBoardPkg/Tools/GNUmakefile @@ -0,0 +1,44 @@ +# +# Makefile +# +# Copyright(c) 2010 Texas Instruments. All rights reserved. +# +# Texas Instruments, <www.ti.com> +# Bastien Allibert <b-allibert@ti.com> +# Olivier Deprez <o-deprez@ti.com> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# * Neither the name Texas Instruments nor the names of its +# contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# + +CC = gcc +CFLAGS = -g + +chtool: chtool.c + $(CC) $(CCFLAGS) $(LDFLAGS) -o chtool chtool.c + +clean: + rm -f chtool diff --git a/PandaBoardPkg/Tools/ch_omap4.h b/PandaBoardPkg/Tools/ch_omap4.h new file mode 100644 index 000000000..2a74abe41 --- /dev/null +++ b/PandaBoardPkg/Tools/ch_omap4.h @@ -0,0 +1,173 @@ +/* + 2 * ch_omap4.h + 3 * + 4 * Copyright(c) 2010 Texas Instruments. All rights reserved. + 5 * + 6 * Texas Instruments, <www.ti.com> + 7 * Bastien Allibert <b-allibert@ti.com> + 8 * Olivier Deprez <o-deprez@ti.com> + 9 * + 10 * Redistribution and use in source and binary forms, with or without + 11 * modification, are permitted provided that the following conditions + 12 * are met: + 13 * + 14 * * Redistributions of source code must retain the above copyright + 15 * notice, this list of conditions and the following disclaimer. + 16 * * Redistributions in binary form must reproduce the above copyright + 17 * notice, this list of conditions and the following disclaimer in + 18 * the documentation and/or other materials provided with the + 19 * distribution. + 20 * * Neither the name Texas Instruments nor the names of its + 21 * contributors may be used to endorse or promote products derived + 22 * from this software without specific prior written permission. + 23 * + 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + 25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + 27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + 28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 35 */ + +#ifndef _CH_OMAP4_H +#define _CH_OMAP4_H + +/* Define here all the data fields for each item */ +CH_Field OMAP4_CHSETTINGS_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C1}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + + {0x0008,0x04,"Flags","ClockSettings",0}, + {0x000C,0x04,"CM_CLKSEL_CORE","ClockSettings",0}, + {0x0010,0x04,"CM_DLL_CTRL","ClockSettings",0}, + {0x0014,0x04,"CM_AUTOIDLE_DPLL_MPU","ClockSettings",0}, + {0x0018,0x04,"CM_CLKSEL_DPLL_MPU","ClockSettings",0}, + {0x001C,0x04,"CM_DIV_M2_DPLL_MPU","ClockSettings",0}, + {0x0020,0x04,"CM_AUTOIDLE_DPLL_CORE","ClockSettings",0}, + {0x0024,0x04,"CM_CLKSEL_DPLL_CORE","ClockSettings",0}, + {0x0028,0x04,"CM_DIV_M2_DPLL_CORE","ClockSettings",0}, + {0x002C,0x04,"CM_DIV_M3_DPLL_CORE","ClockSettings",0}, + {0x0030,0x04,"CM_DIV_M4_DPLL_CORE","ClockSettings",0}, + {0x0034,0x04,"CM_DIV_M5_DPLL_CORE","ClockSettings",0}, + {0x0038,0x04,"CM_DIV_M6_DPLL_CORE","ClockSettings",0}, + {0x003C,0x04,"CM_DIV_M7_DPLL_CORE","ClockSettings",0}, + {0x0040,0x04,"CM_AUTOIDLE_DPLL_PER","ClockSettings",0}, + {0x0044,0x04,"CM_CLKSEL_DPLL_PER","ClockSettings",0}, + {0x0048,0x04,"CM_DIV_M2_DPLL_PER","ClockSettings",0}, + {0x004C,0x04,"CM_DIV_M3_DPLL_PER","ClockSettings",0}, + {0x0050,0x04,"CM_DIV_M4_DPLL_PER","ClockSettings",0}, + {0x0054,0x04,"CM_DIV_M5_DPLL_PER","ClockSettings",0}, + {0x0058,0x04,"CM_DIV_M6_DPLL_PER","ClockSettings",0}, + {0x005C,0x04,"CM_DIV_M7_DPLL_PER","ClockSettings",0}, + {0x0060,0x04,"CM_AUTOIDLE_DPLL_USB","ClockSettings",0}, + {0x0064,0x04,"CM_CLKSEL_DPLL_USB","ClockSettings",0}, + {0x0068,0x04,"CM_DIV_M2_DPLL_USB","ClockSettings",0} +}; +CH_Field OMAP4_CHRAM_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C2}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + + {0x0008,0x04,"SdramConfigEMIF1","SDRAM Configuration Register",0}, + {0x000C,0x04,"SdramRefreshEMIF1","SDRAM Refresh Control Register",0}, + {0x0010,0x04,"SdramTim1EMIF1","SDRAM Timing 1 Register",0}, + {0x0014,0x04,"SdramTim2EMIF1","SDRAM Timing 2 Register",0}, + {0x0018,0x04,"SdramTim3EMIF1","SDRAM Timing 3 Register",0}, + {0x001C,0x04,"PwrMgtCtrlEMIF1","Power mgt control Register",0}, + {0x0020,0x04,"DdrPhyCtrl1EMIF1","DDR PHY Control 1 Register",0}, + {0x0024,0x04,"DdrPhyCtrl2EMIF1","DDR PHY Control 2 Register",0}, + {0x0028,0x01,"ModeReg1EMIF1","Mode register MR1",0}, + {0x0029,0x01,"ModeReg2EMIF1","Mode register MR2",0}, + {0x002A,0x01,"ModeReg3EMIF1","Mode register MR3",0}, + {0x002B,0x01,"Reserved","Reserved",0}, + + {0x002C,0x04,"SdramConfigEMIF2","SDRAM Configuration Register",0}, + {0x0030,0x04,"SdramRefreshEMIF2","SDRAM Refresh Control Register",0}, + {0x0034,0x04,"SdramTim1EMIF2","SDRAM Timing 1 Register",0}, + {0x0038,0x04,"SdramTim2EMIF2","SDRAM Timing 2 Register",0}, + {0x003C,0x04,"SdramTim3EMIF2","SDRAM Timing 3 Register",0}, + {0x0040,0x04,"PwrMgtCtrlEMIF2","Power mgt control Register",0}, + {0x0044,0x04,"DdrPhyCtrl1EMIF2","DDR PHY Control 1 Register",0}, + {0x0048,0x04,"DdrPhyCtrl2EMIF2","DDR PHY Control 2 Register",0}, + {0x004C,0x01,"ModeReg1EMIF2","Mode register MR1",0}, + {0x004D,0x01,"ModeReg2EMIF2","Mode register MR2",0}, + {0x004E,0x01,"ModeReg3EMIF2","Mode register MR3",0}, + {0x004F,0x01,"Reserved","Reserved",0}, + + {0x0050,0x04,"DMMLisaMap0","DMM LISA section 0 mapping",0}, + {0x0054,0x04,"Flags","Configure the chip selects",0} +}; +CH_Field OMAP4_CHFLASH_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C3}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + + {0x0008,0x02,"GPMC_SYSCONFIG_LSB","Register Value",0}, + {0x000A,0x02,"GPMC_IRQENABLE_LSB","Register Value",0}, + {0x000C,0x02,"GPMC_TIMEOUT_CONTROL_LSB","Register Value",0}, + + {0x000E,0x02,"GPMC_CONFIG_LSB","Register Value",0}, + {0x0010,0x04,"GPMC_CONFIG1_0","Register Value",0}, + {0x0014,0x04,"GPMC_CONFIG2_0","Register Value",0}, + {0x0018,0x04,"GPMC_CONFIG3_0","Register Value",0}, + {0x001C,0x04,"GPMC_CONFIG4_0","Register Value",0}, + {0x0020,0x04,"GPMC_CONFIG5_0","Register Value",0}, + {0x0024,0x04,"GPMC_CONFIG6_0","Register Value",0}, + {0x0028,0x04,"GPMC_CONFIG7_0","Register Value",0}, + + {0x002C,0x04,"GPMC_PREFETCH_CONFIG1","Register Value",0}, + {0x0030,0x02,"GPMC_PREFETCH_CONFIG2_LSB","Register Value",0}, + {0x0032,0x02,"GPMC_PREFETCH_CONTROL_LSB","Register Value",0}, + {0x0034,0x02,"GPMC_ECC_CONFIG","Register Value",0}, + {0x0036,0x02,"GPMC_ECC_CONTROL","Register Value",0}, + {0x0038,0x04,"GPMC_ECC_SIZE_CONFIG_LSB","Register Value",0}, + {0x003C,0x04,"Enable_A1_A10","Enable A1-A10 pads",0} +}; +CH_Field OMAP4_CHMMCSD_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C4}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + + {0x0008,0x02,"MMC_SYSCTL_MSW","MMC_SYSCTL_MSW",0}, + {0x000A,0x02,"MMC_SYSCTL_LSW","MMC_SYSCTL_LSW",0}, + + {0x000C,0x04,"BusWidth","BusWidth",0} +}; + +/* Now define here the TOC entry for each item */ +CH_Item_t OMAP4_CHSETTINGS_Item = { {0x0,0x6C,{0,0,0},"CHSETTINGS"}, + OMAP4_CHSETTINGS_Fields, + sizeof(OMAP4_CHSETTINGS_Fields)/sizeof(CH_Field) }; + +CH_Item_t OMAP4_CHRAM_Item = { {0x0,0x58,{0,0,0},"CHRAM"}, + OMAP4_CHRAM_Fields, + sizeof(OMAP4_CHRAM_Fields)/sizeof(CH_Field) }; + +CH_Item_t OMAP4_CHFLASH_Item = { {0x0,0x40,{0,0,0},"CHFLASH"}, + OMAP4_CHFLASH_Fields, + sizeof(OMAP4_CHFLASH_Fields)/sizeof(CH_Field) }; + +CH_Item_t OMAP4_CHMMCSD_Item = { {0x0,0x10,{0,0,0},"CHMMCSD"}, + OMAP4_CHMMCSD_Fields, + sizeof(OMAP4_CHMMCSD_Fields)/sizeof(CH_Field) }; + +/* Make sure to list here each defined item */ +CH_Item_t* OMAP4_ItemsList[] = { &OMAP4_CHSETTINGS_Item, + &OMAP4_CHRAM_Item, + &OMAP4_CHFLASH_Item, + &OMAP4_CHMMCSD_Item }; + +/* Define here your top platform entity, pointing to the item list */ +const OMAP_Platform_t CH_OMAP4_Platform = {"OMAP4",512,OMAP4_ItemsList,sizeof(OMAP4_ItemsList)/sizeof(CH_Item_t*)}; + +#endif // _CH_OMAP4_H diff --git a/PandaBoardPkg/Tools/ch_omap5.h b/PandaBoardPkg/Tools/ch_omap5.h new file mode 100644 index 000000000..1086c5f03 --- /dev/null +++ b/PandaBoardPkg/Tools/ch_omap5.h @@ -0,0 +1,212 @@ +/* + 2 * ch_omap5.h + 3 * + 4 * Copyright(c) 2010 Texas Instruments. All rights reserved. + 5 * + 6 * Texas Instruments, <www.ti.com> + 7 * Bastien Allibert <b-allibert@ti.com> + 8 * Olivier Deprez <o-deprez@ti.com> + 9 * + 10 * Redistribution and use in source and binary forms, with or without + 11 * modification, are permitted provided that the following conditions + 12 * are met: + 13 * + 14 * * Redistributions of source code must retain the above copyright + 15 * notice, this list of conditions and the following disclaimer. + 16 * * Redistributions in binary form must reproduce the above copyright + 17 * notice, this list of conditions and the following disclaimer in + 18 * the documentation and/or other materials provided with the + 19 * distribution. + 20 * * Neither the name Texas Instruments nor the names of its + 21 * contributors may be used to endorse or promote products derived + 22 * from this software without specific prior written permission. + 23 * + 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + 25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + 27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + 28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 35 */ + +#ifndef _CH_OMAP5_H +#define _CH_OMAP5_H + +/* Define here all the data fields for each item */ +CH_Field OMAP5_CHSETTINGS_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C1}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + {0x0008,0x04,"Flags","ClockSettings",0}, + //HAL_CKGEN_General_t + {0x000C,0x04,"CM_CLKSEL_CORE","ClockSettings",0}, + {0x0010,0x04,"CM_BYPCLK_MPU","ClockSettings",0}, + {0x0014,0x04,"CM_BYPCLK_IVA","ClockSettings",0}, + {0x0018,0x04,"CM_MPU_CLK_CTRL","ClockSettings",0}, + {0x001C,0x04,"CM_CLKSEL_USB","ClockSettings",0}, + //HAL_CKGEN_DpllCommon_t MPU + {0x0020,0x04,"CM_CLKMODE_DPLL_MPU","ClockSettings",0}, + {0x0024,0x04,"CM_AUTOIDLE_DPLL_MPU","ClockSettings",0}, + {0x0028,0x04,"CM_CLKSEL_DPLL_MPU","ClockSettings",0}, + {0x002C,0x04,"CM_DIV_M2_DPLL_MPU","ClockSettings",0}, + //HAL_CKGEN_DpllCommon_t CORE + {0x0030,0x04,"CM_CLKMODE_DPLL_CORE","ClockSettings",0}, + {0x0034,0x04,"CM_AUTOIDLE_DPLL_CORE","ClockSettings",0}, + {0x0038,0x04,"CM_CLKSEL_DPLL_CORE","ClockSettings",0}, + {0x003C,0x04,"CM_DIV_M2_DPLL_CORE","ClockSettings",0}, + {0x0040,0x04,"CM_DIV_M3_DPLL_CORE","ClockSettings",0}, + {0x0044,0x04,"CM_DIV_H11_DPLL_CORE","ClockSettings",0}, + {0x0048,0x04,"CM_DIV_H12_DPLL_CORE","ClockSettings",0}, + {0x004C,0x04,"CM_DIV_H13_DPLL_CORE","ClockSettings",0}, + {0x0050,0x04,"CM_DIV_H14_DPLL_CORE","ClockSettings",0}, + {0x0054,0x04,"CM_DIV_H22_DPLL_CORE","ClockSettings",0}, + {0x0058,0x04,"CM_DIV_H23_DPLL_CORE","ClockSettings",0}, + //HAL_CKGEN_DpllCommon_t PER5 + {0x005C,0x04,"CM_CLKMODE_DPLL_PER","ClockSettings",0}, + {0x0060,0x04,"CM_AUTOIDLE_DPLL_PER","ClockSettings",0}, + {0x0064,0x04,"CM_CLKSEL_DPLL_PER","ClockSettings",0}, + {0x0068,0x04,"CM_DIV_M2_DPLL_PER","ClockSettings",0}, + {0x006C,0x04,"CM_DIV_M3_DPLL_PER","ClockSettings",0}, + {0x0070,0x04,"CM_DIV_H11_DPLL_PER","ClockSettings",0}, + {0x0074,0x04,"CM_DIV_H12_DPLL_PER","ClockSettings",0}, + {0x0078,0x04,"CM_DIV_H14_DPLL_PER","ClockSettings",0}, + //HAL_CKGEN_DpllCommon_t USB1 + {0x007C,0x04,"CM_CLKMODE_DPLL_USB","ClockSettings",0}, + {0x0080,0x04,"CM_AUTOIDLE_DPLL_USB","ClockSettings",0}, + {0x0084,0x04,"CM_CLKSEL_DPLL_USB","ClockSettings",0}, + {0x0088,0x04,"CM_DIV_M2_DPLL_USB","ClockSettings",0} +}; +CH_Field OMAP5_CHRAM_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C2}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + {0x0008,0x04,"SdramConfig","SDRAM Configuration Register",0}, + {0x000C,0x04,"SdramConfig2","SDRAM Configuration Register",0}, + {0x0010,0x04,"SdramRefresh","SDRAM Refresh Control Register",0}, + {0x0014,0x04,"SdramRefreshShdw","SDRAM Refresh Control Shadow Register",0}, + {0x0018,0x04,"SdramTim1","SDRAM Timing 1 Register",0}, + {0x001C,0x04,"SdramTim2","SDRAM Timing 2 Register",0}, + {0x0020,0x04,"SdramTim3","SDRAM Timing 3 Register",0}, + {0x0024,0x04,"SdramTim1Shdw","SDRAM Timing 1 Shadow Register",0}, + {0x0028,0x04,"SdramTim2Shdw","SDRAM Timing 2 Shadow Register",0}, + {0x002C,0x04,"SdramTim3Shdw","SDRAM Timing 3 Shadow Register",0}, + {0x0030,0x04,"PwrMgtCtrl","Power mgt control Register",0}, + {0x0034,0x04,"PwrMgtCtrlShdw","Power mgt control Shadow Register",0}, + {0x0038,0x04,"DdrPhyCtrl1","DDR PHY Control 1 Register",0}, + {0x003C,0x04,"DdrPhyCtrl2","DDR PHY Control 2 Register",0}, + {0x0040,0x04,"DdrPhyCtrl1Shdw","DDR PHY Control 1 Register",0}, + {0x0044,0x04,"ExtPhyCtrl1","",0}, + {0x0048,0x04,"ExtPhyCtrl2","",0}, + {0x004C,0x04,"ExtPhyCtrl3","",0}, + {0x0050,0x04,"ExtPhyCtrl4","",0}, + {0x0054,0x04,"ExtPhyCtrl5","",0}, + {0x0058,0x04,"ExtPhyCtrl6","",0}, + {0x005C,0x04,"ExtPhyCtrl7","",0}, + {0x0060,0x04,"ExtPhyCtrl8","",0}, + {0x0064,0x04,"ExtPhyCtrl9","",0}, + {0x0068,0x04,"ExtPhyCtrl10","",0}, + {0x006C,0x04,"ExtPhyCtrl11","",0}, + {0x0070,0x04,"ExtPhyCtrl12","",0}, + {0x0074,0x04,"ExtPhyCtrl13","",0}, + {0x0078,0x04,"ExtPhyCtrl14","",0}, + {0x007C,0x04,"ExtPhyCtrl15","",0}, + {0x0080,0x04,"ExtPhyCtrl16","",0}, + {0x0084,0x04,"ExtPhyCtrl17","",0}, + {0x0088,0x04,"ExtPhyCtrl18","",0}, + {0x008C,0x04,"ExtPhyCtrl19","",0}, + {0x0090,0x04,"ExtPhyCtrl20","",0}, + {0x0094,0x04,"ExtPhyCtrl21","",0}, + {0x0098,0x04,"ExtPhyCtrl22","",0}, + {0x009C,0x04,"ExtPhyCtrl23","",0}, + {0x00A0,0x04,"ExtPhyCtrl24","",0}, + {0x00A4,0x04,"ExtPhyCtrl25","",0}, + {0x00A8,0x04,"ExtPhyCtrl26","",0}, + {0x00AC,0x04,"ExtPhyCtrl27","",0}, + {0x00B0,0x04,"ExtPhyCtrl28","",0}, + {0x00B4,0x04,"ExtPhyCtrl29","",0}, + {0x00B8,0x04,"ExtPhyCtrl30","",0}, + {0x00BC,0x04,"ModeReg","",0}, + {0x00C0,0x04,"CoreFreqConfigM2Div","",0}, + {0x00C4,0x04,"DMMLisaMap0","DMM LISA section 0 mapping",0}, + {0x00C8,0x04,"Flags","Configure the chip selects",0} +}; + +CH_Field OMAP5_CHFLASH_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C3}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + {0x0008,0x02,"GPMC_SYSCONFIG_LSB","",0}, + {0x000A,0x02,"GPMC_IRQENABLE_LSB","",0}, + {0x000C,0x02,"GPMC_TIMEOUT_CONTROL_LSB","",0}, + {0x000E,0x02,"GPMC_CONFIG_LSB","",0}, + {0x0010,0x04,"GPMC_CONFIG1","",0}, + {0x0014,0x04,"GPMC_CONFIG2","",0}, + {0x0018,0x04,"GPMC_CONFIG3","",0}, + {0x001C,0x04,"GPMC_CONFIG4","",0}, + {0x0020,0x04,"GPMC_CONFIG5","",0}, + {0x0024,0x04,"GPMC_CONFIG6","",0}, + {0x0028,0x04,"GPMC_CONFIG7","",0}, + {0x002C,0x04,"GPMC_PREFETCH_CONFIG1","",0}, + {0x0030,0x02,"GPMC_PREFETCH_CONFIG2_LSB","",0}, + {0x0032,0x02,"GPMC_PREFETCH_CONTROL_LSB","",0}, + {0x0034,0x02,"GPMC_ECC_CONFIG","",0}, + {0x0036,0x02,"GPMC_ECC_CONTROL","",0}, + {0x0038,0x04,"GPMC_ECC_SIZE_CONFIG_LSB","",0}, + {0x003C,0x04,"Enable_A1_A10","Enable A1-A10 pads",0} +}; +CH_Field OMAP5_CHMMCSD_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C4}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + {0x0008,0x04,"CLOCK","",0}, + {0x000C,0x04,"BusWidth","",0} +}; +CH_Field OMAP5_CHSATA_Fields[] = { + {0x0000,0x04,"SectionKey","Key used for item verification",0xC0C0C0C5}, + {0x0004,0x01,"Valid","Enables / Disables the item",0}, + {0x0005,0x01,"Version","Configuration header version",1}, + {0x0006,0x02,"Reserved","Reserved",0}, + {0x0008,0x04,"MultiSectorReadEn","",0} +}; + +/* Now define here the TOC entry for each item */ +CH_Item_t OMAP5_CHSETTINGS_Item = { {0x0,0x8C,{0,0,0},"CHSETTINGS"}, + OMAP5_CHSETTINGS_Fields, + sizeof(OMAP5_CHSETTINGS_Fields)/sizeof(CH_Field) }; + +CH_Item_t OMAP5_CHRAM_Item = { {0x0,0xCC,{0,0,0},"CHRAM"}, + OMAP5_CHRAM_Fields, + sizeof(OMAP5_CHRAM_Fields)/sizeof(CH_Field) }; + +CH_Item_t OMAP5_CHFLASH_Item = { {0x0,0x40,{0,0,0},"CHFLASH"}, + OMAP5_CHFLASH_Fields, + sizeof(OMAP5_CHFLASH_Fields)/sizeof(CH_Field) }; + +CH_Item_t OMAP5_CHMMCSD_Item = { {0x0,0x10,{0,0,0},"CHMMCSD"}, + OMAP5_CHMMCSD_Fields, + sizeof(OMAP5_CHMMCSD_Fields)/sizeof(CH_Field) }; + +CH_Item_t OMAP5_CHSATA_Item = { {0x0,0x0C,{0,0,0},"CHSATA"}, + OMAP5_CHSATA_Fields, + sizeof(OMAP5_CHSATA_Fields)/sizeof(CH_Field) }; + +/* Make sure to list here each defined item */ +CH_Item_t* OMAP5_ItemsList[] = { &OMAP5_CHSETTINGS_Item, + &OMAP5_CHRAM_Item, + &OMAP5_CHFLASH_Item, + &OMAP5_CHMMCSD_Item, + &OMAP5_CHSATA_Item }; + +/* Define here your top platform entity, pointing to the item list */ +const OMAP_Platform_t CH_OMAP5_Platform = {"OMAP5",512,OMAP5_ItemsList,sizeof(OMAP5_ItemsList)/sizeof(CH_Item_t*)}; + +#endif // _CH_OMAP5_H diff --git a/PandaBoardPkg/Tools/ch_types.h b/PandaBoardPkg/Tools/ch_types.h new file mode 100644 index 000000000..5f18e1d03 --- /dev/null +++ b/PandaBoardPkg/Tools/ch_types.h @@ -0,0 +1,81 @@ +/* + 2 * ch_types.h + 3 * + 4 * Copyright(c) 2010 Texas Instruments. All rights reserved. + 5 * + 6 * Texas Instruments, <www.ti.com> + 7 * Bastien Allibert <b-allibert@ti.com> + 8 * Olivier Deprez <o-deprez@ti.com> + 9 * + 10 * Redistribution and use in source and binary forms, with or without + 11 * modification, are permitted provided that the following conditions + 12 * are met: + 13 * + 14 * * Redistributions of source code must retain the above copyright + 15 * notice, this list of conditions and the following disclaimer. + 16 * * Redistributions in binary form must reproduce the above copyright + 17 * notice, this list of conditions and the following disclaimer in + 18 * the documentation and/or other materials provided with the + 19 * distribution. + 20 * * Neither the name Texas Instruments nor the names of its + 21 * contributors may be used to endorse or promote products derived + 22 * from this software without specific prior written permission. + 23 * + 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + 25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + 27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + 28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 35 */ + +#ifndef _CH_TYPES_H +#define _CH_TYPES_H + +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; +typedef unsigned int uint32_t; +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed int int32_t; +typedef signed int bool_t; + +typedef struct { + uint32_t Offset; + uint32_t Size; + uint8_t Name[64]; + uint8_t *Description; + uint32_t Value; +} CH_Field; + +typedef struct { + uint32_t Start; + uint32_t Size; + uint32_t Reserved[3]; + uint8_t Filename[12]; +} CH_ItemTOC_t; + +typedef struct { + CH_ItemTOC_t TOC; + CH_Field *fields; + uint32_t numberOfFields; +} CH_Item_t; + +typedef struct { + uint8_t Name[16]; + uint32_t ConfigurationHeaderSize; + CH_Item_t** SupportedItemsList; + uint32_t NumberOfSupportedItems; +} OMAP_Platform_t; + +typedef enum { + BIN_FILE, + C_FILE +} outputfile_t; + +#endif // _CH_TYPES_H diff --git a/PandaBoardPkg/Tools/chtool.c b/PandaBoardPkg/Tools/chtool.c new file mode 100644 index 000000000..f127122a6 --- /dev/null +++ b/PandaBoardPkg/Tools/chtool.c @@ -0,0 +1,1064 @@ +/* + 2 * chtool.c + 3 * + 4 * Copyright(c) 2010 Texas Instruments. All rights reserved. + 5 * + 6 * Texas Instruments, <www.ti.com> + 7 * Bastien Allibert <b-allibert@ti.com> + 8 * Olivier Deprez <o-deprez@ti.com> + 9 * + 10 * Redistribution and use in source and binary forms, with or without + 11 * modification, are permitted provided that the following conditions + 12 * are met: + 13 * + 14 * * Redistributions of source code must retain the above copyright + 15 * notice, this list of conditions and the following disclaimer. + 16 * * Redistributions in binary form must reproduce the above copyright + 17 * notice, this list of conditions and the following disclaimer in + 18 * the documentation and/or other materials provided with the + 19 * distribution. + 20 * * Neither the name Texas Instruments nor the names of its + 21 * contributors may be used to endorse or promote products derived + 22 * from this software without specific prior written permission. + 23 * + 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + 25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + 27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + 28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + 30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + 35 */ + +/*------------------------------ Include Files -------------------------------*/ +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <sys/stat.h> +#include <ctype.h> + +#include "ch_types.h" +#include "ch_omap4.h" +#include "ch_omap5.h" + +/*------------------------------ Local Definitions ---------------------------*/ + + +/*------------------------------ Local Types ---------------------------------*/ +typedef enum { + NO_IMAGE, + PREPENDED_CH, + MERGED_TOCS +} OutMode_t; +typedef struct { + char* infile; + char* outfile; + char* imagefile; + OutMode_t OutMode; + bool_t removeCH; + outputfile_t out_type; + OMAP_Platform_t* platform; +} Params_t; + +/*------------------------------ Local Variables -----------------------------*/ +const OMAP_Platform_t* LV_plist[] = {&CH_OMAP4_Platform,&CH_OMAP5_Platform}; + +/*------------------------------ Local Constants -----------------------------*/ +#define CHTOOL_VERSION "0.4" +#define CH_TRUE 1 +#define CH_FALSE 0 + +/*------------------------------ Local Functions Declarations ----------------*/ +int32_t CheckArguments(int argc, char* argv[],Params_t* params); +void PrintPlatformSettings(OMAP_Platform_t* p); +void PrintHelp(char *progname); +int32_t FileExtension(const char *file,const char *pattern); +int32_t dat2bin(Params_t *p); +int32_t bin2dat(Params_t *p); +int32_t RemoveCH(Params_t *p); +int32_t CreateImageFile(Params_t *p); +uint8_t CheckPlatformCompatibilityWithCHFormat(uint8_t *CH,uint32_t FileSize,OMAP_Platform_t* omap); + +/*------------------------------ Global Functions ----------------------------*/ +/*------------------------------ Local Functions -----------------------------*/ + + +/*------------------------------------------------------------------------------ +* FUNCTION : Main +* +* DESCRIPTION: The function is the top function of the tool, simply calling +* first the arguments chechker and then the appropriate +* function, either image generation or extraction. +* +* +* PARAMETERS : argc - number of arguments +* argv - arguments values +* +* RETURNS : 0 on success +* Others on failure +* +*-----------------------------------------------------------------------------*/ +int main(int argc, char* argv[]) +{ + Params_t params; + + if (CheckArguments(argc,argv,¶ms) != 0) + { + return 0; + } + + // TODO : the job + if (FileExtension(params.infile,"dat") == 0) + { + int32_t err_code; + err_code = dat2bin(¶ms); + if (err_code == 0) + { + if (params.OutMode != NO_IMAGE) + { + CreateImageFile(¶ms); + } + } + } + else if (FileExtension(params.outfile,"dat") == 0) + { + int32_t err_code; + err_code = bin2dat(¶ms); + if ((err_code == 0)&&(params.removeCH == CH_TRUE)) + { + // Remove configuration header from input bin file + RemoveCH(¶ms); + } + } + else + { + printf("Unrecognized file extension...\n"); + } + + return 0; +} + +/*------------------------------------------------------------------------------ +* FUNCTION : CheckArguments +* +* DESCRIPTION: This function is in charge of checking the command-line +* arguments given by the user and display the help page +* in case of troubles. +* +* +* PARAMETERS : argc - number of arguments +* argv - arguments values +* params - an empty data structure to store the parameters +* +* RETURNS : 0 on success +* Others on failure +* +*-----------------------------------------------------------------------------*/ +int32_t CheckArguments(int argc, char* argv[],Params_t* params) +{ + int32_t i,j,k; + + params->infile = NULL; + params->outfile = NULL; + params->imagefile = NULL; + params->OutMode = NO_IMAGE; + params->removeCH = CH_FALSE; + params->out_type = BIN_FILE; + params->platform = NULL; + + if (argc == 1) + { + PrintHelp(argv[0]); + return -1; + } + + for (i=1 ; i<argc ; i++) + { + if (strcmp(argv[i],"-p")==0) + { + int match=0; + for (j=0 ; j<(sizeof(LV_plist)/sizeof(const OMAP_Platform_t *)) ; j++) + { + int len = strlen(argv[i+1]); + for(k=0;k<len;k++) + { + argv[i+1][k] = toupper(argv[i+1][k]); + } + if (strcmp(LV_plist[j]->Name,argv[i+1])==0) + { + params->platform = (OMAP_Platform_t*) (LV_plist[j]); + match=1; + } + } + if (match==0) + { + printf("ERROR : Platform %s is not supported...\n",argv[i+1]); + return -1; + } + i++; + } + else if (strcmp(argv[i],"-c")==0) + { + params->out_type = C_FILE; + } + else if (strcmp(argv[i],"-rmch")==0) + { + params->removeCH = CH_TRUE; + } + else if (strcmp(argv[i],"-m")==0) + { + params->imagefile = argv[i+1]; + if (params->outfile == NULL) + { + params->outfile = "tmp.bin"; + } + params->OutMode = MERGED_TOCS; + i++; + } + else if (strcmp(argv[i],"-i")==0) + { + params->infile = argv[i+1]; + i++; + } + else if (strcmp(argv[i],"-o")==0) + { + params->outfile = argv[i+1]; + i++; + } + else if (strcmp(argv[i],"-O")==0) + { + params->imagefile = argv[i+1]; + if (params->outfile == NULL) + { + params->outfile = "tmp.bin"; + } + params->OutMode = PREPENDED_CH; + i++; + } + else if (strcmp(argv[i],"-v")==0) + { + if (params->platform != NULL) + { + PrintPlatformSettings(params->platform); + } + } + else if (strcmp(argv[i],"-h")==0) + { + PrintHelp(argv[0]); + return -1; + } + else + { + printf("Option %s is not supported...\n",argv[i]); + printf("Type '%s -h' for more a list of supported options\n",argv[0]); + return -1; + } + } + + if (params->infile == NULL) + { + printf("ERROR : Please provide an input file\n"); + return -1; + } + if (params->outfile == NULL) + { + printf("ERROR : Please provide an output file\n"); + return -1; + } + + return 0; +} + +/*------------------------------------------------------------------------------ +* FUNCTION : PrintPlatformSettings +* +* DESCRIPTION: This function is in charge of printing to console all +* the possible parameters supported by a specified platform +* +* +* PARAMETERS : p - pointer to the data structure describing the platform +* +* RETURNS : +* +*-----------------------------------------------------------------------------*/ +void PrintPlatformSettings(OMAP_Platform_t* p) +{ + int32_t i,j; + printf("Platform %s\n",p->Name); + + for(i=0 ; i<p->NumberOfSupportedItems ; i++) + { + CH_Item_t* it = p->SupportedItemsList[i]; + printf("\tItem %s (size 0x%.4X)\n",it->TOC.Filename,it->TOC.Size); + for (j=0 ; j<it->numberOfFields ; j++) + { + CH_Field f = it->fields[j]; + printf("\t\t0x%.4X %-4d %-32s %-40s 0x%-4.4X\n",f.Offset,f.Size,f.Name,f.Description,f.Value); + } + } + printf("\n\n"); +} + +/*------------------------------------------------------------------------------ +* FUNCTION : PrintHelp +* +* DESCRIPTION: This function prints the help page to console +* +* +* PARAMETERS : progname - string containing the program name +* +* RETURNS : +* +*-----------------------------------------------------------------------------*/ +void PrintHelp(char *progname) +{ + int32_t i; + printf("\n"); + printf("Version " CHTOOL_VERSION "\n\n"); + + printf("Usage : %s <options>\n\n",progname); + + printf("Options :\n"); + printf("\t-p <platform_name> : selects the target platform. Supported platforms : "); + for (i=0 ; i<(sizeof(LV_plist)/sizeof(const OMAP_Platform_t *)) ; i++) + { + printf("%s ",LV_plist[i]->Name); + } + printf("\n"); + printf("\t-i <input_CH_file> : input file can be either a *.bin file (for target) or a *.dat file (containing parameters)\n"); + printf("\t-o <output_CH_file> : output file can be either a *.bin file (for target) or a *.dat file (containing parameters)\n"); + printf("\t-m <merge_file> : merges the provided signed image's TOC with the configuration header settings\n"); + printf("\t-O <image_file> : prepend the output CH binary to the provided binary image file\n"); + printf("\t-c : generate c file conforming to Topsim format, instead of the usual binary file\n"); + printf("\t-rmch : remove the input file's configuration header\n"); + printf("\t-v : verbose mode prints to screen all the configuration header fields for the selected platform\n"); + printf("\t-h : prints help\n"); + printf("\n\n"); + + printf("Supported platform(s) : "); + for (i=0 ; i<(sizeof(LV_plist)/sizeof(const OMAP_Platform_t *)) ; i++) + { + printf("%s ",LV_plist[i]->Name); + } + printf("\n\n\n"); +} + +/*------------------------------------------------------------------------------ +* FUNCTION : FileExtension +* +* DESCRIPTION: This function extracts the extension from a filename +* and compares it with a specified pattern +* +* +* PARAMETERS : file - string containing the file name +* pattern - pattern to be compared with the file extension +* +* RETURNS : 0 on success +* Others on failure +* +*-----------------------------------------------------------------------------*/ +int32_t FileExtension(const char *file,const char *pattern) +{ + int32_t i,j; + for (i=strlen(file)-1 ; i>=0 ; i--) + { + if (file[i] == '.') + { + i++; + break; + } + } + if (i == 0) + { + // No extension found... + return -1; + } + if (strlen(pattern) != (strlen(file) - i)) + { + // Extension length do not match + return -1; + } + for (j=0 ; j<strlen(pattern) ; j++) + { + if (pattern[j] != file[i+j]) + { + // Mismatch in extension... + return -1; + } + } + return 0; +} + +/*------------------------------------------------------------------------------ +* FUNCTION : dat2bin +* +* DESCRIPTION: This function generates a binary file containing a +* Configuration Header image from a set of parameters given +* by the user through an input file +* +* +* PARAMETERS : p - parameters given to the program (including +* input and output filenames +* +* RETURNS : 0 on success +* Others on failure +* +*-----------------------------------------------------------------------------*/ +int32_t dat2bin(Params_t *p) +{ + FILE *inf; + FILE *outf; + char myline[128]; + char myword0[128]; + char myword1[128]; + OMAP_Platform_t *omap = p->platform; + CH_Item_t *item = NULL; + uint8_t *CH; + uint8_t *CHt; + uint32_t idx; + uint32_t nItems=0; + uint32_t tmpoffset=0; + + // Open files + inf = fopen(p->infile,"rb"); + outf = fopen(p->outfile,"wb"); + + if ((inf == NULL) || (outf == NULL)) + { + if (inf != NULL) + { + fclose(inf); + } + if (outf != NULL) + { + fclose(outf); + } + return -1; + } + + // If platform is not specified in command-line arguments, try to see if the target is given in the *.dat file + if (omap == NULL) + { + while(fscanf(inf,"%s",myline) != EOF) + { + int32_t i,j; + for (i=0 ; myline[i] != '\0' ; i++) + { + if ((myline[i] == ';') || (myline[i] == '#')) + { + break; + } + if (myline[i] == '=') + { + myline[i] = ' '; + sscanf(myline,"%s %s",myword0,myword1); + if (strcmp(myword0,"TARGET")==0) + { + for(j=0 ; j<sizeof(LV_plist)/sizeof(OMAP_Platform_t*) ; j++) + { + if (strcmp(myword1,LV_plist[j]->Name) == 0) + { + omap = (OMAP_Platform_t*)LV_plist[j]; + p->platform = omap; + } + } + } + break; + } + } + } + fseek(inf,0,SEEK_SET); + } + + // Check that a platform is specified (for output format choice) + if (omap == NULL) + { + printf("ERROR : Platform must be specified, either in command-line or in provided parameter file\n"); + fclose(inf); + fclose(outf); + return -1; + } + + // Allocate Configuration Header memory space + CH = (uint8_t *)malloc(omap->ConfigurationHeaderSize * sizeof(uint8_t)); + memset(CH,0,omap->ConfigurationHeaderSize * sizeof(uint8_t)); + + // Count the number of valid items in image + while(fscanf(inf,"%s",myline) != EOF) + { + int32_t i,j; + for (i=0 ; myline[i] != '\0' ; i++) + { + if (myline[i] == '=') + { + // If we find a '=', then it is not an item section beginning, so break + break; + } + } + if (myline[i] == '\0') + { + // we came to the end of the line w/o finding a '='.... it seems to be a new item section starting point + for (j=0 ; j<omap->NumberOfSupportedItems ; j++) + { + if (strcmp(omap->SupportedItemsList[j]->TOC.Filename,myline)==0) + { + nItems++; + break; + } + } + } + } + //printf("Found %d valid items in input file...\n",nItems); + + /* Come back to the beginning of the file */ + fseek(inf,0,SEEK_SET); + while(fscanf(inf,"%s",myline) != EOF) + { + int32_t i,j; + uint32_t val; + + for (i=0 ; myline[i] != '\0' ; i++) + { + if (myline[i] == '=') + { + myline[i] = ' '; + + sscanf(myline,"%s %s",myword0,myword1); + if (strcmp(myword0,"TARGET")==0) + { + // Ignore here... only informative + } + else + { + // Set item attribute + if ((myword1[0] == '0') && (myword1[1] == 'x')) + { + sscanf(myline,"%s 0x%X",myword0,&val); + } + else + { + sscanf(myline,"%s %d",myword0,&val); + } + + //printf("%s <- 0x%X\n",myword0,val); + + if (item != NULL) + { + for (j=0 ; j<item->numberOfFields ; j++) + { + CH_Field f = item->fields[j]; + if (strcmp(f.Name,myword0)==0) + { + int32_t k; + // Write it in little endian !!! + //printf("fieldSize=%d\n",f.Size); + for (k=0 ; k<f.Size ; k++) + { + uint32_t address = item->TOC.Start + f.Offset + k; + if (address < omap->ConfigurationHeaderSize) + { + CH[address] = (uint8_t)(val & 0xFF); + } + else + { + printf("ERROR : trying to write on address %d but Configuration Header length is %d. Ignoring...\n",address,omap->ConfigurationHeaderSize); + } + //printf("0x%.2X ",val & 0xFF); + val >>= 8; + } + break; + } + } + if (j == item->numberOfFields) + { + //printf("WARNING - Could not find field %s in %s item. This input will be ignored...\n",myword0,item->TOC.Filename); + } + } + } + break; + } + } + + if (myline[i] == '\0') + { + + // Change item + for (j=0 ; j<omap->NumberOfSupportedItems ; j++) + { + if (strcmp(omap->SupportedItemsList[j]->TOC.Filename,myline)==0) + { + //itemN=j; + //itemOffset = (nItems+1)*sizeof(CH_ItemTOC_t) + tmpoffset; + item = omap->SupportedItemsList[j]; + //item->TOC.Start = itemOffset; + item->TOC.Start = (nItems+1)*sizeof(CH_ItemTOC_t) + tmpoffset; + + //printf("ITEM %s (number %d) : Start=0x%.4X ; Size=%d...\n",myline,itemN,item->TOC.Start,item->TOC.Size); + tmpoffset += (omap->SupportedItemsList[j]->TOC.Size); + + break; + } + } + if (j==omap->NumberOfSupportedItems) + { + //printf("ERROR : Item %s is not supported. Please check your parameter file...\n",myline); + } + } + } + + // ... close the input file + fclose(inf); + + // Now, write the TOC ... + for (CHt=CH, idx=0 ; idx<omap->NumberOfSupportedItems ; idx++) + { + if (omap->SupportedItemsList[idx]->TOC.Start != 0) + { + memcpy(CHt, omap->SupportedItemsList[idx], sizeof(CH_ItemTOC_t)); + CHt += sizeof(CH_ItemTOC_t); + } + } + memset(CHt,0xFF,sizeof(CH_ItemTOC_t)); + + if (p->out_type == C_FILE) + { + int32_t i,j; + const char *c_header = "#include \"GlobalTypes.h\"\n\n__align(4) const unsigned char LC_Toc[] = \n{\n"; + const char *c_tail = "};\n\n/*================================ End Of File ==============================*/\n"; + fwrite(c_header,sizeof(uint8_t),strlen(c_header),outf); + for(i=0 ; i<32 ; i++) + { + for(j=0 ; j<16 ; j++) + { + if ((i == 31) && (j == 15)) + { + fprintf(outf,"0x%.2x",CH[(i<<4)|j]); + } + else + { + fprintf(outf,"0x%.2x, ",CH[(i<<4)|j]); + } + } + fprintf(outf,"\n"); + } + fwrite(c_tail,sizeof(uint8_t),strlen(c_tail),outf); + } + else + { + // Write everything to the output file in standard binary format + fwrite(CH,sizeof(uint8_t),omap->ConfigurationHeaderSize,outf); + } + + // ... close the output file + fclose(outf); + + // Free Configuration Header memory space + free(CH); + + return 0; +} + +/*------------------------------------------------------------------------------ +* FUNCTION : bin2dat +* +* DESCRIPTION: This function extracts all the parameters stored in a binary +* file containing a Configuration Header image and stores them +* into an output file +* +* +* PARAMETERS : p - parameters given to the program (including +* input and output filenames +* +* RETURNS : 0 on success +* Others on failure +* +*-----------------------------------------------------------------------------*/ +int32_t bin2dat(Params_t *p) +{ + FILE *inf; + FILE *outf; + struct stat FileStat; + uint32_t FileSize; + OMAP_Platform_t *omap; + uint8_t *CH; + int32_t i,j,k; + uint8_t MatchFound; + + // Open the files + inf = fopen(p->infile,"rb"); + outf = fopen(p->outfile,"wb"); + + if ((inf == NULL) || (outf == NULL)) + { + if (inf != NULL) + { + fclose(inf); + } + if (outf != NULL) + { + fclose(outf); + } + return -1; + } + + // Stat the input file to get the input inage size + fstat(fileno(inf), &FileStat); + FileSize = (uint32_t) FileStat.st_size; + //printf("Input file size is %dbytes\n",FileSize); + + // Fill an temporary buffer with the file content + CH = (uint8_t *)malloc(FileSize * sizeof(uint8_t)); + fread(CH,FileSize,sizeof(uint8_t),inf); + + // Close the input file + fclose(inf); + + if (p->platform == NULL) + { + // Try to guess the target by parsing the TOC + // Browse the supported platform list and take the first platform matching these : + // - The input image size matches the expected configuration header size for the platform + // - All item names (CHSETTINGS, CHRAM,...) contained in the input image are supported by the platform + // - For each of these items, the item data size must match the expected size + for (MatchFound=0,i=0 ; (MatchFound==0)&&(i<(sizeof(LV_plist) / sizeof(OMAP_Platform_t*))) ; i++) + { + omap = (OMAP_Platform_t*) LV_plist[i]; + MatchFound = CheckPlatformCompatibilityWithCHFormat(CH,FileSize,omap); + } + + if (MatchFound==1) + { + printf("Found platform compatibility with %s...\n",omap->Name); + p->platform = omap; + } + else + { + printf("Could not find a compatible platform for this image\n"); + return -1; + } + } + else + { + omap = p->platform; + MatchFound = CheckPlatformCompatibilityWithCHFormat(CH,FileSize,omap); + if (MatchFound==0) + { + printf("Compatibility test with %s platform's Configuration Header format FAILED\n", omap->Name); + return -1; + } + } + + if (MatchFound != 0) + { + CH_Item_t *item; + CH_ItemTOC_t *toc; + + //OK, do the job ! + fprintf(outf,"TARGET=%s\n",omap->Name); + + // Point to the first TOC entry of the input image + toc = (CH_ItemTOC_t *)CH; + while(toc->Start != 0xFFFFFFFF) + { + for(i=0 ; i<omap->NumberOfSupportedItems ; i++) + { + if (strcmp(omap->SupportedItemsList[i]->TOC.Filename,toc->Filename) == 0) + { + item = omap->SupportedItemsList[i]; + break; + } + } + // Print the item name + fprintf(outf,"\n%s\n",toc->Filename); + + // Then reverse all the items + for(j=0 ; j<item->numberOfFields ; j++) + { + uint32_t value = 0; + uint8_t *pvalue = (uint8_t *)&value; + CH_Field f = item->fields[j]; + + for(k=0 ; k<f.Size ; k++) + { + pvalue[k] = CH[toc->Start + f.Offset + k]; + } + + //printf("Field %s value is 0x%.8X\n",f.Name,value); + fprintf(outf,"%s=0x%.8X\n",f.Name,value); + } + + // Then move to next TOC entry of the input image + toc++; + } + } + + // Free the temporary buffer space + free(CH); + + // Close the output file + fclose(outf); + + return 0; +} + +/*------------------------------------------------------------------------------ +* FUNCTION : bin2dat +* +* DESCRIPTION: This function extracts all the parameters stored in a binary +* file containing a Configuration Header image and stores them +* into an output file +* +* +* PARAMETERS : p - parameters given to the program (including +* input and output filenames +* +* RETURNS : 0 on success +* Others on failure +* +*-----------------------------------------------------------------------------*/ +int32_t RemoveCH(Params_t *p) +{ + FILE *f; + struct stat FileStat; + uint32_t FileSize; + + // Open the files + f = fopen(p->infile,"rb"); + + if (f == NULL) + { + return -1; + } + + // Stat the input file to get the input inage size + fstat(fileno(f), &FileStat); + FileSize = (uint32_t) FileStat.st_size; + //printf("Input file size is %dbytes\n",FileSize); + + if (p->platform != NULL) + { + uint8_t *buffer = (uint8_t *)malloc(FileSize * sizeof(uint8_t)); + if (buffer == NULL) + { + fclose(f); + return -1; + } + + fread((void *)buffer,sizeof(uint8_t),FileSize,f); + fclose(f); + f = fopen(p->infile,"wb"); + if (f == NULL) + { + free(buffer); + return -1; + } + + fwrite((void *)(buffer + p->platform->ConfigurationHeaderSize),sizeof(uint8_t),FileSize - p->platform->ConfigurationHeaderSize,f); + free(buffer); + } + + fclose(f); + return 0; +} + +/*------------------------------------------------------------------------------ +* FUNCTION : CreateImageFile +* +* DESCRIPTION: This function merges configuration header's TOC with +* a provided signed image's TOC. +* +* +* PARAMETERS : p - parameters given to the program (including +* config header and signed image filenames +* +* RETURNS : 0 on success +* Others on failure +* +*-----------------------------------------------------------------------------*/ +int32_t CreateImageFile(Params_t *p) +{ + FILE *chf; + FILE *sif; + struct stat FileStat; + uint32_t ch_size,si_size; + uint8_t *CH; + uint8_t *SI; + CH_ItemTOC_t *toc_entry; + uint32_t ch_tocsize; + uint32_t si_tocsize; + uint32_t new_tocsize; + uint32_t ch_itemsize; + + + // Open the files + chf = fopen(p->outfile,"rb"); /* config header file */ + sif = fopen(p->imagefile,"rb"); /* signed image file */ + + if ((chf == NULL) || (sif == NULL)) + { + if (chf != NULL) + { + fclose(chf); + } + if (sif != NULL) + { + fclose(sif); + } + return -1; + } + + // Stat the CH file to get the CH image size + fstat(fileno(chf), &FileStat); + ch_size = (uint32_t) FileStat.st_size; + + // Fill an temporary buffer with the CH file content + CH = (uint8_t *)malloc(ch_size * sizeof(uint8_t)); + fread(CH,ch_size,sizeof(uint8_t),chf); + + // Close the CH file + fclose(chf); + + // Stat the signed image file to get the signed image size + fstat(fileno(sif), &FileStat); + si_size = (uint32_t) FileStat.st_size; + + // Fill an temporary buffer with the CH file content + SI = (uint8_t *)malloc(si_size * sizeof(uint8_t)); + fread(SI,si_size,sizeof(uint8_t),sif); + + // Close the CH file + fclose(sif); + + // Now, analyze SI file's TOC to get its size + si_tocsize=0; + for(toc_entry=(CH_ItemTOC_t *)SI ; (toc_entry->Start != 0xFFFFFFFF) ; toc_entry++) + { + si_tocsize += (sizeof(CH_ItemTOC_t)); + } + + // Now, analyze CH file's TOC and TOC items to get their sizes + ch_tocsize=0; + ch_itemsize=0; + for(toc_entry=(CH_ItemTOC_t *)CH ; (toc_entry->Start != 0xFFFFFFFF) ; toc_entry++) + { + ch_tocsize += (sizeof(CH_ItemTOC_t)); + ch_itemsize += toc_entry->Size; + } + + switch (p->OutMode) + { + case MERGED_TOCS: + new_tocsize = ch_tocsize + sizeof(CH_ItemTOC_t) + si_tocsize; + if (new_tocsize > p->platform->ConfigurationHeaderSize) + { + printf("WARNING : Configuration header and image TOC are too big (%d bytes) to fit in the first %d bytes. Program will attempt to prepend CH to image binary file",new_tocsize,p->platform->ConfigurationHeaderSize); + p->OutMode = PREPENDED_CH; + } + else + { + break; + } + case PREPENDED_CH: + new_tocsize = ch_tocsize + sizeof(CH_ItemTOC_t); + if (new_tocsize > p->platform->ConfigurationHeaderSize) + { + printf("ERROR : This configuration header is too big (%d bytes) to be prepended to the image file. Maximum supported size is %d bytes.\n",new_tocsize,p->platform->ConfigurationHeaderSize); + return -1; + } + break; + default: + printf("ERROR : This output mode is not supported.\n"); + return -1; + break; + } + + /* Open the output file (signed image file) */ + sif = fopen(p->imagefile,"wb"); /* signed image file */ + + /* Process */ + switch (p->OutMode) + { + case MERGED_TOCS: + for(toc_entry=(CH_ItemTOC_t *)CH ; (toc_entry->Start != 0xFFFFFFFF) ; toc_entry++) + { + // Add a constant offset to each config header TOC entry, equivalent to the signed image TOC size (overhead of muxing) + toc_entry->Start += si_tocsize; + } + fwrite(CH,sizeof(uint8_t),ch_tocsize,sif); /* copy configuration header's TOC */ + fwrite(SI,sizeof(uint8_t),si_tocsize + sizeof(CH_ItemTOC_t),sif); /* copy signed image's TOC + the TOCEND entry */ + fwrite((void *)(CH + ch_tocsize + sizeof(CH_ItemTOC_t)),sizeof(uint8_t),ch_itemsize,sif); /* copy configuration header's items */ + fwrite((void *)(SI + si_tocsize + sizeof(CH_ItemTOC_t)),sizeof(uint8_t),p->platform->ConfigurationHeaderSize - (new_tocsize + ch_itemsize),sif); /* Add some padding between configuratino header items and signed image items */ + fwrite((void *)(SI + p->platform->ConfigurationHeaderSize),sizeof(uint8_t),si_size - p->platform->ConfigurationHeaderSize,sif); /* Copy signed image items */ + break; + case PREPENDED_CH: + fwrite(CH,sizeof(uint8_t),p->platform->ConfigurationHeaderSize,sif); /* copy configuration header */ + fwrite(SI,sizeof(uint8_t),si_size,sif); /* copy signed image */ + break; + default: + break; + } + + // All changes are done, close the signed image file... + fclose(sif); + + // Free allocated space for input files + free(CH); + free(SI); + + return 0; +} + +/*------------------------------------------------------------------------------ +* FUNCTION : CheckPlatformCompatibilityWithCHFormat +* +* DESCRIPTION: This function analyze a Configuration Header image and +* tries to determine its compatibility with a given platform, +* based on the TOC entries and on their respective size +* +* +* PARAMETERS : CH - input Configuration Header image +* Filesize - input Configuration Header image size +* omap - platform to be checked for compatibility +* +* RETURNS : 1 in case of compatibility +* 0 in case of incompatibility +* +*-----------------------------------------------------------------------------*/ +uint8_t CheckPlatformCompatibilityWithCHFormat(uint8_t *CH,uint32_t FileSize,OMAP_Platform_t* omap) +{ + uint8_t MatchFound=0; + int j,k; + + CH_ItemTOC_t *toc; + + /* commented the following line since file size comparison is not meaningfull when people provides + not only the config header but also the code image */ + //if (FileSize == omap->ConfigurationHeaderSize) + { + for(j=0,toc=(CH_ItemTOC_t *)CH ; toc->Start != 0xFFFFFFFF ; toc++,j++) + { + for(MatchFound=0,k=0 ; k<omap->NumberOfSupportedItems ; k++) + { + if (strcmp(omap->SupportedItemsList[k]->TOC.Filename,toc->Filename)==0) + { + if (omap->SupportedItemsList[k]->TOC.Size == toc->Size) + { + MatchFound=1; + } + break; + } + } + if (MatchFound==0) + { + break; + } + } + } + return MatchFound; +} + +/*-------------------------------End of File ---------------------------------*/ diff --git a/PandaBoardPkg/Tools/makefile b/PandaBoardPkg/Tools/makefile new file mode 100755 index 000000000..fe5eea853 --- /dev/null +++ b/PandaBoardPkg/Tools/makefile @@ -0,0 +1,22 @@ +# +# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +all: GenerateImage replace + +GenerateImage: generate_image.c + $(CC) $(CCFLAGS) $(LDFLAGS) -o GenerateImage.exe generate_image.c + +replace: replace.c + $(CC) $(CCFLAGS) $(LDFLAGS) -o replace.exe replace.c + +clean: + del GenerateImage.exe generate_image.obj replace.exe replace.obj diff --git a/PandaBoardPkg/Tools/mkheader.pl b/PandaBoardPkg/Tools/mkheader.pl new file mode 100755 index 000000000..8e0e81883 --- /dev/null +++ b/PandaBoardPkg/Tools/mkheader.pl @@ -0,0 +1,39 @@ +#!/usr/bin/perl + +my $size = -s "$ARGV[0]"; +#my $addr = 0x80008000; +my $addr = 0x80008208; + +open OUTPUT_FILE, ">$ARGV[1]"; +open INPUT_FILE, "<$ARGV[0]"; + +binmode OUTPUT_FILE; +binmode INPUT_FILE; + +$size-=0x200; +$size-=8; + +print OUTPUT_FILE chr($size&0xFF); +$size>>=8; +print OUTPUT_FILE chr($size&0xFF); +$size>>=8; +print OUTPUT_FILE chr($size&0xFF); +$size>>=8; +print OUTPUT_FILE chr($size&0xFF); + +print OUTPUT_FILE chr($addr&0xFF); +$addr>>=8; +print OUTPUT_FILE chr($addr&0xFF); +$addr>>=8; +print OUTPUT_FILE chr($addr&0xFF); +$addr>>=8; +print OUTPUT_FILE chr($addr&0xFF); + +seek INPUT_FILE, 520, 0; + +while(<INPUT_FILE>) { + print OUTPUT_FILE $_; +} + +close OUTPUT_FILE; +close INPUT_FILE; diff --git a/PandaBoardPkg/b.bat b/PandaBoardPkg/b.bat new file mode 100755 index 000000000..af4a8cbdc --- /dev/null +++ b/PandaBoardPkg/b.bat @@ -0,0 +1,68 @@ +@REM Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +@REM This program and the accompanying materials +@REM are licensed and made available under the terms and conditions of the BSD License +@REM which accompanies this distribution. The full text of the license may be found at +@REM http://opensource.org/licenses/bsd-license.php +@REM +@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +@REM + +@REM Example usage of this script. default is a DEBUG build +@REM b +@REM b clean +@REM b release +@REM b release clean +@REM b -v -y build.log + +ECHO OFF +@REM Setup Build environment. Sets WORKSPACE and puts build in path +CALL ..\edksetup.bat + +@REM Set for tools chain. Currently RVCT31 +SET TARGET_TOOLS=RVCT31 +SET TARGET=DEBUG + +@if /I "%1"=="RELEASE" ( + @REM If 1st argument is release set TARGET to RELEASE and shift arguments to remove it + SET TARGET=RELEASE + shift /1 +) + +SET BUILD_ROOT=%WORKSPACE%\Build\PandaBoard\%TARGET%_%TARGET_TOOLS% + +@REM Build the Panda Board firmware and creat an FD (FLASH Device) Image. +CALL build -p PandaBoardPkg\PandaBoardPkg.dsc -a ARM -t %TARGET_TOOLS% -b %TARGET% %1 %2 %3 %4 %5 %6 %7 %8 +@if ERRORLEVEL 1 goto Exit + +@if /I "%1"=="CLEAN" goto Clean + +@REM +@REM Ram starts at 0x80000000 +@REM OMAP TRM defines 0x80008208 as the entry point +@REM The reset vector is caught by the mask ROM in the OMAP so that is why this entry +@REM point looks so strange. +@REM OMAP TRM section 26.4.8 has Image header information. (missing in OMAP TRM) +@REM +@cd Tools + +ECHO Building tools... +CALL nmake + +ECHO Patching image with ConfigurationHeader.dat +CALL GenerateImage -D ..\ConfigurationHeader.dat -E 0x80008208 -I %BUILD_ROOT%\FV\PANDABOARD_EFI.fd -O %BUILD_ROOT%\FV\PandaBoard_EFI_flashboot.fd + +ECHO Patching ..\Debugger_scripts ... +SET DEBUGGER_SCRIPT=..\Debugger_scripts +@for /f %%a IN ('dir /b %DEBUGGER_SCRIPT%\*.inc %DEBUGGER_SCRIPT%\*.cmm') do ( + @CALL replace %DEBUGGER_SCRIPT%\%%a %BUILD_ROOT%\%%a ZZZZZZ %BUILD_ROOT% WWWWWW %WORKSPACE% +) + +cd .. +:Exit +EXIT /B + +:Clean +cd Tools +CALL nmake clean +cd .. diff --git a/PandaBoardPkg/ba.bat b/PandaBoardPkg/ba.bat new file mode 100755 index 000000000..e3a3b9395 --- /dev/null +++ b/PandaBoardPkg/ba.bat @@ -0,0 +1,68 @@ +@REM Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> +@REM This program and the accompanying materials +@REM are licensed and made available under the terms and conditions of the BSD License +@REM which accompanies this distribution. The full text of the license may be found at +@REM http://opensource.org/licenses/bsd-license.php +@REM +@REM THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +@REM WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +@REM + +@REM Example usage of this script. default is a DEBUG build +@REM b +@REM b clean +@REM b release +@REM b release clean +@REM b -v -y build.log + +ECHO OFF +@REM Setup Build environment. Sets WORKSPACE and puts build in path +CALL ..\edksetup.bat + +@REM Set for tools chain. Currently ARMGCC +SET TARGET_TOOLS=ARMGCC +SET TARGET=DEBUG + +@if /I "%1"=="RELEASE" ( + @REM If 1st argument is release set TARGET to RELEASE and shift arguments to remove it + SET TARGET=RELEASE + shift /1 +) + +SET BUILD_ROOT=%WORKSPACE%\Build\PandaBoard\%TARGET%_%TARGET_TOOLS% + +@REM Build the Panda Board firmware and creat an FD (FLASH Device) Image. +CALL build -p PandaBoardPkg\PandaBoardPkg.dsc -a ARM -t %TARGET_TOOLS% -b %TARGET% %1 %2 %3 %4 %5 %6 %7 %8 +@if ERRORLEVEL 1 goto Exit + +@if /I "%1"=="CLEAN" goto Clean + +@REM +@REM Ram starts at 0x80000000 +@REM OMAP TRM defines 0x80008208 as the entry point +@REM The reset vector is caught by the mask ROM in the OMAP so that is why this entry +@REM point looks so strange. +@REM OMAP TRM section 26.4.8 has Image header information. (missing in OMAP TRM) +@REM +@cd Tools + +ECHO Building tools... +CALL nmake + +ECHO Patching image with ConfigurationHeader.dat +CALL GenerateImage -D ..\ConfigurationHeader.dat -E 0x80008208 -I %BUILD_ROOT%\FV\PANDABOARD_EFI.fd -O %BUILD_ROOT%\FV\PandaBoard_EFI_flashboot.fd + +ECHO Patching ..\Debugger_scripts ... +SET DEBUGGER_SCRIPT=..\Debugger_scripts +@for /f %%a IN ('dir /b %DEBUGGER_SCRIPT%\*.inc %DEBUGGER_SCRIPT%\*.cmm') do ( + @CALL replace %DEBUGGER_SCRIPT%\%%a %BUILD_ROOT%\%%a ZZZZZZ %BUILD_ROOT% WWWWWW %WORKSPACE% +) + +cd .. +:Exit +EXIT /B + +:Clean +cd Tools +CALL nmake clean +cd .. diff --git a/PandaBoardPkg/build.sh b/PandaBoardPkg/build.sh new file mode 100755 index 000000000..dc4b9067d --- /dev/null +++ b/PandaBoardPkg/build.sh @@ -0,0 +1,164 @@ +#!/bin/bash +# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +set -e +shopt -s nocasematch + +function process_debug_scripts { + if [[ -d $1 ]]; then + for filename in `ls $1` + do + sed -e "s@ZZZZZZ@$BUILD_ROOT@g" -e "s@WWWWWW@$WORKSPACE@g" \ + "$1/$filename" \ + > "$BUILD_ROOT/$filename" + + #For ARMCYGWIN, we have to change /cygdrive/c to c: + if [[ $TARGET_TOOLS == RVCT31CYGWIN ]] + then + mv "$BUILD_ROOT/$filename" "$BUILD_ROOT/$filename"_temp + sed -e "s@/cygdrive/\(.\)@\1:@g" \ + "$BUILD_ROOT/$filename"_temp \ + > "$BUILD_ROOT/$filename" + rm -f "$BUILD_ROOT/$filename"_temp + fi + done + fi +} + + +# +# Setup workspace if it is not set +# +if [ -z "${WORKSPACE:-}" ] +then + echo Initializing workspace + cd .. +# Uses an external BaseTools project +# export EDK_TOOLS_PATH=`pwd`/../BaseTools +# Uses the BaseTools in edk2 + export EDK_TOOLS_PATH=`pwd`/BaseTools + source edksetup.sh BaseTools +else + echo Building from: $WORKSPACE +fi + +# +# Pick a default tool type for a given OS if no toolchain already defined +# +if [ X"$TOOLCHAIN" != X"" ] +then + TARGET_TOOLS="$TOOLCHAIN" +fi + +if [ -z "${TARGET_TOOLS:-}" ] +then + case `uname` in + CYGWIN*) + TARGET_TOOLS=RVCT31CYGWIN + ;; + Linux*) + if [[ ! -z `locate arm-linux-gnueabi-gcc` ]]; then + TARGET_TOOLS=ARMLINUXGCC + else + TARGET_TOOLS=ARMGCC + fi + ;; + Darwin*) + Major=$(uname -r | cut -f 1 -d '.') + if [[ $Major == 9 ]] + then + # Not supported by this open source project + TARGET_TOOLS=XCODE31 + else + TARGET_TOOLS=XCODE32 + fi + ;; + esac +fi + +TARGET=DEBUG +BUILD_TARGET=DEBUG +args=($@) + +for (( i=0; i<$#; i++ )) +do + if [[ "${args[$i]}" == "-b" ]] + then + TARGET=${args[$i+1]} + BUILD_TARGET=$TARGET + if [[ "$TARGET" == "RELEASE" ]] + then + BUILD_TARGET="$BUILD_TARGET -D DEBUG_TARGET=RELEASE" + fi + i=$i+1 + else + other_args="$other_args ${args[$i]}" + fi +done + +BUILD_ROOT=$WORKSPACE/Build/PandaBoard/"$TARGET"_"$TARGET_TOOLS" +GENERATE_IMAGE=$WORKSPACE/PandaBoardPkg/Tools/chtool +FLASH_BOOT=$BUILD_ROOT/FV/PandaBoard_EFI_flashboot.fd + +if [[ ! -e $EDK_TOOLS_PATH/Source/C/bin ]]; +then + # build the tools if they don't yet exist + echo Building tools: $EDK_TOOLS_PATH + make -C $EDK_TOOLS_PATH +else + echo using prebuilt tools +fi + +# +# Build the edk2 PandaBoard code +# +build -p $WORKSPACE/PandaBoardPkg/PandaBoardPkg.dsc -a ARM -t $TARGET_TOOLS -b $BUILD_TARGET $other_args + +for arg in "$@" +do + if [[ $arg == clean ]]; then + # no need to post process if we are doing a clean + exit + elif [[ $arg == cleanall ]]; then + make -C $EDK_TOOLS_PATH clean + make -C $WORKSPACE/PandaBoardPkg/Tools clean + exit + + fi +done + + +# +# Build the tool used to patch the FLASH image to work with the Panda board ROM +# +if [[ ! -e $GENERATE_IMAGE ]]; +then + make -C $WORKSPACE/PandaBoardPkg/Tools +fi + +echo Patching FD to work with PandaBoard ROM +rm -f $FLASH_BOOT + +# +# Ram starts at 0x80000000 +# OMAP TRM defines 0x80008000 as the entry point +# The reset vector is caught by the mask ROM in the OMAP so that is why this entry +# point looks so strange. +# OMAP TRM section 26.4.8 has Image header information. (missing in OMAP TRM) +# +$WORKSPACE/PandaBoardPkg/Tools/mkheader.pl $BUILD_ROOT/FV/PANDABOARD_EFI.fd $FLASH_BOOT +$GENERATE_IMAGE -p OMAP4 -i $WORKSPACE/PandaBoardPkg/ConfigurationHeader.dat -O $FLASH_BOOT +rm -f $WORKSPACE/PandaBoardPkg/tmp.bin +cp $FLASH_BOOT $BUILD_ROOT/FV/MLO + +echo Creating debugger scripts +process_debug_scripts $WORKSPACE/PandaBoardPkg/Debugger_scripts + diff --git a/PandaBoardPkg/patches/0001-Add-call-to-early-prepi-init-in-ModuleEntryPoint.patch b/PandaBoardPkg/patches/0001-Add-call-to-early-prepi-init-in-ModuleEntryPoint.patch new file mode 100644 index 000000000..15b4d7f9a --- /dev/null +++ b/PandaBoardPkg/patches/0001-Add-call-to-early-prepi-init-in-ModuleEntryPoint.patch @@ -0,0 +1,35 @@ +From 9a22e1fed42e2ece74ae06546bc300bd0202e1ad Mon Sep 17 00:00:00 2001 +From: Olivier Deprez <o-deprez@ti.com> +Date: Fri, 1 Mar 2013 16:03:11 +0100 +Subject: [PATCH] Add call to early prepi init in ModuleEntryPoint + +omap4 requires an early call to an inner asm function to work +around a rom mask issue tied to dram initialization. +--- + ArmPlatformPkg/PrePi/ModuleEntryPoint.S | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/ArmPlatformPkg/PrePi/ModuleEntryPoint.S b/ArmPlatformPkg/PrePi/ModuleEntryPoint.S +index c0c20a9..66f0701 100755 +--- a/ArmPlatformPkg/PrePi/ModuleEntryPoint.S ++++ b/ArmPlatformPkg/PrePi/ModuleEntryPoint.S +@@ -24,12 +24,16 @@ + GCC_ASM_IMPORT(CEntryPoint) + GCC_ASM_IMPORT(ArmReadMpidr) + GCC_ASM_IMPORT(ArmPlatformStackSet) ++GCC_ASM_IMPORT(ArmPlatformPrePiBootAction) + GCC_ASM_EXPORT(_ModuleEntryPoint) + + StartupAddr: .word CEntryPoint + + + ASM_PFX(_ModuleEntryPoint): ++ // Perform early PrePi init ++ bl ASM_PFX(ArmPlatformPrePiBootAction) ++ + // Get ID of this CPU in Multicore system + bl ASM_PFX(ArmReadMpidr) + LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1) +-- +1.7.9.5 + diff --git a/PandaBoardPkg/patches/0001-fixes-sd-card-identification-on-panda.patch b/PandaBoardPkg/patches/0001-fixes-sd-card-identification-on-panda.patch new file mode 100644 index 000000000..a48c0e0f9 --- /dev/null +++ b/PandaBoardPkg/patches/0001-fixes-sd-card-identification-on-panda.patch @@ -0,0 +1,31 @@ +From 8d5bd220aee4a0b6e4c1dc9b3b54fe1b30c30e32 Mon Sep 17 00:00:00 2001 +From: Olivier Deprez <o-deprez@ti.com> +Date: Mon, 25 Jun 2012 11:06:31 +0200 +Subject: [PATCH] fixes sd card identification on panda + +It is observed with few SD cards that the protocol is hanging after issuing cmd5 and before cmd8. +Adding a small delay inbetween recovers and driver bring up is continuing without problem. +--- +EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c | 6 ++++++ + 1 files changed, 6 insertions(+), 0 deletions(-) + +diff --git a/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c b/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c +index 47f4aeb..f8d2cc4 100644 +--- a/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c ++++ b/EmbeddedPkg/Universal/MmcDxe/MmcBlockIo.c +@@ -229,6 +229,12 @@ MmcIdentificationMode ( + + // Are we using SDIO ? + Status = MmcHost->SendCommand (MmcHost, MMC_CMD5, 0); ++ ++#if 1 // Added for Panda Board ++ /* It seems few SD cards need some time to recover from this command? */ ++ MicroSecondDelay(1000); ++#endif ++ + if (Status == EFI_SUCCESS) { + DEBUG((EFI_D_ERROR, "MmcIdentificationMode(MMC_CMD5): Error - SDIO not supported.\n")); + return EFI_UNSUPPORTED; +-- +1.7.4.1 + diff --git a/PandaBoardPkg/patches/0001-remove-ASSERT-because-serial-not-yet-initialized.patch b/PandaBoardPkg/patches/0001-remove-ASSERT-because-serial-not-yet-initialized.patch new file mode 100644 index 000000000..a2f76c7da --- /dev/null +++ b/PandaBoardPkg/patches/0001-remove-ASSERT-because-serial-not-yet-initialized.patch @@ -0,0 +1,27 @@ +From e6b3ca0f765545b94e74de75d67b3c830f354c70 Mon Sep 17 00:00:00 2001 +From: Olivier Deprez <o-deprez@ti.com> +Date: Thu, 9 Aug 2012 16:12:40 +0200 +Subject: [PATCH] remove ASSERT because serial not yet initialized + +In CEntryPoint, this ASSERT statement calls serial print functions when serial port has not been initialized yet +This is causing board hand on panda board. +--- +ArmPlatformPkg/PrePi/PrePi.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/ArmPlatformPkg/PrePi/PrePi.c b/ArmPlatformPkg/PrePi/PrePi.c +index 11396d1..05385cc 100755 +--- a/ArmPlatformPkg/PrePi/PrePi.c ++++ b/ArmPlatformPkg/PrePi/PrePi.c +@@ -209,7 +209,7 @@ CEntryPoint ( + } + + // Write VBAR - The Vector table must be 32-byte aligned +- ASSERT (((UINT32)PrePiVectorTable & ((1 << 5)-1)) == 0); ++ //ASSERT (((UINT32)PrePiVectorTable & ((1 << 5)-1)) == 0); + ArmWriteVBar ((UINT32)PrePiVectorTable); + + // If not primary Jump to Secondary Main +-- +1.7.0.4 + diff --git a/PandaBoardPkg/readme.txt b/PandaBoardPkg/readme.txt new file mode 100644 index 000000000..fee17d8fb --- /dev/null +++ b/PandaBoardPkg/readme.txt @@ -0,0 +1,179 @@ +A. Overview +=========== + +The Panda packages are hosted on http://gitorious.org/omap-romcode/omap-edk2 +This repository contains the latest developments concerning UEFI on PandaBoard. +Contact: o-deprez@ti.com + +Patches from omap-edk2 tree are regularly merged on need basis to +http://git.linaro.org/gitweb?p=arm/uefi/uefi-next.git by Linaro maintainer. + +B. Environment setup +==================== + + 1. Toolchain + ------------ + +PandaBoardPkg was built/tested using gcc version 4.6 on an Ubuntu Precise machine. + +For a list of possible toolchains visit: +http://sourceforge.net/apps/mediawiki/tianocore/index.php?title=ArmPkg/Toolchain + + 2. Install necessary package + ---------------------------- + +Install uuid-dev package if not present already: + +sudo apt-get install uuid-dev + +C. Building +=========== + +Build information is found on uefi-next summary page: +http://git.linaro.org/gitweb?p=arm/uefi/uefi-next.git;a=summary + +After cloning the Linaro EDK2 tree and before compiling the PandaBoardPkg, +you must apply following patch to ArmPlatformPkg: + + git apply PandaBoardPkg/patches/0001-Add-call-to-early-prepi-init-in-ModuleEntryPoint.patch + +Compilation is done with following command: + + cd PandaBoardPkg + ./build.sh -b RELEASE + +Note: the Debug version is compiled by invoking build.sh without parameters or: + + ./build.sh -b DEBUG + +D. Running EDK2 on Panda +======================== + + 1. UEFI Shell + ------------- + +If you just intend to see how UEFI boots up and make a try with the shell, you +can do a raw copy of the firmware image to an SD card (e.g. /dev/sdc): + + dd if=edk2/Build/PandaBoard/RELEASE_ARMGCC/FV/MLO of=/dev/sdc + +Open your favorite serial terminal e.g. + minicom -b 115200 -D /dev/ttyS0 -8 --color=on -w -o + +Plug serial and power cables. + +After few seconds, the following boot menu shall pop up: + + [1] Linux from SD + - VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(1,MBR,0x00000000,0x3F,0 + x19FC0)/uImage + - Initrd: VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(1,MBR,0x0000000 + 0,0x3F,0x19FC0)/uInitrd + - Arguments: console=ttyO2,115200n8 root=/dev/mmcblk0p2 earlyprintk root + wait ro fixrtc nocompcache vram=48M omapfb.vram=0:24M + - LoaderType: Linux kernel with global FDT + ----------------------- + Global FDT Config + - VenHw(100C2CFA-B586-4198-9B4C-1683D195B1DA)/HD(1,MBR,0x00000000,0x3F,0 + x19FC0)/board.dtb + ----------------------- + [a] Boot Manager + [b] Shell + Start: + +From there, type 'b' for starting the shell. + + 2. Starting a Linux kernel + -------------------------- + +Check following page: http://releases.linaro.org/13.01/ubuntu/panda + +The easiest way is to get a full boot+filesystem image: +wget http://releases.linaro.org/13.01/ubuntu/boards/panda/panda-quantal_developer_20130128-58.img.gz + +Unzip and dd to an sd card as described on Linaro's website. + +Note: on OMAP, usage of earlyprintk statement on kernel command line looks incompatible with device tree. +Indeed early print routines use legacy machine type id to identify which uart module to use. +In case of device tree based boot the machine type passed to kernel entry by Bds is 0xFFFFFFFF, +which is unknown to earlyprintk routines and result in a hang. + +E. Boards tested +================ + +PandaBoard Rev EA2 - EBL and linux boot (PANDA_EDK2_080912) +PandaBoard Rev A3 - Shell and linux boot (PANDA_EDK2_030113) +PandaBoard ES Rev B1 - Shell (PANDA_EDK2_030113) + +Note: Panda ES did not fully boot up linaro 13.01 image thru UEFI (stuck at L2 cache init). + +F. chtool +========= + +The PandaBoardPkg/Tools directory contains a tool called chtool for creating +a Configuration Header block for use with the ROM Code boot sequence (in this port +it serves as configuration of OMAP DPLLs, system clocks, and initlization of external SDRAM). + +This tool is tracked in the following tree: git://gitorious.org/omap-romcode/chtool.git + +The version of chtool present in PandaBoardPkg is v0.4. + +G. History +========== + +03/01/2013 PANDA_EDK2_030113 + Added patch early PrePi init patch to ArmPlatformPkg + Board revision + Cleaned up Pad conf + Cleaned up setup clocks acceleration + Enable 1GB support + Add usb host support + Use null sd card's uuid + +01/28/2013 PANDA_EDK2_012813 + Created an edk2 top dir, moved packages in this dir + +11/21/2012 PANDA_EDK2_112112 + Add TWL6030 PMIC support + Update GPMC base address + Remove unused drivers (Flash, MMCHSDxe, InterruptDxe, SemihostFs) + Change PcdCoreCount to 2 + Change default boot type to Fdt + Update linux machine type to PandaBoard + +11/09/2012 PANDA_EDK2_110912 + Fix build.sh removing tmp.bin temporary file + Fix SerialPollGetControl with returning correct Control parm + Comment out Semihostfs from PandaBoardPkg.fdf + +08/09/2012 PANDA_EDK2_080912 + Boots linux "OMAP Ubuntu Core" kernel + +06/25/2012 PANDA_EDK2_062512 + First drop able to boot EBL + +H. Resources +============ + +Panda Board - TI OMAP4 +*http://pandaboard.org + +Beagle Board - TI OMAP3 +*http://sourceforge.net/apps/mediawiki/tianocore/index.php?title=BeagleBoardPkg + +ArmPlatformPkg - Generic package for ARM platforms +*http://sourceforge.net/apps/mediawiki/tianocore/index.php?title=ArmPlatformPkg + +I. To do/next steps +=================== + +-Enable Network +-Enable display/gui +-Add a CHMMCSD item in ROM's Configuration Header to accelerate image copy from SD to external RAM + +-DONE 03/01/2013 Enable USB host capability +-DONE 03/01/2013 Enable >512MiB external SDRAM +-DONE 03/01/2013 Clean PandaBoardLib for: detection of PandaBoard revision, pad conf, clocks speed up (if necessary) +-DONE 11/21/2012 Add PMIC management e.g. for SD card detection +-DONE 08/09/2012 Boot up linux kernel +-DONE 08/09/2012 Switch to linaro-uefi-2012.04 tag diff --git a/ShellPkg/ShellPkg.dsc b/ShellPkg/ShellPkg.dsc index 3284c1cdc..86c5d4d4e 100644 --- a/ShellPkg/ShellPkg.dsc +++ b/ShellPkg/ShellPkg.dsc @@ -48,7 +48,7 @@ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
- PathLib|ShellPkg/Library/BasePathLib/BasePathLib.inf
+ PathLib|MdeModulePkg/Library/BasePathLib/BasePathLib.inf
[LibraryClasses.ARM]
#
diff --git a/StdLib/StdLib.dsc b/StdLib/StdLib.dsc index b0309e2bf..e3fe99ad7 100644 --- a/StdLib/StdLib.dsc +++ b/StdLib/StdLib.dsc @@ -82,7 +82,7 @@ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
FileHandleLib|ShellPkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf
- PathLib|ShellPkg/Library/BasePathLib/BasePathLib.inf
+ PathLib|MdeModulePkg/Library/BasePathLib/BasePathLib.inf
###################################################################################################
#
diff --git a/StdLib/StdLib.inc b/StdLib/StdLib.inc index 0c8b04f7f..64604a327 100644 --- a/StdLib/StdLib.inc +++ b/StdLib/StdLib.inc @@ -28,7 +28,7 @@ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
FileHandleLib|ShellPkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf
- PathLib|ShellPkg/Library/BasePathLib/BasePathLib.inf
+ PathLib|MdeModulePkg/Library/BasePathLib/BasePathLib.inf
ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
#
|