HisiPkg: update the uart driver to fix the issue of truncated text when pasting text

Signed-off-by: Wei Xu <xuwei5@huawei.com>

4 files changed, 190 insertions, 190 deletions

diff --git a/HisiPkg/Drivers/PL390Gic/PL390GicDxe.c b/HisiPkg/Drivers/PL390Gic/PL390GicDxe.c
index cd653a944..8a80b667d 100644
--- a/HisiPkg/Drivers/PL390Gic/PL390GicDxe.c
+++ b/HisiPkg/Drivers/PL390Gic/PL390GicDxe.c
@@ -2,16 +2,16 @@
 

 Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>

 Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>

-Portions copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR> 

+Portions copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>

 Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.

 

-This program and the accompanying materials                          

-are licensed and made available under the terms and conditions of the BSD License         

-which accompanies this distribution.  The full text of the license may be found at        

-http://opensource.org/licenses/bsd-license.php                                            

-                                                                                          

-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     

-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.   

+This program and the accompanying materials

+are licensed and made available under the terms and conditions of the BSD License

+which accompanies this distribution.  The full text of the license may be found at

+http://opensource.org/licenses/bsd-license.php

+

+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

 

 Module Name:

 

@@ -75,7 +75,7 @@ RegisterInterruptSource (
     ASSERT(FALSE);

     return EFI_UNSUPPORTED;

   }

-  

+

   if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {

     return EFI_INVALID_PARAMETER;

   }

@@ -88,9 +88,9 @@ RegisterInterruptSource (
 

   // If the interrupt handler is unregistered then disable the interrupt

   if (NULL == Handler){

-  	return This->DisableInterruptSource (This, Source);

+       return This->DisableInterruptSource (This, Source);

   } else {

-  	return This->EnableInterruptSource (This, Source);

+       return This->EnableInterruptSource (This, Source);

   }

 }

 

@@ -113,19 +113,19 @@ EnableInterruptSource (
 {

   UINT32    RegOffset;

   UINTN     RegShift;

-  

+

   if (Source > mGicNumInterrupts) {

     ASSERT(FALSE);

     return EFI_UNSUPPORTED;

   }

-  

+

   // calculate enable register offset and bit position

   RegOffset = Source / 32;

   RegShift = Source % 32;

 

   // write set-enable register

   MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);

-  

+

   return EFI_SUCCESS;

 }

 

@@ -148,19 +148,19 @@ DisableInterruptSource (
 {

   UINT32    RegOffset;

   UINTN     RegShift;

-  

+

   if (Source > mGicNumInterrupts) {

     ASSERT(FALSE);

     return EFI_UNSUPPORTED;

   }

-  

+

   // Calculate enable register offset and bit position

   RegOffset = Source / 32;

   RegShift = Source % 32;

 

   // Write set-enable register

   MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);

-  

+

   return EFI_SUCCESS;

 }

 

@@ -185,27 +185,27 @@ GetInterruptSourceState (
 {

   UINT32    RegOffset;

   UINTN     RegShift;

-  

+

   if (Source > mGicNumInterrupts) {

     ASSERT(FALSE);

     return EFI_UNSUPPORTED;

   }

-  

+

   // calculate enable register offset and bit position

   RegOffset = Source / 32;

   RegShift = Source % 32;

-    

+

   if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {

     *InterruptState = FALSE;

   } else {

     *InterruptState = TRUE;

   }

-  

+

   return EFI_SUCCESS;

 }

 

 /**

-  Signal to the hardware that the End Of Intrrupt state 

+  Signal to the hardware that the End Of Intrrupt state

   has been reached.

 

   @param This     Instance pointer for this protocol

@@ -259,7 +259,7 @@ IrqInterruptHandler (
     // The special interrupt do not need to be acknowledge

     return;

   }

-  

+

   InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];

   if (InterruptHandler != NULL) {

     // Call the registered interrupt handler.

@@ -289,7 +289,7 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {
 

 /**

   Shutdown our hardware

-  

+

   DXE Core will disable interrupts and turn off the timer and disable interrupts

   after all the event handlers have run.

 

@@ -304,7 +304,7 @@ ExitBootServicesEvent (
   )

 {

   UINTN    Index;

-  

+

   // Acknowledge all pending interrupts

   for (Index = 0; Index < mGicNumInterrupts; Index++) {

     DisableInterruptSource (&gHardwareInterruptProtocol, Index);

@@ -345,7 +345,7 @@ InterruptDxeInitialize (
   UINTN                   RegShift;

   EFI_CPU_ARCH_PROTOCOL   *Cpu;

   UINT32                  CpuTarget;

-  

+

   // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0

   DEBUG_CODE_BEGIN();

   if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {

@@ -360,13 +360,13 @@ InterruptDxeInitialize (
 

   for (Index = 0; Index < mGicNumInterrupts; Index++) {

     DisableInterruptSource (&gHardwareInterruptProtocol, Index);

-    

-    // Set Priority 

+

+    // Set Priority

     RegOffset = Index / 4;

     RegShift = (Index % 4) * 8;

     MmioAndThenOr32 (

       PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),

-      ~(0xff << RegShift), 

+      ~(0xff << RegShift),

       ARM_GIC_DEFAULT_PRIORITY << RegShift

       );

   }

@@ -382,23 +382,23 @@ InterruptDxeInitialize (
 

   // Set priority mask reg to 0xff to allow all priorities through

   MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);

-  

+

   // Enable gic cpu interface

   MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);

 

   // Enable gic distributor

   MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);

-  

+

   // Initialize the array for the Interrupt Handlers

   gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);

-  

+

   Status = gBS->InstallMultipleProtocolInterfaces (

                   &gHardwareInterruptHandle,

                   &gHardwareInterruptProtocolGuid,   &gHardwareInterruptProtocol,

                   NULL

                   );

   ASSERT_EFI_ERROR (Status);

-  

+

   //

   // Get the CPU protocol that this driver requires.

   //

diff --git a/HisiPkg/Drivers/PL390Gic/PL390GicDxe.inf b/HisiPkg/Drivers/PL390Gic/PL390GicDxe.inf
index 1f2d3990e..84650e80e 100644
--- a/HisiPkg/Drivers/PL390Gic/PL390GicDxe.inf
+++ b/HisiPkg/Drivers/PL390Gic/PL390GicDxe.inf
@@ -1,5 +1,5 @@
 #/** @file

-#  

+#

 #  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>

 #  Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>

 #  Copyright Huawei Technologies Co., Ltd. 1998-2013. All rights reserved.

@@ -8,16 +8,16 @@
 #  are licensed and made available under the terms and conditions of the BSD License

 #  which accompanies this distribution.  The full text of the license may be found at

 #  http://opensource.org/licenses/bsd-license.php

-#  

+#

 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-#  

+#

 #**/

 

 [Defines]

   INF_VERSION                    = 0x00010005

   BASE_NAME                      = PL390GicDxe

-  FILE_GUID                      = DE371F7C-DEC4-4D21-ADF1-593ABCC15882 

+  FILE_GUID                      = DE371F7C-DEC4-4D21-ADF1-593ABCC15882

   MODULE_TYPE                    = DXE_DRIVER

   VERSION_STRING                 = 1.0

 

@@ -47,11 +47,11 @@
 [Protocols]

   gHardwareInterruptProtocolGuid

   gEfiCpuArchProtocolGuid

-  

+

 [FixedPcd.common]

   gArmTokenSpaceGuid.PcdGicDistributorBase

   gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase

-  

+

   gArmTokenSpaceGuid.PcdArmPrimaryCore

   gHwTokenSpaceGuid.PcdGicPrimaryCoreId

 

diff --git a/HisiPkg/Drivers/TimerDxe/TimerDxe.c b/HisiPkg/Drivers/TimerDxe/TimerDxe.c
index a95a6d006..5854a3656 100644
--- a/HisiPkg/Drivers/TimerDxe/TimerDxe.c
+++ b/HisiPkg/Drivers/TimerDxe/TimerDxe.c
@@ -3,14 +3,14 @@
 

   Copyright (c) 2011 ARM Ltd. All rights reserved.<BR>

   Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.

-  

-  This program and the accompanying materials                          

-  are licensed and made available under the terms and conditions of the BSD License         

-  which accompanies this distribution.  The full text of the license may be found at        

-  http://opensource.org/licenses/bsd-license.php                                            

 

-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     

-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

 

 **/

 

@@ -45,163 +45,163 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
 #define SRE_HITIMER32_OFFSET (0x00000020)

 

 /****************** Timer32 register addresses offset start ***********************/

-#define SRE_HITIMER32_LOAD_OFFSET              (0x0)      

-#define SRE_HITIMER32_VALUE_OFFSET             (0x4)      

-#define SRE_HITIMER32_CNTL_OFFSET              (0x8)     

-#define SRE_HITIMER32_INTC_OFFSET              (0xC)     

-#define SRE_HITIMER32_RIS_OFFSET               (0x10)    

-#define SRE_HITIMER32_MIS_OFFSET               (0x0014)  

-#define SRE_HITIMER32_BGLOAD_OFFSET            (0x18)   

+#define SRE_HITIMER32_LOAD_OFFSET              (0x0)

+#define SRE_HITIMER32_VALUE_OFFSET             (0x4)

+#define SRE_HITIMER32_CNTL_OFFSET              (0x8)

+#define SRE_HITIMER32_INTC_OFFSET              (0xC)

+#define SRE_HITIMER32_RIS_OFFSET               (0x10)

+#define SRE_HITIMER32_MIS_OFFSET               (0x0014)

+#define SRE_HITIMER32_BGLOAD_OFFSET            (0x18)

 /****************** end ******************************/

 

-#define SRE_HITIMER_NUM                        48        

-#define SRE_HITIMER64_START_INDEX              32        

+#define SRE_HITIMER_NUM                        48

+#define SRE_HITIMER64_START_INDEX              32

 #define SRE_HITIMER_ENCLK_SEL_BIT              (1 << 7)   /* Timer enable flag */

 

 

-#define SRE_HITIMER_CLK_IN_FREQ                187500000  

+#define SRE_HITIMER_CLK_IN_FREQ                187500000

 #define SRE_HITIMER_MICROSECOND_PER_SECOND     1000000

 

-#define SRE_HITIMER_DEFAULT_TICKS              100       

-#define SRE_HITIMER_RELOAD_TICKS               1         

+#define SRE_HITIMER_DEFAULT_TICKS              100

+#define SRE_HITIMER_RELOAD_TICKS               1

+

+#define SRE_HITIMER_INT_CLEAR                  (0x01)

+#define SRE_HITIMER_CNTL_ENABLE                (0x80)

+#define SRE_HITIMER_CNTL_MODE                  (0x40)

+#define SRE_HITIMER_CNTL_IRQ_ENABLE            (0x20)

+#define SRE_HITIMER_CNTL_SIZEMODE              (0x2)

 

-#define SRE_HITIMER_INT_CLEAR                  (0x01)    

-#define SRE_HITIMER_CNTL_ENABLE                (0x80)     

-#define SRE_HITIMER_CNTL_MODE                  (0x40)     

-#define SRE_HITIMER_CNTL_IRQ_ENABLE            (0x20)   

-#define SRE_HITIMER_CNTL_SIZEMODE              (0x2)    

-                                                                                

 

-#define SRE_HITIMER_CNTL_MODE_ONCE             0         

-#define SRE_HITIMER_CNTL_MODE_CYCLE            1      

-#define SRE_HITIMER_CNTL_IRQ_ON                1        

-#define SRE_HITIMER_CNTL_IRQ_OFF               0       

+#define SRE_HITIMER_CNTL_MODE_ONCE             0

+#define SRE_HITIMER_CNTL_MODE_CYCLE            1

+#define SRE_HITIMER_CNTL_IRQ_ON                1

+#define SRE_HITIMER_CNTL_IRQ_OFF               0

 

 

-#define SRE_D01_HITIMER01_INTVEC             (256)  

-#define SRE_D01_HITIMER23_INTVEC             (257)   

-#define SRE_D01_HITIMER45_INTVEC             (258)  

-#define SRE_D01_HITIMER67_INTVEC             (259) 

-#define SRE_D01_HITIMER89_INTVEC             (260)   

+#define SRE_D01_HITIMER01_INTVEC             (256)

+#define SRE_D01_HITIMER23_INTVEC             (257)

+#define SRE_D01_HITIMER45_INTVEC             (258)

+#define SRE_D01_HITIMER67_INTVEC             (259)

+#define SRE_D01_HITIMER89_INTVEC             (260)

 #define SRE_D01_HITIMER1011_INTVEC           (261)

-#define SRE_D01_HITIMER1213_INTVEC           (262) 

-#define SRE_D01_HITIMER1415_INTVEC           (263)   

-#define SRE_D01_HITIMER1617_INTVEC           (264)  

-#define SRE_D01_HITIMER1819_INTVEC           (265)  

-#define SRE_D01_HITIMER2021_INTVEC           (266)   

-#define SRE_D01_HITIMER2223_INTVEC           (267)   

-#define SRE_D01_HITIMER2425_INTVEC           (268) 

-#define SRE_D01_HITIMER2627_INTVEC           (269) 

-#define SRE_D01_HITIMER2829_INTVEC           (270)  

-#define SRE_D01_HITIMER3031_INTVEC           (271)   

-#define SRE_D01_HITIMER3233_INTVEC           (272) 

-#define SRE_D01_HITIMER3435_INTVEC           (273) 

-#define SRE_D01_HITIMER3637_INTVEC           (274)  

-#define SRE_D01_HITIMER3839_INTVEC           (275)   

-#define SRE_D01_HITIMER4041_INTVEC           (276) 

-#define SRE_D01_HITIMER4243_INTVEC           (277) 

-#define SRE_D01_HITIMER4445_INTVEC           (278)  

-#define SRE_D01_HITIMER4647_INTVEC           (279)  

+#define SRE_D01_HITIMER1213_INTVEC           (262)

+#define SRE_D01_HITIMER1415_INTVEC           (263)

+#define SRE_D01_HITIMER1617_INTVEC           (264)

+#define SRE_D01_HITIMER1819_INTVEC           (265)

+#define SRE_D01_HITIMER2021_INTVEC           (266)

+#define SRE_D01_HITIMER2223_INTVEC           (267)

+#define SRE_D01_HITIMER2425_INTVEC           (268)

+#define SRE_D01_HITIMER2627_INTVEC           (269)

+#define SRE_D01_HITIMER2829_INTVEC           (270)

+#define SRE_D01_HITIMER3031_INTVEC           (271)

+#define SRE_D01_HITIMER3233_INTVEC           (272)

+#define SRE_D01_HITIMER3435_INTVEC           (273)

+#define SRE_D01_HITIMER3637_INTVEC           (274)

+#define SRE_D01_HITIMER3839_INTVEC           (275)

+#define SRE_D01_HITIMER4041_INTVEC           (276)

+#define SRE_D01_HITIMER4243_INTVEC           (277)

+#define SRE_D01_HITIMER4445_INTVEC           (278)

+#define SRE_D01_HITIMER4647_INTVEC           (279)

 

 UINT32 gRegBase = SRE_HITIMER_ADDR;

 #define SC_CTRL 0xe3e00000

 

 void HITIMER_Start()

 {

-		UINT32 ulRegAddr;

-		UINT32 ulVal = 0;

-		UINT32 ulMask;

-        

+               UINT32 ulRegAddr;

+               UINT32 ulVal = 0;

+               UINT32 ulMask;

+

         ulVal = *(UINT32*)SC_CTRL;

         ulVal |= BIT17 | BIT16 | BIT18 | BIT19;

         *(UINT32*)SC_CTRL = ulVal;

 

-		/*timer mode*/

-		ulMask = SRE_HITIMER_CNTL_MODE; //BIT6

-		ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET; 

-		ulVal = *(UINT32*)ulRegAddr;

-		ulVal = ulVal;

-		ulVal |= ulMask; /*cycle*/        

+               /*timer mode*/

+               ulMask = SRE_HITIMER_CNTL_MODE; //BIT6

+               ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;

+               ulVal = *(UINT32*)ulRegAddr;

+               ulVal = ulVal;

+               ulVal |= ulMask; /*cycle*/

         *(UINT32*)ulRegAddr = ulVal;

 

-		/*int mode*/

-		ulMask = SRE_HITIMER_CNTL_IRQ_ENABLE; //BIT5

-		ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;

-		ulVal = *(UINT32*)ulRegAddr;

-		ulVal = ulVal;

-		ulVal |= ulMask;

+               /*int mode*/

+               ulMask = SRE_HITIMER_CNTL_IRQ_ENABLE; //BIT5

+               ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;

+               ulVal = *(UINT32*)ulRegAddr;

+               ulVal = ulVal;

+               ulVal |= ulMask;

         //DEBUG((EFI_D_ERROR, "int mode = %0x at %0x\n", ulVal, ulRegAddr));

-		*(UINT32*)ulRegAddr = ulVal;

-

-		/*start up*/

-		ulMask = (SRE_HITIMER_ENCLK_SEL_BIT | SRE_HITIMER_CNTL_SIZEMODE); //BIT7 | BIT1

-		ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;

-		ulVal = *(UINT32*)ulRegAddr;

-		ulVal = ulVal;

-		ulVal |= ulMask;

+               *(UINT32*)ulRegAddr = ulVal;

+

+               /*start up*/

+               ulMask = (SRE_HITIMER_ENCLK_SEL_BIT | SRE_HITIMER_CNTL_SIZEMODE); //BIT7 | BIT1

+               ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;

+               ulVal = *(UINT32*)ulRegAddr;

+               ulVal = ulVal;

+               ulVal |= ulMask;

         //DEBUG((EFI_D_ERROR, "start up = %0x at %0x\n", ulVal, ulRegAddr));

-		*(UINT32*)ulRegAddr = ulVal;

+               *(UINT32*)ulRegAddr = ulVal;

 

 }

 

 void HITMER_ClearInt()

 {

-	UINT32 ulRegAddr;

-	UINT32 ulVal = 0;

+       UINT32 ulRegAddr;

+       UINT32 ulVal = 0;

 

 

-	ulRegAddr = gRegBase + SRE_HITIMER32_INTC_OFFSET;

-	ulVal = SRE_HITIMER_INT_CLEAR;

+       ulRegAddr = gRegBase + SRE_HITIMER32_INTC_OFFSET;

+       ulVal = SRE_HITIMER_INT_CLEAR;

     //DEBUG((EFI_D_ERROR, "HITMER_ClearInt = %0x at %0x\n", ulVal, ulRegAddr));

-	*(UINT32*)ulRegAddr = ulVal;

+       *(UINT32*)ulRegAddr = ulVal;

 

 }

 

 void DisableTimer()

 {

-	UINT32 ulRegAddr;

-	UINT32 ulVal = 0;

-	UINT32 ulMask;

-

-	/*disable*/

-	ulMask = SRE_HITIMER_ENCLK_SEL_BIT;

-	ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;

-	ulVal = *(UINT32*)ulRegAddr;

-	ulVal = ulVal;

-	ulVal &= (~ulMask);

+       UINT32 ulRegAddr;

+       UINT32 ulVal = 0;

+       UINT32 ulMask;

+

+       /*disable*/

+       ulMask = SRE_HITIMER_ENCLK_SEL_BIT;

+       ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;

+       ulVal = *(UINT32*)ulRegAddr;

+       ulVal = ulVal;

+       ulVal &= (~ulMask);

     //DEBUG((EFI_D_ERROR, "DisableTimer = %0x at %0x\n", ulVal, ulRegAddr));

-	*(UINT32*)ulRegAddr = ulVal;

+       *(UINT32*)ulRegAddr = ulVal;

 

 }

 

 void EnableTimer()

 {

-	UINT32 ulRegAddr;

-	UINT32 ulVal = 1;

-	UINT32 ulMask;

-

-	/*disable*/

-	ulMask = SRE_HITIMER_ENCLK_SEL_BIT;

-	ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;

-	ulVal = *(UINT32*)ulRegAddr;

-	ulVal = ulVal;

-	ulVal |= ulMask;

+       UINT32 ulRegAddr;

+       UINT32 ulVal = 1;

+       UINT32 ulMask;

+

+       /*disable*/

+       ulMask = SRE_HITIMER_ENCLK_SEL_BIT;

+       ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;

+       ulVal = *(UINT32*)ulRegAddr;

+       ulVal = ulVal;

+       ulVal |= ulMask;

     //DEBUG((EFI_D_ERROR, "EnableTimer = %0x at %0x\n", ulVal, ulRegAddr));

-	*(UINT32*)ulRegAddr = ulVal;

+       *(UINT32*)ulRegAddr = ulVal;

 

 }

 

 /**

-  This function registers the handler NotifyFunction so it is called every time 

-  the timer interrupt fires.  It also passes the amount of time since the last 

-  handler call to the NotifyFunction.  If NotifyFunction is NULL, then the 

-  handler is unregistered.  If the handler is registered, then EFI_SUCCESS is 

-  returned.  If the CPU does not support registering a timer interrupt handler, 

-  then EFI_UNSUPPORTED is returned.  If an attempt is made to register a handler 

-  when a handler is already registered, then EFI_ALREADY_STARTED is returned.  

-  If an attempt is made to unregister a handler when a handler is not registered, 

-  then EFI_INVALID_PARAMETER is returned.  If an error occurs attempting to 

-  register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR 

+  This function registers the handler NotifyFunction so it is called every time

+  the timer interrupt fires.  It also passes the amount of time since the last

+  handler call to the NotifyFunction.  If NotifyFunction is NULL, then the

+  handler is unregistered.  If the handler is registered, then EFI_SUCCESS is

+  returned.  If the CPU does not support registering a timer interrupt handler,

+  then EFI_UNSUPPORTED is returned.  If an attempt is made to register a handler

+  when a handler is already registered, then EFI_ALREADY_STARTED is returned.

+  If an attempt is made to unregister a handler when a handler is not registered,

+  then EFI_INVALID_PARAMETER is returned.  If an error occurs attempting to

+  register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR

   is returned.

 

   @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.

@@ -254,17 +254,17 @@ ExitBootServicesEvent (
 

 /**

 

-  This function adjusts the period of timer interrupts to the value specified 

-  by TimerPeriod.  If the timer period is updated, then the selected timer 

-  period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned.  If 

-  the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.  

-  If an error occurs while attempting to update the timer period, then the 

-  timer hardware will be put back in its state prior to this call, and 

-  EFI_DEVICE_ERROR is returned.  If TimerPeriod is 0, then the timer interrupt 

-  is disabled.  This is not the same as disabling the CPU's interrupts.  

-  Instead, it must either turn off the timer hardware, or it must adjust the 

-  interrupt controller so that a CPU interrupt is not generated when the timer 

-  interrupt fires. 

+  This function adjusts the period of timer interrupts to the value specified

+  by TimerPeriod.  If the timer period is updated, then the selected timer

+  period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned.  If

+  the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.

+  If an error occurs while attempting to update the timer period, then the

+  timer hardware will be put back in its state prior to this call, and

+  EFI_DEVICE_ERROR is returned.  If TimerPeriod is 0, then the timer interrupt

+  is disabled.  This is not the same as disabling the CPU's interrupts.

+  Instead, it must either turn off the timer hardware, or it must adjust the

+  interrupt controller so that a CPU interrupt is not generated when the timer

+  interrupt fires.

 

   @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.

   @param  TimerPeriod      The rate to program the timer interrupt in 100 nS units. If

@@ -288,9 +288,9 @@ TimerDriverSetTimerPeriod (
   )

 {

   UINT64      TimerTicks;

-  

+

   UINT32 ulRegAddr;

-  

+

   // always disable the timer

   DisableTimer ();

 

@@ -301,12 +301,12 @@ TimerDriverSetTimerPeriod (
 

     TimerTicks = MultU64x32 (TimerTicks, (PcdGet32(PcdArmArchTimerFreqInHz)/1000000));

     #endif

-    

+

     TimerTicks = DivU64x32 (TimerPeriod, 100);

     TimerTicks = MultU64x32 (TimerTicks, (PcdGet32(PcdArmArchTimerFreqInHz)/100000));

-    

+

     //ArmArchTimerSetTimerVal((UINTN)TimerTicks);

-    

+

     ulRegAddr = gRegBase + SRE_HITIMER32_LOAD_OFFSET;

     //DEBUG((EFI_D_ERROR, "TimerTicks1 = %0x at %0x ======\n", TimerTicks, ulRegAddr));

     *(UINT32*)ulRegAddr = TimerTicks;

@@ -324,9 +324,9 @@ TimerDriverSetTimerPeriod (
 }

 

 /**

-  This function retrieves the period of timer interrupts in 100 ns units, 

-  returns that value in TimerPeriod, and returns EFI_SUCCESS.  If TimerPeriod 

-  is NULL, then EFI_INVALID_PARAMETER is returned.  If a TimerPeriod of 0 is 

+  This function retrieves the period of timer interrupts in 100 ns units,

+  returns that value in TimerPeriod, and returns EFI_SUCCESS.  If TimerPeriod

+  is NULL, then EFI_INVALID_PARAMETER is returned.  If a TimerPeriod of 0 is

   returned, then the timer is currently disabled.

 

   @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.

@@ -354,12 +354,12 @@ TimerDriverGetTimerPeriod (
 }

 

 /**

-  This function generates a soft timer interrupt. If the platform does not support soft 

-  timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned. 

-  If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler() 

-  service, then a soft timer interrupt will be generated. If the timer interrupt is 

-  enabled when this service is called, then the registered handler will be invoked. The 

-  registered handler should not be able to distinguish a hardware-generated timer 

+  This function generates a soft timer interrupt. If the platform does not support soft

+  timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.

+  If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()

+  service, then a soft timer interrupt will be generated. If the timer interrupt is

+  enabled when this service is called, then the registered handler will be invoked. The

+  registered handler should not be able to distinguish a hardware-generated timer

   interrupt from a software-generated timer interrupt.

 

   @param  This             The EFI_TIMER_ARCH_PROTOCOL instance.

@@ -456,7 +456,7 @@ TimerInterruptHandler (
 

     // Signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers

     gInterrupt->EndOfInterrupt (gInterrupt, Source);

-    

+

 

     if (mTimerNotifyFunction) {

       mTimerNotifyFunction (mTimerPeriod);

@@ -466,7 +466,7 @@ TimerInterruptHandler (
     //TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod));

   //}

   //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));

-  

+

   //DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));

 

   // Enable timer interrupts

@@ -502,7 +502,7 @@ TimerInitialize (
   EFI_HANDLE  Handle = NULL;

   EFI_STATUS  Status;

 

-  

+

   // Find the interrupt controller protocol.  ASSERT if not found.

   Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);

   ASSERT_EFI_ERROR (Status);

diff --git a/HisiPkg/Drivers/TimerDxe/TimerDxe.inf b/HisiPkg/Drivers/TimerDxe/TimerDxe.inf
index 6dd90ecd2..9661cd113 100644
--- a/HisiPkg/Drivers/TimerDxe/TimerDxe.inf
+++ b/HisiPkg/Drivers/TimerDxe/TimerDxe.inf
@@ -1,23 +1,23 @@
 #/** @file

-#  

+#

 #    Component description file for Timer DXE module

-#  

+#

 #  Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>

 #  Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.

 #  This program and the accompanying materials

 #  are licensed and made available under the terms and conditions of the BSD License

 #  which accompanies this distribution.  The full text of the license may be found at

 #  http://opensource.org/licenses/bsd-license.php

-#  

+#

 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

-#  

+#

 #**/

 

 [Defines]

   INF_VERSION                    = 0x00010005

   BASE_NAME                      = ArmTimerDxe

-  FILE_GUID                      = 49ea041e-6752-42ca-b0b1-7344fe2546b7 

+  FILE_GUID                      = 49ea041e-6752-42ca-b0b1-7344fe2546b7

   MODULE_TYPE                    = DXE_DRIVER

   VERSION_STRING                 = 1.0

 

@@ -41,19 +41,19 @@
   BaseMemoryLib

   DebugLib

   UefiDriverEntryPoint

-  IoLib  

+  IoLib

 

 [Guids]

 

 [Protocols]

-  gEfiTimerArchProtocolGuid  

+  gEfiTimerArchProtocolGuid

   gHardwareInterruptProtocolGuid

 

 [Pcd.common]

   gEmbeddedTokenSpaceGuid.PcdTimerPeriod

-  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum  

+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum

   gArmTokenSpaceGuid.PcdArmArchTimerIntrNum

-  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz  

+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz

 

 [Depex]

   gHardwareInterruptProtocolGuid