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| author | Olivier Martin <olivier.martin@arm.com> | 2014-07-29 14:09:10 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-07-29 14:09:10 +0000 |
| commit | f3c5066fa6e5e62c0584101d3a17c1e9ee523dd1 (patch) | |
| tree | 2a37d6c29cab32979d9d7b9140da22644ecfe7b4 | |
| parent | 6a44c2273279b17f0c4a80be0ae8104d27333542 (diff) | |
ArmPkg/AArch64.h: Added Exception Syndrome Register definitions
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15709 6f19259b-4bc3-4df7-8a09-765794883524
| -rw-r--r-- | ArmPkg/Include/Chipset/AArch64.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h index b63f577ac..040074024 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -62,6 +62,13 @@ #define ARM_HCR_TSC BIT19
#define ARM_HCR_TGE BIT27
+// Exception Syndrome Register
+#define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))
+#define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))
+
+#define AARCH64_ESR_EC_SMC32 (0x13 << 26)
+#define AARCH64_ESR_EC_SMC64 (0x17 << 26)
+
// AArch64 Exception Level
#define AARCH64_EL3 0xC
#define AARCH64_EL2 0x8
|