diff options
| author | Liming Gao <liming.gao@intel.com> | 2014-11-19 02:30:21 +0000 |
|---|---|---|
| committer | lgao4 <lgao4@Edk2> | 2014-11-19 02:30:21 +0000 |
| commit | c9e0bba3855c18728199b99dada6d03102ca331c (patch) | |
| tree | 6613935ad8796e8c0e54567622a79de0e93046c0 | |
| parent | 18a7dbbc020f0aec63ae71d034f32617da1eec9e (diff) | |
MdeModulePkg BaseSerialPortLib16550: Correct MemoryLimit and MemoryBase offset.
Their offset in PCI-to-PCI Bridge Configuration Space.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Guo Dong <guo.dong@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16402 6f19259b-4bc3-4df7-8a09-765794883524
| -rw-r--r-- | MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c index d21c00c5a..0ade9b231 100644 --- a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c +++ b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c @@ -244,8 +244,8 @@ GetSerialRegisterBase ( // Retrieve and verify the I/O or MMIO decode window in the PCI to PCI Bridge
//
if (PcdGetBool (PcdSerialUseMmio)) {
- MemoryLimit = PciRead16 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, MemoryLimit)) & 0xfff0;
- MemoryBase = PciRead16 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, MemoryBase)) & 0xfff0;
+ MemoryLimit = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit)) & 0xfff0;
+ MemoryBase = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase)) & 0xfff0;
//
// If PCI Bridge MMIO window is disabled, then return 0
@@ -263,17 +263,17 @@ GetSerialRegisterBase ( ParentMemoryBase = MemoryBase;
ParentMemoryLimit = MemoryLimit;
} else {
- IoLimit = PciRead8 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, IoLimit));
+ IoLimit = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimit));
if ((IoLimit & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
IoLimit = IoLimit >> 4;
} else {
- IoLimit = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, IoLimitUpper16)) << 4) | (IoLimit >> 4);
+ IoLimit = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimitUpper16)) << 4) | (IoLimit >> 4);
}
- IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, IoBase));
+ IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase));
if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {
IoBase = IoBase >> 4;
} else {
- IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_BRIDGE_CONTROL_REGISTER, IoBaseUpper16)) << 4) | (IoBase >> 4);
+ IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16)) << 4) | (IoBase >> 4);
}
//
|