diff options
| author | wei.xu <xuwei5@huawei.com> | 2014-05-29 09:45:11 +0800 |
|---|---|---|
| committer | Wei Xu <xuwei5@huawei.com> | 2014-12-10 08:33:43 +0800 |
| commit | a89a545683972d7a8a7249b3a121ae7f5ab071b4 (patch) | |
| tree | 207ce06722994984e01d983b8aa7654cb06fe1c7 | |
| parent | 5f7f7bbaa86d81caa87148eedf82af5a51423b73 (diff) | |
HisiPkg: update the uart driver to fix the issue of truncated text when pasting text
Signed-off-by: Wei Xu <xuwei5@huawei.com>
19 files changed, 323 insertions, 345 deletions
diff --git a/HisiPkg/D01BoardPkg/Application/Ebl/Ebl.efi b/HisiPkg/D01BoardPkg/Application/Ebl/Ebl.efi Binary files differindex bf0477c0a..50c6aaa9c 100644 --- a/HisiPkg/D01BoardPkg/Application/Ebl/Ebl.efi +++ b/HisiPkg/D01BoardPkg/Application/Ebl/Ebl.efi diff --git a/HisiPkg/D01BoardPkg/D01BoardPkg.dsc b/HisiPkg/D01BoardPkg/D01BoardPkg.dsc index bf856d5d6..cece5aa28 100644 --- a/HisiPkg/D01BoardPkg/D01BoardPkg.dsc +++ b/HisiPkg/D01BoardPkg/D01BoardPkg.dsc @@ -41,12 +41,12 @@ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
- NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
- DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
- HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
- UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
- UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
- IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
[LibraryClasses.common.SEC]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
@@ -55,7 +55,7 @@ [BuildOptions]
- RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8 --fpu=softvfp -I$(WORKSPACE)/HisiPkg/Include/Platform
+ RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 --fpu=softvfp -I$(WORKSPACE)/HisiPkg/Include/Platform
GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a -I$(WORKSPACE)/HisiPkg/Include/Platform
@@ -105,7 +105,7 @@ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x40028000
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x8000
- gHwTokenSpaceGuid.PcdEmbeddedBiosVersion|"Linaro_BIOS_V1.6"
+ gHwTokenSpaceGuid.PcdEmbeddedBiosVersion|"Linaro_BIOS_V1.9"
# System Memory (1GB)
@@ -126,11 +126,13 @@ ## PL011 - Serial Terminal
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0xe4007000
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|9600
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+ gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000
+
#
# ARM PL390 General Interrupt Controller
@@ -142,20 +144,19 @@ # ARM OS Loader
#
# Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
- gArmTokenSpaceGuid.PcdArmMachineType|2272
+ gArmTokenSpaceGuid.PcdArmMachineType|0xffffffff
#gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"SemiHosting"
gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Ramdisk"
#gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/zImage"
gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenMsg(06ED4DD0-FF78-11D3-BDC4-00A0C94053D1,0000000000000000)/uImage"
gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L"VenMsg(06ED4DD0-FF78-11D3-BDC4-00A0C94053D1,0000000000000000)/initrd"
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"mem=256M console=ttyAMA0,9600"
+ gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|"mem=256M console=ttyAMA0,115200"
gArmPlatformTokenSpaceGuid.PcdDefaultBootType|1
# Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(9600,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(9600,8,N,1)/VenPcAnsi()"
-
- gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L"VenHw(61EDB580-1739-4912-A4E8-D05F90FC8D79)/HD(1,MBR,0x00000000,0x3F,0x19FC0)/board.dtb"
+ #gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
+ #gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+ #gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|10
#
# ARM L2x0 PCDs
@@ -171,8 +172,8 @@ gHwTokenSpaceGuid.PcdGPIO0Base|0xe4000000
gArmTokenSpaceGuid.PcdSysCtrlBase|0xe3e00000
- gArmTokenSpaceGuid.PcdTimerBase|0xe3000000
- gArmTokenSpaceGuid.PcdTimer0InterruptNum|130
+ gArmTokenSpaceGuid.PcdTimerBase|0xe3000000
+ gArmTokenSpaceGuid.PcdTimer0InterruptNum|130
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"EVB_SECURE_UEFI_BIOS"
diff --git a/HisiPkg/D01BoardPkg/D01BoardPkg.dsc.inc b/HisiPkg/D01BoardPkg/D01BoardPkg.dsc.inc index 277e0fb65..1b0c40702 100644 --- a/HisiPkg/D01BoardPkg/D01BoardPkg.dsc.inc +++ b/HisiPkg/D01BoardPkg/D01BoardPkg.dsc.inc @@ -70,9 +70,18 @@ # ARM PL354 SMC Driver
PL35xSmcLib|ArmPlatformPkg/Drivers/PL35xSmc/PL35xSmc.inf
# ARM PL011 UART Driver
- PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
+
+
SerialPortLib|HisiPkg/Library/SerialPortLib/SerialPortLib.inf
SerialPortExtLib|HisiPkg/Library/SerialPortLib/SerialPortLib.inf
+
+ SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+ #SerialPortLib|ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf
+ #SerialPortExtLib|EmbeddedPkg/Library/TemplateSerialPortExtLib/TemplateSerialPortExtLib.inf
+
+ #PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf
+ #SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+ #SerialPortExtLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortExtLib.inf
ResetWdtLib|HisiPkg/D01BoardPkg/Library/ResetWdtLib/ResetWdtLib.inf
BspUartLib|HisiPkg/Library/BspUartLib/BspUartLib.inf
PinIoLib|HisiPkg/Library/PinIoLib/PinIoLib.inf
@@ -92,10 +101,7 @@ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
-
- SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
- #SerialPortExtLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortExtLib.inf
ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
# BDS Libraries
@@ -336,7 +342,7 @@ gArmPlatformTokenSpaceGuid.PcdDefaultBootType|1
# Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()"
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|10
diff --git a/HisiPkg/D01BoardPkg/D01BoardPkg.fdf b/HisiPkg/D01BoardPkg/D01BoardPkg.fdf index 427e5fe2c..d5037c7f1 100644 --- a/HisiPkg/D01BoardPkg/D01BoardPkg.fdf +++ b/HisiPkg/D01BoardPkg/D01BoardPkg.fdf @@ -2,14 +2,14 @@ #
# Copyright (c) 2011, ARM Limited. All rights reserved.
# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
################################################################################
@@ -112,10 +112,10 @@ READ_STATUS = TRUE READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
- INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
#
- # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
#
INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
@@ -131,7 +131,7 @@ READ_LOCK_STATUS = TRUE INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
-
+
#
# Multiple Console IO support
#
@@ -154,14 +154,14 @@ READ_LOCK_STATUS = TRUE # Semi-hosting filesystem
#
#INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
-
+
# RamDisk filesystem
INF HisiPkg/Drivers/ramdisk/ramdisk.inf
-
+
#NorFlash Driver
INF HisiPkg/Drivers/FlashDriver/FlashDriver.inf
-
+
INF HisiPkg/Drivers/NandFlash/NandFlashDxe.inf
#
@@ -173,7 +173,7 @@ READ_LOCK_STATUS = TRUE INF RuleOverride = BINARY FatBinPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
-
+
INF HisiPkg/Drivers/AtaAtapiPassThru/AtaAtapiPassThru.inf
INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
@@ -200,11 +200,11 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
#
- # UEFI application (Shell Embedded Boot Loader)
- #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
INF HisiPkg/D01BoardPkg/Application/Ebl/Ebl.inf
INF ShellBinPkg/UefiShell/UefiShell.inf
-
+
#
# Bds
#
@@ -242,7 +242,7 @@ READ_LOCK_STATUS = TRUE # INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
# INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
#!endif
-
+
FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
SECTION FV_IMAGE = FVMAIN
@@ -261,7 +261,7 @@ READ_LOCK_STATUS = TRUE ############################################################################
-# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
############################################################################
#
#[Rule.Common.DXE_DRIVER]
@@ -282,7 +282,7 @@ READ_LOCK_STATUS = TRUE FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
-
+
[Rule.Common.SEC.BINARY]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 32 |.efi
@@ -291,14 +291,14 @@ READ_LOCK_STATUS = TRUE [Rule.Common.PEI_CORE]
FILE PEI_CORE = $(NAMED_GUID) {
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING ="$(MODULE_NAME)" Optional
+ UI STRING ="$(MODULE_NAME)" Optional
}
[Rule.Common.PEIM]
FILE PEIM = $(NAMED_GUID) {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
- UI STRING="$(MODULE_NAME)" Optional
+ UI STRING="$(MODULE_NAME)" Optional
}
[Rule.Common.PEIM.TIANOCOMPRESSED]
@@ -322,7 +322,7 @@ READ_LOCK_STATUS = TRUE PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
}
-
+
[Rule.Common.UEFI_DRIVER.BINARY]
FILE DRIVER = $(NAMED_GUID) {
DXE_DEPEX DXE_DEPEX Optional |.depex
@@ -352,10 +352,10 @@ READ_LOCK_STATUS = TRUE [Rule.Common.UEFI_APPLICATION]
FILE APPLICATION = $(NAMED_GUID) {
- UI STRING ="$(MODULE_NAME)" Optional
+ UI STRING ="$(MODULE_NAME)" Optional
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
-
+
[Rule.Common.UEFI_APPLICATION.BINARY]
FILE APPLICATION = $(NAMED_GUID) {
PE32 PE32 |.efi
@@ -367,4 +367,3 @@ READ_LOCK_STATUS = TRUE RAW ACPI Optional |.acpi
RAW ASL Optional |.aml
}
-
diff --git a/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSM.c b/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSM.c index 3cb42acfd..eaaf5ab64 100644 --- a/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSM.c +++ b/HisiPkg/D01BoardPkg/Library/D01LibRTSM/RTSM.c @@ -2,14 +2,14 @@ *
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
@@ -71,7 +71,7 @@ ARM_CORE_INFO mVersatileExpressMpCoreInfoTable[] = { {
// Cluster 1, Core 0
0x1, 0x0,
-
+
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
@@ -81,7 +81,7 @@ ARM_CORE_INFO mVersatileExpressMpCoreInfoTable[] = { {
// Cluster 1, Core 1
0x1, 0x1,
-
+
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
@@ -91,7 +91,7 @@ ARM_CORE_INFO mVersatileExpressMpCoreInfoTable[] = { {
// Cluster 1, Core 2
0x1, 0x2,
-
+
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
@@ -101,7 +101,7 @@ ARM_CORE_INFO mVersatileExpressMpCoreInfoTable[] = { {
// Cluster 1, Core 3
0x1, 0x3,
-
+
// MP Core MailBox Set/Get/Clear Addresses and Clear Value
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
(EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
@@ -168,7 +168,7 @@ PrePeiCoreGetMpCoreInfo ( OUT ARM_CORE_INFO **ArmCoreTable
)
{
-#if 0
+#if 0
UINT32 ProcType;
ProcType = MmioRead32 (ARM_VE_SYS_PROCID0_REG) & ARM_VE_SYS_PROC_ID_MASK;
@@ -181,10 +181,10 @@ PrePeiCoreGetMpCoreInfo ( return EFI_UNSUPPORTED;
}
#else
-
+
*CoreCount = 2 * ArmGetCpuCountPerCluster ();
*ArmCoreTable = mVersatileExpressMpCoreInfoTable;
-
+
return EFI_SUCCESS;
#endif
}
diff --git a/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/D01SecLib.inf b/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/D01SecLib.inf index e6c96cc86..2a88d3959 100644 --- a/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/D01SecLib.inf +++ b/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/D01SecLib.inf @@ -1,14 +1,14 @@ #/* @file
# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#*/
@@ -19,7 +19,6 @@ MODULE_TYPE = BASE
VERSION_STRING = 1.0
LIBRARY_CLASS = ArmPlatformSecLib
-
+
[binaries.common]
LIB|RTSMArmD01SecLib.lib
-
diff --git a/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/RTSMArmD01SecLib.lib b/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/RTSMArmD01SecLib.lib Binary files differindex 3a5489921..a6b5ba005 100644 --- a/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/RTSMArmD01SecLib.lib +++ b/HisiPkg/D01BoardPkg/Library/D01SecLibRTSM/RTSMArmD01SecLib.lib diff --git a/HisiPkg/D01BoardPkg/Sec/Sec/Sec.c b/HisiPkg/D01BoardPkg/Sec/Sec/Sec.c index d66916b0f..31b2669f8 100644 --- a/HisiPkg/D01BoardPkg/Sec/Sec/Sec.c +++ b/HisiPkg/D01BoardPkg/Sec/Sec/Sec.c @@ -3,14 +3,14 @@ *
* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
* Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-*
-* This program and the accompanying materials
-* are licensed and made available under the terms and conditions of the BSD License
-* which accompanies this distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
@@ -167,7 +167,7 @@ TrustedWorldInitialization ( // Write to CP15 Non-secure Access Control Register
ArmWriteNsacr (PcdGet32 (PcdArmNsacr));
-
+
/* set SMP bit */
ArmWriteAuxCr(ArmReadAuxCr() | BIT6);
@@ -195,4 +195,3 @@ NonTrustedWorldTransition ( // PEI Core should always load and never return
ASSERT (FALSE);
}
-
diff --git a/HisiPkg/Drivers/PL390Gic/PL390GicDxe.c b/HisiPkg/Drivers/PL390Gic/PL390GicDxe.c index cd653a944..8a80b667d 100644 --- a/HisiPkg/Drivers/PL390Gic/PL390GicDxe.c +++ b/HisiPkg/Drivers/PL390Gic/PL390GicDxe.c @@ -2,16 +2,16 @@ Copyright (c) 2009, Hewlett-Packard Company. All rights reserved.<BR>
Portions copyright (c) 2010, Apple Inc. All rights reserved.<BR>
-Portions copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
+Portions copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution. The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
Module Name:
@@ -75,7 +75,7 @@ RegisterInterruptSource ( ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
-
+
if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -88,9 +88,9 @@ RegisterInterruptSource ( // If the interrupt handler is unregistered then disable the interrupt
if (NULL == Handler){
- return This->DisableInterruptSource (This, Source);
+ return This->DisableInterruptSource (This, Source);
} else {
- return This->EnableInterruptSource (This, Source);
+ return This->EnableInterruptSource (This, Source);
}
}
@@ -113,19 +113,19 @@ EnableInterruptSource ( {
UINT32 RegOffset;
UINTN RegShift;
-
+
if (Source > mGicNumInterrupts) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
-
+
// calculate enable register offset and bit position
RegOffset = Source / 32;
RegShift = Source % 32;
// write set-enable register
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);
-
+
return EFI_SUCCESS;
}
@@ -148,19 +148,19 @@ DisableInterruptSource ( {
UINT32 RegOffset;
UINTN RegShift;
-
+
if (Source > mGicNumInterrupts) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
-
+
// Calculate enable register offset and bit position
RegOffset = Source / 32;
RegShift = Source % 32;
// Write set-enable register
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);
-
+
return EFI_SUCCESS;
}
@@ -185,27 +185,27 @@ GetInterruptSourceState ( {
UINT32 RegOffset;
UINTN RegShift;
-
+
if (Source > mGicNumInterrupts) {
ASSERT(FALSE);
return EFI_UNSUPPORTED;
}
-
+
// calculate enable register offset and bit position
RegOffset = Source / 32;
RegShift = Source % 32;
-
+
if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
*InterruptState = FALSE;
} else {
*InterruptState = TRUE;
}
-
+
return EFI_SUCCESS;
}
/**
- Signal to the hardware that the End Of Intrrupt state
+ Signal to the hardware that the End Of Intrrupt state
has been reached.
@param This Instance pointer for this protocol
@@ -259,7 +259,7 @@ IrqInterruptHandler ( // The special interrupt do not need to be acknowledge
return;
}
-
+
InterruptHandler = gRegisteredInterruptHandlers[GicInterrupt];
if (InterruptHandler != NULL) {
// Call the registered interrupt handler.
@@ -289,7 +289,7 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = { /**
Shutdown our hardware
-
+
DXE Core will disable interrupts and turn off the timer and disable interrupts
after all the event handlers have run.
@@ -304,7 +304,7 @@ ExitBootServicesEvent ( )
{
UINTN Index;
-
+
// Acknowledge all pending interrupts
for (Index = 0; Index < mGicNumInterrupts; Index++) {
DisableInterruptSource (&gHardwareInterruptProtocol, Index);
@@ -345,7 +345,7 @@ InterruptDxeInitialize ( UINTN RegShift;
EFI_CPU_ARCH_PROTOCOL *Cpu;
UINT32 CpuTarget;
-
+
// Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0
DEBUG_CODE_BEGIN();
if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {
@@ -360,13 +360,13 @@ InterruptDxeInitialize ( for (Index = 0; Index < mGicNumInterrupts; Index++) {
DisableInterruptSource (&gHardwareInterruptProtocol, Index);
-
- // Set Priority
+
+ // Set Priority
RegOffset = Index / 4;
RegShift = (Index % 4) * 8;
MmioAndThenOr32 (
PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),
- ~(0xff << RegShift),
+ ~(0xff << RegShift),
ARM_GIC_DEFAULT_PRIORITY << RegShift
);
}
@@ -382,23 +382,23 @@ InterruptDxeInitialize ( // Set priority mask reg to 0xff to allow all priorities through
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);
-
+
// Enable gic cpu interface
MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);
// Enable gic distributor
MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);
-
+
// Initialize the array for the Interrupt Handlers
gRegisteredInterruptHandlers = (HARDWARE_INTERRUPT_HANDLER*)AllocateZeroPool (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
-
+
Status = gBS->InstallMultipleProtocolInterfaces (
&gHardwareInterruptHandle,
&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,
NULL
);
ASSERT_EFI_ERROR (Status);
-
+
//
// Get the CPU protocol that this driver requires.
//
diff --git a/HisiPkg/Drivers/PL390Gic/PL390GicDxe.inf b/HisiPkg/Drivers/PL390Gic/PL390GicDxe.inf index 1f2d3990e..84650e80e 100644 --- a/HisiPkg/Drivers/PL390Gic/PL390GicDxe.inf +++ b/HisiPkg/Drivers/PL390Gic/PL390GicDxe.inf @@ -1,5 +1,5 @@ #/** @file
-#
+#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2012, ARM Ltd. All rights reserved.<BR>
# Copyright Huawei Technologies Co., Ltd. 1998-2013. All rights reserved.
@@ -8,16 +8,16 @@ # are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
-#
+#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
+#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = PL390GicDxe
- FILE_GUID = DE371F7C-DEC4-4D21-ADF1-593ABCC15882
+ FILE_GUID = DE371F7C-DEC4-4D21-ADF1-593ABCC15882
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
@@ -47,11 +47,11 @@ [Protocols]
gHardwareInterruptProtocolGuid
gEfiCpuArchProtocolGuid
-
+
[FixedPcd.common]
gArmTokenSpaceGuid.PcdGicDistributorBase
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
-
+
gArmTokenSpaceGuid.PcdArmPrimaryCore
gHwTokenSpaceGuid.PcdGicPrimaryCoreId
diff --git a/HisiPkg/Drivers/TimerDxe/TimerDxe.c b/HisiPkg/Drivers/TimerDxe/TimerDxe.c index a95a6d006..5854a3656 100644 --- a/HisiPkg/Drivers/TimerDxe/TimerDxe.c +++ b/HisiPkg/Drivers/TimerDxe/TimerDxe.c @@ -3,14 +3,14 @@ Copyright (c) 2011 ARM Ltd. All rights reserved.<BR>
Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
@@ -45,163 +45,163 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL; #define SRE_HITIMER32_OFFSET (0x00000020)
/****************** Timer32 register addresses offset start ***********************/
-#define SRE_HITIMER32_LOAD_OFFSET (0x0)
-#define SRE_HITIMER32_VALUE_OFFSET (0x4)
-#define SRE_HITIMER32_CNTL_OFFSET (0x8)
-#define SRE_HITIMER32_INTC_OFFSET (0xC)
-#define SRE_HITIMER32_RIS_OFFSET (0x10)
-#define SRE_HITIMER32_MIS_OFFSET (0x0014)
-#define SRE_HITIMER32_BGLOAD_OFFSET (0x18)
+#define SRE_HITIMER32_LOAD_OFFSET (0x0)
+#define SRE_HITIMER32_VALUE_OFFSET (0x4)
+#define SRE_HITIMER32_CNTL_OFFSET (0x8)
+#define SRE_HITIMER32_INTC_OFFSET (0xC)
+#define SRE_HITIMER32_RIS_OFFSET (0x10)
+#define SRE_HITIMER32_MIS_OFFSET (0x0014)
+#define SRE_HITIMER32_BGLOAD_OFFSET (0x18)
/****************** end ******************************/
-#define SRE_HITIMER_NUM 48
-#define SRE_HITIMER64_START_INDEX 32
+#define SRE_HITIMER_NUM 48
+#define SRE_HITIMER64_START_INDEX 32
#define SRE_HITIMER_ENCLK_SEL_BIT (1 << 7) /* Timer enable flag */
-#define SRE_HITIMER_CLK_IN_FREQ 187500000
+#define SRE_HITIMER_CLK_IN_FREQ 187500000
#define SRE_HITIMER_MICROSECOND_PER_SECOND 1000000
-#define SRE_HITIMER_DEFAULT_TICKS 100
-#define SRE_HITIMER_RELOAD_TICKS 1
+#define SRE_HITIMER_DEFAULT_TICKS 100
+#define SRE_HITIMER_RELOAD_TICKS 1
+
+#define SRE_HITIMER_INT_CLEAR (0x01)
+#define SRE_HITIMER_CNTL_ENABLE (0x80)
+#define SRE_HITIMER_CNTL_MODE (0x40)
+#define SRE_HITIMER_CNTL_IRQ_ENABLE (0x20)
+#define SRE_HITIMER_CNTL_SIZEMODE (0x2)
-#define SRE_HITIMER_INT_CLEAR (0x01)
-#define SRE_HITIMER_CNTL_ENABLE (0x80)
-#define SRE_HITIMER_CNTL_MODE (0x40)
-#define SRE_HITIMER_CNTL_IRQ_ENABLE (0x20)
-#define SRE_HITIMER_CNTL_SIZEMODE (0x2)
-
-#define SRE_HITIMER_CNTL_MODE_ONCE 0
-#define SRE_HITIMER_CNTL_MODE_CYCLE 1
-#define SRE_HITIMER_CNTL_IRQ_ON 1
-#define SRE_HITIMER_CNTL_IRQ_OFF 0
+#define SRE_HITIMER_CNTL_MODE_ONCE 0
+#define SRE_HITIMER_CNTL_MODE_CYCLE 1
+#define SRE_HITIMER_CNTL_IRQ_ON 1
+#define SRE_HITIMER_CNTL_IRQ_OFF 0
-#define SRE_D01_HITIMER01_INTVEC (256)
-#define SRE_D01_HITIMER23_INTVEC (257)
-#define SRE_D01_HITIMER45_INTVEC (258)
-#define SRE_D01_HITIMER67_INTVEC (259)
-#define SRE_D01_HITIMER89_INTVEC (260)
+#define SRE_D01_HITIMER01_INTVEC (256)
+#define SRE_D01_HITIMER23_INTVEC (257)
+#define SRE_D01_HITIMER45_INTVEC (258)
+#define SRE_D01_HITIMER67_INTVEC (259)
+#define SRE_D01_HITIMER89_INTVEC (260)
#define SRE_D01_HITIMER1011_INTVEC (261)
-#define SRE_D01_HITIMER1213_INTVEC (262)
-#define SRE_D01_HITIMER1415_INTVEC (263)
-#define SRE_D01_HITIMER1617_INTVEC (264)
-#define SRE_D01_HITIMER1819_INTVEC (265)
-#define SRE_D01_HITIMER2021_INTVEC (266)
-#define SRE_D01_HITIMER2223_INTVEC (267)
-#define SRE_D01_HITIMER2425_INTVEC (268)
-#define SRE_D01_HITIMER2627_INTVEC (269)
-#define SRE_D01_HITIMER2829_INTVEC (270)
-#define SRE_D01_HITIMER3031_INTVEC (271)
-#define SRE_D01_HITIMER3233_INTVEC (272)
-#define SRE_D01_HITIMER3435_INTVEC (273)
-#define SRE_D01_HITIMER3637_INTVEC (274)
-#define SRE_D01_HITIMER3839_INTVEC (275)
-#define SRE_D01_HITIMER4041_INTVEC (276)
-#define SRE_D01_HITIMER4243_INTVEC (277)
-#define SRE_D01_HITIMER4445_INTVEC (278)
-#define SRE_D01_HITIMER4647_INTVEC (279)
+#define SRE_D01_HITIMER1213_INTVEC (262)
+#define SRE_D01_HITIMER1415_INTVEC (263)
+#define SRE_D01_HITIMER1617_INTVEC (264)
+#define SRE_D01_HITIMER1819_INTVEC (265)
+#define SRE_D01_HITIMER2021_INTVEC (266)
+#define SRE_D01_HITIMER2223_INTVEC (267)
+#define SRE_D01_HITIMER2425_INTVEC (268)
+#define SRE_D01_HITIMER2627_INTVEC (269)
+#define SRE_D01_HITIMER2829_INTVEC (270)
+#define SRE_D01_HITIMER3031_INTVEC (271)
+#define SRE_D01_HITIMER3233_INTVEC (272)
+#define SRE_D01_HITIMER3435_INTVEC (273)
+#define SRE_D01_HITIMER3637_INTVEC (274)
+#define SRE_D01_HITIMER3839_INTVEC (275)
+#define SRE_D01_HITIMER4041_INTVEC (276)
+#define SRE_D01_HITIMER4243_INTVEC (277)
+#define SRE_D01_HITIMER4445_INTVEC (278)
+#define SRE_D01_HITIMER4647_INTVEC (279)
UINT32 gRegBase = SRE_HITIMER_ADDR;
#define SC_CTRL 0xe3e00000
void HITIMER_Start()
{
- UINT32 ulRegAddr;
- UINT32 ulVal = 0;
- UINT32 ulMask;
-
+ UINT32 ulRegAddr;
+ UINT32 ulVal = 0;
+ UINT32 ulMask;
+
ulVal = *(UINT32*)SC_CTRL;
ulVal |= BIT17 | BIT16 | BIT18 | BIT19;
*(UINT32*)SC_CTRL = ulVal;
- /*timer mode*/
- ulMask = SRE_HITIMER_CNTL_MODE; //BIT6
- ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
- ulVal = *(UINT32*)ulRegAddr;
- ulVal = ulVal;
- ulVal |= ulMask; /*cycle*/
+ /*timer mode*/
+ ulMask = SRE_HITIMER_CNTL_MODE; //BIT6
+ ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
+ ulVal = *(UINT32*)ulRegAddr;
+ ulVal = ulVal;
+ ulVal |= ulMask; /*cycle*/
*(UINT32*)ulRegAddr = ulVal;
- /*int mode*/
- ulMask = SRE_HITIMER_CNTL_IRQ_ENABLE; //BIT5
- ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
- ulVal = *(UINT32*)ulRegAddr;
- ulVal = ulVal;
- ulVal |= ulMask;
+ /*int mode*/
+ ulMask = SRE_HITIMER_CNTL_IRQ_ENABLE; //BIT5
+ ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
+ ulVal = *(UINT32*)ulRegAddr;
+ ulVal = ulVal;
+ ulVal |= ulMask;
//DEBUG((EFI_D_ERROR, "int mode = %0x at %0x\n", ulVal, ulRegAddr));
- *(UINT32*)ulRegAddr = ulVal;
-
- /*start up*/
- ulMask = (SRE_HITIMER_ENCLK_SEL_BIT | SRE_HITIMER_CNTL_SIZEMODE); //BIT7 | BIT1
- ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
- ulVal = *(UINT32*)ulRegAddr;
- ulVal = ulVal;
- ulVal |= ulMask;
+ *(UINT32*)ulRegAddr = ulVal;
+
+ /*start up*/
+ ulMask = (SRE_HITIMER_ENCLK_SEL_BIT | SRE_HITIMER_CNTL_SIZEMODE); //BIT7 | BIT1
+ ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
+ ulVal = *(UINT32*)ulRegAddr;
+ ulVal = ulVal;
+ ulVal |= ulMask;
//DEBUG((EFI_D_ERROR, "start up = %0x at %0x\n", ulVal, ulRegAddr));
- *(UINT32*)ulRegAddr = ulVal;
+ *(UINT32*)ulRegAddr = ulVal;
}
void HITMER_ClearInt()
{
- UINT32 ulRegAddr;
- UINT32 ulVal = 0;
+ UINT32 ulRegAddr;
+ UINT32 ulVal = 0;
- ulRegAddr = gRegBase + SRE_HITIMER32_INTC_OFFSET;
- ulVal = SRE_HITIMER_INT_CLEAR;
+ ulRegAddr = gRegBase + SRE_HITIMER32_INTC_OFFSET;
+ ulVal = SRE_HITIMER_INT_CLEAR;
//DEBUG((EFI_D_ERROR, "HITMER_ClearInt = %0x at %0x\n", ulVal, ulRegAddr));
- *(UINT32*)ulRegAddr = ulVal;
+ *(UINT32*)ulRegAddr = ulVal;
}
void DisableTimer()
{
- UINT32 ulRegAddr;
- UINT32 ulVal = 0;
- UINT32 ulMask;
-
- /*disable*/
- ulMask = SRE_HITIMER_ENCLK_SEL_BIT;
- ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
- ulVal = *(UINT32*)ulRegAddr;
- ulVal = ulVal;
- ulVal &= (~ulMask);
+ UINT32 ulRegAddr;
+ UINT32 ulVal = 0;
+ UINT32 ulMask;
+
+ /*disable*/
+ ulMask = SRE_HITIMER_ENCLK_SEL_BIT;
+ ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
+ ulVal = *(UINT32*)ulRegAddr;
+ ulVal = ulVal;
+ ulVal &= (~ulMask);
//DEBUG((EFI_D_ERROR, "DisableTimer = %0x at %0x\n", ulVal, ulRegAddr));
- *(UINT32*)ulRegAddr = ulVal;
+ *(UINT32*)ulRegAddr = ulVal;
}
void EnableTimer()
{
- UINT32 ulRegAddr;
- UINT32 ulVal = 1;
- UINT32 ulMask;
-
- /*disable*/
- ulMask = SRE_HITIMER_ENCLK_SEL_BIT;
- ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
- ulVal = *(UINT32*)ulRegAddr;
- ulVal = ulVal;
- ulVal |= ulMask;
+ UINT32 ulRegAddr;
+ UINT32 ulVal = 1;
+ UINT32 ulMask;
+
+ /*disable*/
+ ulMask = SRE_HITIMER_ENCLK_SEL_BIT;
+ ulRegAddr = gRegBase + SRE_HITIMER32_CNTL_OFFSET;
+ ulVal = *(UINT32*)ulRegAddr;
+ ulVal = ulVal;
+ ulVal |= ulMask;
//DEBUG((EFI_D_ERROR, "EnableTimer = %0x at %0x\n", ulVal, ulRegAddr));
- *(UINT32*)ulRegAddr = ulVal;
+ *(UINT32*)ulRegAddr = ulVal;
}
/**
- This function registers the handler NotifyFunction so it is called every time
- the timer interrupt fires. It also passes the amount of time since the last
- handler call to the NotifyFunction. If NotifyFunction is NULL, then the
- handler is unregistered. If the handler is registered, then EFI_SUCCESS is
- returned. If the CPU does not support registering a timer interrupt handler,
- then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
- when a handler is already registered, then EFI_ALREADY_STARTED is returned.
- If an attempt is made to unregister a handler when a handler is not registered,
- then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
- register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+ This function registers the handler NotifyFunction so it is called every time
+ the timer interrupt fires. It also passes the amount of time since the last
+ handler call to the NotifyFunction. If NotifyFunction is NULL, then the
+ handler is unregistered. If the handler is registered, then EFI_SUCCESS is
+ returned. If the CPU does not support registering a timer interrupt handler,
+ then EFI_UNSUPPORTED is returned. If an attempt is made to register a handler
+ when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+ If an attempt is made to unregister a handler when a handler is not registered,
+ then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to
+ register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
is returned.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@@ -254,17 +254,17 @@ ExitBootServicesEvent ( /**
- This function adjusts the period of timer interrupts to the value specified
- by TimerPeriod. If the timer period is updated, then the selected timer
- period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
- the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
- If an error occurs while attempting to update the timer period, then the
- timer hardware will be put back in its state prior to this call, and
- EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
- is disabled. This is not the same as disabling the CPU's interrupts.
- Instead, it must either turn off the timer hardware, or it must adjust the
- interrupt controller so that a CPU interrupt is not generated when the timer
- interrupt fires.
+ This function adjusts the period of timer interrupts to the value specified
+ by TimerPeriod. If the timer period is updated, then the selected timer
+ period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. If
+ the timer hardware is not programmable, then EFI_UNSUPPORTED is returned.
+ If an error occurs while attempting to update the timer period, then the
+ timer hardware will be put back in its state prior to this call, and
+ EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer interrupt
+ is disabled. This is not the same as disabling the CPU's interrupts.
+ Instead, it must either turn off the timer hardware, or it must adjust the
+ interrupt controller so that a CPU interrupt is not generated when the timer
+ interrupt fires.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@param TimerPeriod The rate to program the timer interrupt in 100 nS units. If
@@ -288,9 +288,9 @@ TimerDriverSetTimerPeriod ( )
{
UINT64 TimerTicks;
-
+
UINT32 ulRegAddr;
-
+
// always disable the timer
DisableTimer ();
@@ -301,12 +301,12 @@ TimerDriverSetTimerPeriod ( TimerTicks = MultU64x32 (TimerTicks, (PcdGet32(PcdArmArchTimerFreqInHz)/1000000));
#endif
-
+
TimerTicks = DivU64x32 (TimerPeriod, 100);
TimerTicks = MultU64x32 (TimerTicks, (PcdGet32(PcdArmArchTimerFreqInHz)/100000));
-
+
//ArmArchTimerSetTimerVal((UINTN)TimerTicks);
-
+
ulRegAddr = gRegBase + SRE_HITIMER32_LOAD_OFFSET;
//DEBUG((EFI_D_ERROR, "TimerTicks1 = %0x at %0x ======\n", TimerTicks, ulRegAddr));
*(UINT32*)ulRegAddr = TimerTicks;
@@ -324,9 +324,9 @@ TimerDriverSetTimerPeriod ( }
/**
- This function retrieves the period of timer interrupts in 100 ns units,
- returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
- is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
+ This function retrieves the period of timer interrupts in 100 ns units,
+ returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPeriod
+ is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 is
returned, then the timer is currently disabled.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@@ -354,12 +354,12 @@ TimerDriverGetTimerPeriod ( }
/**
- This function generates a soft timer interrupt. If the platform does not support soft
- timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
- If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
- service, then a soft timer interrupt will be generated. If the timer interrupt is
- enabled when this service is called, then the registered handler will be invoked. The
- registered handler should not be able to distinguish a hardware-generated timer
+ This function generates a soft timer interrupt. If the platform does not support soft
+ timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCESS is returned.
+ If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.RegisterHandler()
+ service, then a soft timer interrupt will be generated. If the timer interrupt is
+ enabled when this service is called, then the registered handler will be invoked. The
+ registered handler should not be able to distinguish a hardware-generated timer
interrupt from a software-generated timer interrupt.
@param This The EFI_TIMER_ARCH_PROTOCOL instance.
@@ -456,7 +456,7 @@ TimerInterruptHandler ( // Signal end of interrupt early to help avoid losing subsequent ticks from long duration handlers
gInterrupt->EndOfInterrupt (gInterrupt, Source);
-
+
if (mTimerNotifyFunction) {
mTimerNotifyFunction (mTimerPeriod);
@@ -466,7 +466,7 @@ TimerInterruptHandler ( //TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod));
//}
//DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
-
+
//DEBUG((EFI_D_ERROR, "[DJ]: %a : %d\n", __FUNCTION__, __LINE__));
// Enable timer interrupts
@@ -502,7 +502,7 @@ TimerInitialize ( EFI_HANDLE Handle = NULL;
EFI_STATUS Status;
-
+
// Find the interrupt controller protocol. ASSERT if not found.
Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
ASSERT_EFI_ERROR (Status);
diff --git a/HisiPkg/Drivers/TimerDxe/TimerDxe.inf b/HisiPkg/Drivers/TimerDxe/TimerDxe.inf index 6dd90ecd2..9661cd113 100644 --- a/HisiPkg/Drivers/TimerDxe/TimerDxe.inf +++ b/HisiPkg/Drivers/TimerDxe/TimerDxe.inf @@ -1,23 +1,23 @@ #/** @file
-#
+#
# Component description file for Timer DXE module
-#
+#
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
# Copyright (c) Huawei Technologies Co., Ltd. 2013. All rights reserved.
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
-#
+#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
+#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = ArmTimerDxe
- FILE_GUID = 49ea041e-6752-42ca-b0b1-7344fe2546b7
+ FILE_GUID = 49ea041e-6752-42ca-b0b1-7344fe2546b7
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
@@ -41,19 +41,19 @@ BaseMemoryLib
DebugLib
UefiDriverEntryPoint
- IoLib
+ IoLib
[Guids]
[Protocols]
- gEfiTimerArchProtocolGuid
+ gEfiTimerArchProtocolGuid
gHardwareInterruptProtocolGuid
[Pcd.common]
gEmbeddedTokenSpaceGuid.PcdTimerPeriod
- gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
[Depex]
gHardwareInterruptProtocolGuid
diff --git a/HisiPkg/HisiPlatformPkg.dec b/HisiPkg/HisiPlatformPkg.dec index de22eafdb..669a1eb0b 100644 --- a/HisiPkg/HisiPlatformPkg.dec +++ b/HisiPkg/HisiPlatformPkg.dec @@ -52,7 +52,7 @@ gHwTokenSpaceGuid.PcdtinitrdStart|0x03800000|UINT32|0x01000007
gHwTokenSpaceGuid.PcdBootcmdAddr|0x00a01000|UINT32|0x010000c
- gHwTokenSpaceGuid.PcdDefaultCmdlineTagCmdline|"mem=256M console=ttyAMA0,9600 quiet"|VOID*|0x010000F
+ gHwTokenSpaceGuid.PcdDefaultCmdlineTagCmdline|"mem=256M console=ttyAMA0,115200 quiet"|VOID*|0x010000F
gHwTokenSpaceGuid.PcdNANDCRegBase|0xe4020000|UINT32|0x0030000b
diff --git a/HisiPkg/Include/Library/BspUartLib.h b/HisiPkg/Include/Library/BspUartLib.h index 9e64130c7..3faca886d 100644 --- a/HisiPkg/Include/Library/BspUartLib.h +++ b/HisiPkg/Include/Library/BspUartLib.h @@ -85,14 +85,8 @@ #define NULL 0
#endif
-extern void BspUartInit(void);
extern void BspSendChar(char scShowChar);
extern char BspGetChar(U32 ulTimeout);
-extern void BspSendString(char* pShow);
-extern void BspSendUintHex(U32 ulData);
-extern void BspSendUshortHex(U16 usData);
-extern U32 BspUartClkFreq(void);
-extern void BspUartAgingStatDet(void);
#ifdef __cplusplus
}
diff --git a/HisiPkg/Include/Library/config.h b/HisiPkg/Include/Library/config.h index 7f53d02f7..3911e236c 100644 --- a/HisiPkg/Include/Library/config.h +++ b/HisiPkg/Include/Library/config.h @@ -88,17 +88,17 @@ extern "C" { /* Memory configuration */
#undef LOCAL_MEM_AUTOSIZE /* run-time memory sizing */
-#ifndef _BSP_BUILD_VXWORKS
+#ifndef _BSP_BUILD_VXWORKS
#ifdef _CONTROL_SLAVE_CORE_IMG
#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_SLAVE_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
#else
-#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_MASTER_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
+#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_MASTER_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
#endif
-#else
+#else
#ifdef _CONTROL_SLAVE_CORE_IMG
#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_SLAVE_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
#else
-#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_MASTER_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
+#define USER_RESERVED_MEM HDF_GetMemPoolResSizeConfig(HDF_MASTER_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
#endif
#endif
@@ -106,13 +106,13 @@ extern "C" { -#ifndef _BSP_BUILD_VXWORKS
+#ifndef _BSP_BUILD_VXWORKS
#ifdef _CONTROL_SLAVE_CORE_IMG
#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_SLAVE_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
#else
#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_MASTER_CORE_FLAG,HDF_BOOTROM_COMPILE_FLAG)
#endif
-#else
+#else
#ifdef _CONTROL_SLAVE_CORE_IMG
#define LOCAL_MEM_SIZE HDF_GetMemPoolPhyMemTopConfig(HDF_SLAVE_CORE_FLAG,HDF_VXWORKS_COMPILE_FLAG)
#else
@@ -160,8 +160,8 @@ extern "C" { #else
#ifndef _BSP_BUILD_VXWORKS
-#define ROM_BASE_ADRS (HDFINF_GetTextBase())
-#define ROM_TEXT_ADRS (HDFINF_GetTextBase())
+#define ROM_BASE_ADRS (HDFINF_GetTextBase())
+#define ROM_TEXT_ADRS (HDFINF_GetTextBase())
#define RAM_LOW_ADRS 0x05000000 /* VxWorks image entry point */
#define RAM_HIGH_ADRS 0x06000000 /* RAM address for ROM boot */
#else
@@ -189,7 +189,7 @@ extern "C" { /* Serial port configuration */
-#define N_SIO_CHANNELS 3
+#define N_SIO_CHANNELS 3
#undef NUM_TTY
#define NUM_TTY N_SIO_CHANNELS
@@ -306,7 +306,7 @@ extern "C" { #endif /* INCLUDE_END */
#ifdef _BSP_BUILD_VXWORKS
-#ifndef _CONTROL_SLAVE_CORE_IMG
+#ifndef _CONTROL_SLAVE_CORE_IMG
#if 1
#define INCLUDE_USB
#define INCLUDE_USB_INIT
@@ -328,7 +328,7 @@ extern "C" { #define INCLUDE_USB_MS_CBI_INIT
#define INCLUDE_NOR_FILESYS
#endif
-#endif
+#endif
#endif
#define INCLUDE_BSP_WATCHDOG
@@ -412,10 +412,10 @@ extern "C" { #define INCLUDE_SHELL_INTERP_CMD /* shell command interpreter */
#undef SHELL_COMPATIBLE
-#define SHELL_COMPATIBLE TRUE
+#define SHELL_COMPATIBLE TRUE
#ifndef BSP_BUILD_BASIC_BTRM
-#define INCLUDE_RAWFS
+#define INCLUDE_RAWFS
#define INCLUDE_XBD_RAMDRV
#endif
#ifndef _CONTROL_SLAVE_CORE_IMG
@@ -434,5 +434,3 @@ extern "C" { }
#endif
#endif /* __INCconfigh */
-
-
diff --git a/HisiPkg/Library/BspUartLib/BspUartLib.c b/HisiPkg/Library/BspUartLib/BspUartLib.c index 9ffbee272..7c313d300 100644 --- a/HisiPkg/Library/BspUartLib/BspUartLib.c +++ b/HisiPkg/Library/BspUartLib/BspUartLib.c @@ -20,19 +20,6 @@ #include <Library/ResetWdtLib.h>
#include <Library/DebugLib.h>
-extern U32 get_current_mmu_status( void );
-//extern void WDT_ResetWatchdog(void);
-//extern void romInit();
-extern void TMB_Read(U32* pulValueHigh, U32* pulValueLow);
-//extern U32 GET_ClkFreq(U32* psysClkReg);
-//extern U32 GET_InterTimerRefPreq(void);
-extern void sysUsDelay(U32 delay);
-
-U32 BspUartClkFreq(void);
-void BspSendString(char* pShow);
-void BspSendUintHex(U32 ulData);
-
-#define FEED_WDT WDT_ResetWatchdog()
#define BSP_UartDelay(loop) delayuart(2 * loop)
void delayuart(unsigned long ulCount)
diff --git a/HisiPkg/Library/SerialPortLib/SerialPortLib.c b/HisiPkg/Library/SerialPortLib/SerialPortLib.c index e41aac79f..93cf04ad0 100644 --- a/HisiPkg/Library/SerialPortLib/SerialPortLib.c +++ b/HisiPkg/Library/SerialPortLib/SerialPortLib.c @@ -20,17 +20,29 @@ #include <Uefi/UefiBaseType.h>
#include <Protocol/SerialIo.h>
-static int flag=1;
-
-UINT32 UART_UartClkFreq(void)
+VOID SerialInit(VOID)
{
- #define UART_CLK_FREQ_ADRS 0x20000020
- UINT32 ulRegVal = 0x00;
- UINT32 ulCpllFreq = 0x00;
- ulRegVal = ((*(UINT32 *)UART_CLK_FREQ_ADRS));
- ulCpllFreq = ((((25000000 /(ulRegVal&0x3f))) /((ulRegVal>>18)&0x07))
- /((ulRegVal>>21)&0x07))* ((ulRegVal>>6)&0xfff);
- return ulCpllFreq;
+ UINT32 ulUartClkFreq;
+
+ *(volatile UINT32 *)(UART_LCR_REG) = UART_LCR_DLS8;
+
+ *(volatile UINT32 *)(UART_FCR_REG) = UART_FCR_EN | UART_FCR_RXCLR | UART_FCR_TXCLR;
+
+ *(volatile UINT32 *)(UART_LCR_REG) = UART_LCR_DLAB | UART_LCR_DLS8;
+
+ ulUartClkFreq = TCXO_CLK_FREQ;
+
+ *(volatile UINT32 *)(UART_DLL_REG) = (ulUartClkFreq / (16 * BAUDRATE) ) & 0xff;
+ *(volatile UINT32 *)(UART_DLH_REG) = ((ulUartClkFreq/ (16 * BAUDRATE) ) >> 8 ) & 0xff;
+
+ *(volatile UINT32 *)(UART_LCR_REG) = UART_LCR_DLS8;
+
+ *(volatile UINT32 *)(UART_IEL_REG) = 0x00;
+
+ *(volatile UINT32 *)(UART_THR_REG) = 0x53;
+
+ return ;
+
}
@@ -51,22 +63,6 @@ SerialPortInitialize ( VOID
)
{
- UINT32 ulUartClkFreq;
-
-if(flag>0) return RETURN_SUCCESS;
- *(volatile UINT8 *)(UART_LCR_REG) = UART_LCR_DLS8;
- *(volatile UINT8 *)(UART_FCR_REG) = UART_FCR_EN | UART_FCR_RXCLR | UART_FCR_TXCLR;
- *(volatile UINT8 *)(UART_LCR_REG) = UART_LCR_DLAB | UART_LCR_DLS8;
- ulUartClkFreq = 168750000;
- //ulUartClkFreq = 50000000;
- *(volatile UINT8 *)(UART_DLL_REG) = (ulUartClkFreq / (16 * BAUDRATE) ) & 0xff;
- *(volatile UINT8 *)(UART_DLH_REG) = ((ulUartClkFreq/ (16 * BAUDRATE) ) >> 8 ) & 0xff;
- //*(volatile UINT8 *)(UART_DLL_REG) = (ulUartClkFreq / (16 * 2400) ) & 0xff;
- //*(volatile UINT8 *)(UART_DLH_REG) = ((ulUartClkFreq/ (16 * 2400) ) >> 8 ) & 0xff;
- //*(volatile UINT8 *)(UART_DLL_REG) = 0x5B; //115200
- //*(volatile UINT8 *)(UART_DLH_REG) = 0x00; //115200
- *(volatile UINT8 *)(UART_LCR_REG) = UART_LCR_DLS8;
- *(volatile UINT8 *)(UART_IEL_REG) = 0x00;
return RETURN_SUCCESS;
}
@@ -191,7 +187,7 @@ VOID SerialPortWriteChar(UINT8 scShowChar) while(ulLoop < UART_SEND_DELAY)
{
- if ((*(volatile UINT8 *)(UART_USR_REG) & 0x02) == 0x02)
+ if ((*(volatile UINT8 *)(UART_USR_REG) & UART_FCR_RXCLR) == UART_FCR_RXCLR)
{
break;
}
@@ -203,7 +199,7 @@ VOID SerialPortWriteChar(UINT8 scShowChar) ulLoop = 0;
while(ulLoop < UART_SEND_DELAY)
{
- if ((*(volatile UINT8 *)(UART_USR_REG) & 0x04) == 0x04)
+ if ((*(volatile UINT8 *)(UART_USR_REG) & UART_FCR_TXCLR) == UART_FCR_TXCLR)
{
break;
}
@@ -220,12 +216,11 @@ UINT8 SerialPortReadChar(VOID) do
{
- if ((*(UINT8 *)(UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR)
+ if ((*(volatile UINT8 *)(UART_LSR_REG) & UART_LSR_DR) == UART_LSR_DR)
{
break;
}
-
- }while(*(UINT8 *)(UART_USR_REG) & UART_USR_BUSY);
+ }while(1);
recvchar = (*(volatile UINT8 *)(UART_RBR_REG));
diff --git a/HisiPkg/Library/SerialPortLib/SerialPortLib.h b/HisiPkg/Library/SerialPortLib/SerialPortLib.h index cf9d5450a..b8f6f599c 100644 --- a/HisiPkg/Library/SerialPortLib/SerialPortLib.h +++ b/HisiPkg/Library/SerialPortLib/SerialPortLib.h @@ -15,13 +15,13 @@ #ifndef __HISIARM_SERIAL_PORT__
#define __HISIARM_SERIAL_PORT__
-
-#define UART_USED_CHANNELS 1
-#define TCXO_CLK_FREQ 26000000
-#define SERIAL_0_BASE_ADR 0xe4007000
-#define REG_VAL (*(UINT32 *)0x118) & 0xffff
-#define UART_SEND_DELAY 500000
-#define BAUDRATE 115200
+#include <Library/PcdLib.h>
+#define UART_USED_CHANNELS 1
+#define TCXO_CLK_FREQ 168750000
+#define SERIAL_0_BASE_ADR 0xe4007000
+#define REG_VAL (*(UINT32 *)0x118) & 0xffff
+#define UART_SEND_DELAY 500000
+#define BAUDRATE 115200
#define UART_THR_REG (SERIAL_0_BASE_ADR + UART_RBR)
diff --git a/HisiPkg/README b/HisiPkg/README index 05f5e851a..d4e8517d5 100644 --- a/HisiPkg/README +++ b/HisiPkg/README @@ -46,4 +46,4 @@ D01 >updateL1 D01.fd * Connect the Uart cable from the D01 device to the PC terminal.
* Power ON the Device.
* The boot message should be visible on the termial.
-* Finally, it should give boot options.
+* Finally, it should give boot options.
|