From ecc380b543b76b942666599d593c657d5c1542b9 Mon Sep 17 00:00:00 2001 From: Haojian Zhuang Date: Tue, 27 Aug 2013 11:14:49 +0800 Subject: ARM: dts: fix the clock setting of sp804 timer Use sp804 clock mux to include PLL setting. Drop the clock gate to enable PLL setting. Then sp804 could work right. It's caused by clk_disable() is invoked. It results in clock source and clock event working in two different frequency. Signed-off-by: Haojian Zhuang --- arch/arm/boot/dts/hi3620.dtsi | 128 +++++++++++------------------------------- arch/arm/boot/dts/hi4511.dts | 2 +- 2 files changed, 33 insertions(+), 97 deletions(-) diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index d0baa681e561..242a47c8401a 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -211,68 +211,68 @@ clock-output-names = "rclk_tcxo"; hisilicon,fixed-factor = <1 4>; }; - refclk_timer0: refclk@12 { + timer0_mux: timer0_mux { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc32k &timerclk01>; - clock-output-names = "rclk_tim0"; - hisilicon,clkmux-reg = <0 0x8000>; + clock-output-names = "timer0_mux"; + hisilicon,clkmux-reg = <0 0x18000>; hisilicon,clkmux-table = <0 0x8000>; }; - refclk_timer1: refclk@13 { + timer1_mux: timer1_mux { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc32k &timerclk01>; - clock-output-names = "rclk_tim1"; - hisilicon,clkmux-reg = <0 0x20000>; + clock-output-names = "timer1_mux"; + hisilicon,clkmux-reg = <0 0x60000>; hisilicon,clkmux-table = <0 0x20000>; }; - refclk_timer2: refclk@14 { + timer2_mux: timer2_mux { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc32k &timerclk23>; - clock-output-names = "rclk_tim2"; - hisilicon,clkmux-reg = <0 0x80000>; + clock-output-names = "timer2_mux"; + hisilicon,clkmux-reg = <0 0x180000>; hisilicon,clkmux-table = <0 0x80000>; }; - refclk_timer3: refclk@15 { + timer3_mux: timer3_mux { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc32k &timerclk23>; - clock-output-names = "rclk_tim3"; - hisilicon,clkmux-reg = <0 0x200000>; + clock-output-names = "timer3_mux"; + hisilicon,clkmux-reg = <0 0x600000>; hisilicon,clkmux-table = <0 0x200000>; }; - refclk_timer4: refclk@16 { + timer4_mux: timer4_mux { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc32k &timerclk45>; - clock-output-names = "rclk_tim4"; - hisilicon,clkmux-reg = <0x18 0x1>; + clock-output-names = "timer4_mux"; + hisilicon,clkmux-reg = <0x18 0x3>; hisilicon,clkmux-table = <0 0x1>; }; - refclk_timer5: refclk@17 { + timer5_mux: timer5_mux { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc32k &timerclk45>; - clock-output-names = "rclk_tim5"; - hisilicon,clkmux-reg = <0x18 0x4>; + clock-output-names = "timer5_mux"; + hisilicon,clkmux-reg = <0x18 0xc>; hisilicon,clkmux-table = <0 0x4>; }; - refclk_timer6: refclk@18 { + timer6_mux: timer6_mux { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc32k &timerclk67>; - clock-output-names = "rclk_tim6"; - hisilicon,clkmux-reg = <0x18 0x10>; + clock-output-names = "timer6_mux"; + hisilicon,clkmux-reg = <0x18 0x30>; hisilicon,clkmux-table = <0 0x10>; }; - refclk_timer7: refclk@19 { + timer7_mux: timer7_mux { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc32k &timerclk67>; - clock-output-names = "rclk_tim7"; - hisilicon,clkmux-reg = <0x18 0x40>; + clock-output-names = "timer7_mux"; + hisilicon,clkmux-reg = <0x18 0xc0>; hisilicon,clkmux-table = <0 0x40>; }; refclk_shareAXI: refclk@22 { @@ -707,70 +707,6 @@ hisilicon,hi3620-clkreset = <0x98 0x20>; hisilicon,hi3620-clkgate = <0x40 0x20>; }; - timclk0: clkgate@37 { - compatible = "hisilicon,clk-gate"; - #clock-cells = <0>; - clocks = <&refclk_timer0>; - clock-output-names = "timclk0"; - hisilicon,clkgate-inverted; - hisilicon,clkgate = <0 16>; - }; - timclk1: clkgate@38 { - compatible = "hisilicon,clk-gate"; - #clock-cells = <0>; - clocks = <&refclk_timer1>; - clock-output-names = "timclk1"; - hisilicon,clkgate-inverted; - hisilicon,clkgate = <0 18>; - }; - timclk2: clkgate@39 { - compatible = "hisilicon,clk-gate"; - #clock-cells = <0>; - clocks = <&refclk_timer2>; - clock-output-names = "timclk2"; - hisilicon,clkgate-inverted; - hisilicon,clkgate = <0 20>; - }; - timclk3: clkgate@40 { - compatible = "hisilicon,clk-gate"; - #clock-cells = <0>; - clocks = <&refclk_timer3>; - clock-output-names = "timclk3"; - hisilicon,clkgate-inverted; - hisilicon,clkgate = <0 22>; - }; - timclk4: clkgate@41 { - compatible = "hisilicon,clk-gate"; - #clock-cells = <0>; - clocks = <&refclk_timer4>; - clock-output-names = "timclk4"; - hisilicon,clkgate-inverted; - hisilicon,clkgate = <0x18 0>; - }; - timclk5: clkgate@42 { - compatible = "hisilicon,clk-gate"; - #clock-cells = <0>; - clocks = <&refclk_timer5>; - clock-output-names = "timclk5"; - hisilicon,clkgate-inverted; - hisilicon,clkgate = <0x18 2>; - }; - timclk6: clkgate@43 { - compatible = "hisilicon,clk-gate"; - #clock-cells = <0>; - clocks = <&refclk_timer6>; - clock-output-names = "timclk6"; - hisilicon,clkgate-inverted; - hisilicon,clkgate = <0x18 4>; - }; - timclk7: clkgate@44 { - compatible = "hisilicon,clk-gate"; - #clock-cells = <0>; - clocks = <&refclk_timer7>; - clock-output-names = "timclk7"; - hisilicon,clkgate-inverted; - hisilicon,clkgate = <0x18 6>; - }; rtcclk: clkgate@47 { compatible = "hisilicon,hi3620-clk-gate"; #clock-cells = <0>; @@ -1015,17 +951,17 @@ reg = <0xfc001000 0x1000>, <0xfc000100 0x100>; }; - timer0: timer@fc800000 { + dual_timer0: dual_timer@fc800000 { compatible = "arm,sp804", "arm,primecell"; reg = <0xfc800000 0x1000>; /* timer00 & timer01 */ interrupts = <0 0 4>, <0 1 4>; - clocks = <&timclk0 &timclk1>; + clocks = <&timer0_mux &timer1_mux>; clock-names = "apb_pclk"; status = "disabled"; }; - timer1: timer@fc801000 { + dual_timer1: dual_timer@fc801000 { /* * Only used in NORMAL state, not available ins * SLOW or DOZE state. @@ -1035,27 +971,27 @@ reg = <0xfc801000 0x1000>; /* timer10 & timer11 */ interrupts = <0 2 4>, <0 3 4>; - clocks = <&timclk2 &timclk3>; + clocks = <&timer2_mux &timer3_mux>; clock-names = "apb_pclk"; status = "disabled"; }; - timer2: timer@fca01000 { + dual_timer2: dual_timer@fca01000 { compatible = "arm,sp804", "arm,primecell"; reg = <0xfca01000 0x1000>; /* timer20 & timer21 */ interrupts = <0 4 4>, <0 5 4>; - clocks = <&timclk4 &timclk5>; + clocks = <&timer4_mux &timer5_mux>; clock-names = "apb_pclk"; status = "disabled"; }; - timer3: timer@fca02000 { + dual_timer3: dual_timer@fca02000 { compatible = "arm,sp804", "arm,primecell"; reg = <0xfca02000 0x1000>; /* timer30 & timer31 */ interrupts = <0 6 4>, <0 7 4>; - clocks = <&timclk6 &timclk7>; + clocks = <&timer6_mux &timer7_mux>; clock-names = "apb_pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/hi4511.dts b/arch/arm/boot/dts/hi4511.dts index b8d27401c4a9..c783a0b05bfb 100644 --- a/arch/arm/boot/dts/hi4511.dts +++ b/arch/arm/boot/dts/hi4511.dts @@ -56,7 +56,7 @@ }; amba { - timer0: timer@fc800000 { + dual_timer0: dual_timer@fc800000 { status = "ok"; }; -- cgit v1.2.3