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2013-03-19ARM: hs: power on/off cpuZhangfei Gao
Add more operation to power on/off cpu, as well as reset cpu Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
2013-03-19hs_defconfig: add MMC configZhangfei Gao
mmc driver & filesystem support Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
2013-03-19mmc: dw-mmc-hisilicon add workaroundZhangfei Gao
to be reverted Since clk driver still can not choose parent accordingly, add testsdclk and access register directly for simplicity The patch can be reverted if clk driver is enhanced Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
2013-03-19ARM: dts: add mmc resourceZhangfei Gao
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
2013-03-19ARM: dts: add clock for mmc, mcuZhangfei Gao
Signed-off-by: LiXin <li.xin@linaro.org>
2013-03-14Merge remote-tracking branch 'origin/testing/sync_pinmux' into ↵Guodong Xu
integration-linux-mainline
2013-03-13ARM: hs: refresh pin configuration in dtsHaojian Zhuang
Now node names can't be same. Otherwise, pinmux setting would be dropped. Sync properties with 3.10 at the same time. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2013-02-22ARM: hs: enable hotplug and reboothotplugZhangfei Gao
Hisilicon require system register to enable/disable cpu How to test: cat proc/interrupts echo 0 > /sys/devices/system/cpu/cpuX/online cat proc/interrupts echo 1 > /sys/devices/system/cpu/cpuX/online reboot Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Tested-by: Zhang Mingjun <zhang.mingjun@linaro.org>
2013-02-21ARM: hs: add twd timerZhangfei Gao
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
2013-02-21ARM: hs: add l2 aux prop in hi3716.dtsiMingjun Zhang
add l2 aux prop in hi3716.dtsi Signed-off-by: Mingjun Zhang <zhang.mingjun@linaro.org>
2013-02-21hs_defconfig: Enable mtd and jffs2Guodong Xu
Enable mtd and jffs2 Signed-off-by: Mingjun <zhang.mingjun@linaro.org>
2013-02-21hs_defconfig: Enable Hi6421 mfd and regulatorsGuodong Xu
Enable Hi6421 mfd and regulators. Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
2013-02-21ARM: hs: remove version prop from flash node in dtsMingjun
remove sfc version prop from flash node in hi3716-dkb.dts Signed-off-by: Mingjun <zhang.mingjun@linaro.org>
2013-02-21ARM: hs: add dma clk dependenceZhangfei Gao
DMA need two clks to work, enable acp_clk here 1. 0xfc800000 + 0x50, bit 10 2. 0xfcA09000 + 0x30, bit 28, acp_clk Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
2013-02-21hs_defconfig: Enable K3 DMA and I2CGuodong Xu
Enable K3 DMA and Designware I2C for HiSilicon Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
2013-02-21ARM: dts: add clock for i2c,rtc,dmacLiXin
Add clock dts for i2c, rtc, dmac. Signed-off-by: LiXin <li.xin@linaro.org>
2013-02-21ARM: hs: solve sysctrl conflictLiXin
Solve sysctrl redefine for hi3620. Signed-off-by: LiXin <li.xin@linaro.org>
2013-02-21ARM: hs: compatible with hi3716Zhangfei Gao
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
2013-02-21regulator: hi6421: add more properties in dtsGuodong Xu
2013-02-21regulator:hi6421, update dtsGuodong Xu
2013-02-21regulator: hi6421 driver for each regulatorGuodong Xu
2013-02-21add regulators to hi4511.dts initialGuodong Xu
2013-02-21regulator:hs:add hi6421 dts supportGuodong Xu
2013-02-21ARM: hs: add clock driver to hi4511LiXin
Add clock driver based on common clock framework to hi4511. Signed-off-by: LiXin <li.xin@linaro.org>
2013-02-21HS: add SFC nodeMingjun Zhang
also add mtdparts in choose for easier use Signed-off-by: Mingjun Zhang <troy.zhangmingjun@huawei.com>
2013-02-21ARM: hs: add dma and i2c resourceZhangfei Gao
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
2013-02-21ARM: hs: add smp resource to dtsZhangfei Gao
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
2013-02-21ARM: hs: support smpZhangfei Gao
uboot requirement: CPUn: enable gic cpu interface; 1: wfi; check regn; /* notes: CPUn check own specific regn */ if (reg == 0) goto 1; else disable gic cpu interface set pc regn Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Tested-by: Zhang Mingjun <zhang.mingjun@linaro.org> Tested-by: Li Xin <li.xin@linaro.org>
2013-02-21ARM: hs: hi3716 dts modificationZhangfei Gao
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
2013-02-21ARM: dts: append l2 aux property in hi3620Haojian Zhuang
L2 aux property is used to initialize L2 cache. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2013-02-21ARM: hs: enable l2 cacheHaojian Zhuang
Enable l2 cache on hisilicon SoC platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2013-02-21ARM: dts: fix the mapping on l2 cacheHaojian Zhuang
The register mapping on L2 cache is wrong. So it results failure on enabling L2 cache. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2013-02-21ARM: dts: append rtc into hi4511 platformHaojian Zhuang
Enable rtc device in hi4511 platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2013-02-21ARM: dts: add config file for Hisilicon SoCHaojian Zhuang
Add the default config of Hisilicon SoC. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2013-02-21ARM: hs: add hi3716 dts supportZhangfei Gao
Add the support the hi3716 platform. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2013-02-21ARM: hs: add debug ll support for HI3716 UART0Zhangfei Gao
Add debug ll support for Hi3716 UART0. Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2013-02-21ARM: hs: enable hi4511 with device treeHaojian Zhuang
Enable Hisilicon Hi4511 development platform with device tree support. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2013-02-21gpio: set gpio range cells property as 3Haojian Zhuang
Add gpio offset into "gpio-range-cells" property. It's used to support sparse pinctrl range in gpio chip. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2013-02-21ARM: config: append arch hs into multi defconfigHaojian Zhuang
Append ARCH_HS (Hisilicon SoC) into multi_v7_defconfig. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2013-02-21ARM: hs: add board support with device treeHaojian Zhuang
Add board support with device tree for Hisilicon Hi36xx/Hi37xx platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2013-02-21ARM: debug: support debug ll on hisilicon socHaojian Zhuang
Support UART0 debug ll on hisilicon Hi3620 SoC. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2013-02-09Merge tag 'highbank-fixes-for-3.8' of git://sources.calxeda.com/kernel/linux ↵Olof Johansson
into fixes From Rob Herring: highbank fixes for 3.8 -Compile fix for !SMP -More cpu cluster id related fixes * tag 'highbank-fixes-for-3.8' of git://sources.calxeda.com/kernel/linux: ARM: highbank: mask cluster id from cpu_logical_map ARM: scu: mask cluster id from cpu_logical_map ARM: scu: add empty scu_enable for !CONFIG_SMP
2013-02-09Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-armLinus Torvalds
Pull ARM fixes from Russell King: "I was going to hold these off until v3.8 was out, and send them with a stable tag, but as everyone else is pushing much bigger fixes which Linus is accepting, let's save people from the hastle of having to patch v3.8 back into working or use a stable kernel. Looking at the diffstat, this really is high value for its size; this is miniscule compared to how the -rc6 to tip diffstat currently looks. So, four patches in this set: - Punit Agrawal reports that the kernel no longer boots on MPCore due to a new assumption made in the GIC code which isn't true of earlier GIC designs. This is the biggest change in this set. - Punit's boot log also revealed a bunch of WARN_ON() dumps caused by the DT-ification of the GIC support without fixing up non-DT Realview - which now sees a greater number of interrupts than it did before. - A fix for the DMA coherent code from Marek which uses the wrong check for atomic allocations; this can result in spinlock lockups or other nasty effects. - A fix from Will, which will affect all Android based platforms if not applied (which use the 2G:2G VM split) - this causes particularly 'make' to misbehave unless this bug is fixed." * 'fixes' of git://git.linaro.org/people/rmk/linux-arm: ARM: 7641/1: memory: fix broken mmap by ensuring TASK_UNMAPPED_BASE is aligned ARM: DMA mapping: fix bad atomic test ARM: realview: ensure that we have sufficient IRQs available ARM: GIC: fix GIC cpumask initialization
2013-02-08ARM: 7641/1: memory: fix broken mmap by ensuring TASK_UNMAPPED_BASE is alignedWill Deacon
We have received multiple reports of mmap failures when running with a 2:2 vm split. These manifest as either -EINVAL with a non page-aligned address (ending 0xaaa) or a SEGV, depending on the application. The issue is commonly observed in children of make, which appears to use bottom-up mmap (assumedly because it changes the stack rlimit). Further investigation reveals that this regression was triggered by 394ef6403abc ("mm: use vm_unmapped_area() on arm architecture"), whereby TASK_UNMAPPED_BASE is no longer page-aligned for bottom-up mmap, causing get_unmapped_area to choke on misaligned addressed. This patch fixes the problem by defining TASK_UNMAPPED_BASE in terms of TASK_SIZE and explicitly aligns the result to 16M, matching the other end of the heap. Acked-by: Nicolas Pitre <nico@linaro.org> Reported-by: Steve Capper <steve.capper@arm.com> Reported-by: Jean-Francois Moine <moinejf@free.fr> Reported-by: Christoffer Dall <cdall@cs.columbia.edu> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-02-08ARM: DMA mapping: fix bad atomic testRussell King
Realview fails to boot with this warning: BUG: spinlock lockup suspected on CPU#0, init/1 lock: 0xcf8bde10, .magic: dead4ead, .owner: init/1, .owner_cpu: 0 Backtrace: [<c00185d8>] (dump_backtrace+0x0/0x10c) from [<c03294e8>] (dump_stack+0x18/0x1c) r6:cf8bde10 r5:cf83d1c0 r4:cf8bde10 r3:cf83d1c0 [<c03294d0>] (dump_stack+0x0/0x1c) from [<c018926c>] (spin_dump+0x84/0x98) [<c01891e8>] (spin_dump+0x0/0x98) from [<c0189460>] (do_raw_spin_lock+0x100/0x198) [<c0189360>] (do_raw_spin_lock+0x0/0x198) from [<c032cbac>] (_raw_spin_lock+0x3c/0x44) [<c032cb70>] (_raw_spin_lock+0x0/0x44) from [<c01c9224>] (pl011_console_write+0xe8/0x11c) [<c01c913c>] (pl011_console_write+0x0/0x11c) from [<c002aea8>] (call_console_drivers.clone.7+0xdc/0x104) [<c002adcc>] (call_console_drivers.clone.7+0x0/0x104) from [<c002b320>] (console_unlock+0x2e8/0x454) [<c002b038>] (console_unlock+0x0/0x454) from [<c002b8b4>] (vprintk_emit+0x2d8/0x594) [<c002b5dc>] (vprintk_emit+0x0/0x594) from [<c0329718>] (printk+0x3c/0x44) [<c03296dc>] (printk+0x0/0x44) from [<c002929c>] (warn_slowpath_common+0x28/0x6c) [<c0029274>] (warn_slowpath_common+0x0/0x6c) from [<c0029304>] (warn_slowpath_null+0x24/0x2c) [<c00292e0>] (warn_slowpath_null+0x0/0x2c) from [<c0070ab0>] (lockdep_trace_alloc+0xd8/0xf0) [<c00709d8>] (lockdep_trace_alloc+0x0/0xf0) from [<c00c0850>] (kmem_cache_alloc+0x24/0x11c) [<c00c082c>] (kmem_cache_alloc+0x0/0x11c) from [<c00bb044>] (__get_vm_area_node.clone.24+0x7c/0x16c) [<c00bafc8>] (__get_vm_area_node.clone.24+0x0/0x16c) from [<c00bb7b8>] (get_vm_area_caller+0x48/0x54) [<c00bb770>] (get_vm_area_caller+0x0/0x54) from [<c0020064>] (__alloc_remap_buffer.clone.15+0x38/0xb8) [<c002002c>] (__alloc_remap_buffer.clone.15+0x0/0xb8) from [<c0020244>] (__dma_alloc+0x160/0x2c8) [<c00200e4>] (__dma_alloc+0x0/0x2c8) from [<c00204d8>] (arm_dma_alloc+0x88/0xa0)[<c0020450>] (arm_dma_alloc+0x0/0xa0) from [<c00beb00>] (dma_pool_alloc+0xcc/0x1a8) [<c00bea34>] (dma_pool_alloc+0x0/0x1a8) from [<c01a9d14>] (pl08x_fill_llis_for_desc+0x28/0x568) [<c01a9cec>] (pl08x_fill_llis_for_desc+0x0/0x568) from [<c01aab8c>] (pl08x_prep_slave_sg+0x258/0x3b0) [<c01aa934>] (pl08x_prep_slave_sg+0x0/0x3b0) from [<c01c9f74>] (pl011_dma_tx_refill+0x140/0x288) [<c01c9e34>] (pl011_dma_tx_refill+0x0/0x288) from [<c01ca748>] (pl011_start_tx+0xe4/0x120) [<c01ca664>] (pl011_start_tx+0x0/0x120) from [<c01c54a4>] (__uart_start+0x48/0x4c) [<c01c545c>] (__uart_start+0x0/0x4c) from [<c01c632c>] (uart_start+0x2c/0x3c) [<c01c6300>] (uart_start+0x0/0x3c) from [<c01c795c>] (uart_write+0xcc/0xf4) [<c01c7890>] (uart_write+0x0/0xf4) from [<c01b0384>] (n_tty_write+0x1c0/0x3e4) [<c01b01c4>] (n_tty_write+0x0/0x3e4) from [<c01acfe8>] (tty_write+0x144/0x240) [<c01acea4>] (tty_write+0x0/0x240) from [<c01ad17c>] (redirected_tty_write+0x98/0xac) [<c01ad0e4>] (redirected_tty_write+0x0/0xac) from [<c00c371c>] (vfs_write+0xbc/0x150) [<c00c3660>] (vfs_write+0x0/0x150) from [<c00c39c0>] (sys_write+0x4c/0x78) [<c00c3974>] (sys_write+0x0/0x78) from [<c0014460>] (ret_fast_syscall+0x0/0x3c) This happens because the DMA allocation code is not respecting atomic allocations correctly. GFP flags should not be tested for GFP_ATOMIC to determine if an atomic allocation is being requested. GFP_ATOMIC is not a flag but a value. The GFP bitmask flags are all prefixed with __GFP_. The rest of the kernel tests for __GFP_WAIT not being set to indicate an atomic allocation. We need to do the same. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-02-08ARM: realview: ensure that we have sufficient IRQs availableRussell King
Realview EB with a rev B MPcore tile results in lots of warnings at boot because it can't allocate enough IRQs. Fix this by increasing the number of available IRQs. WARNING: at /home/rmk/git/linux-rmk/arch/arm/common/gic.c:757 gic_init_bases+0x12c/0x2ec() Cannot allocate irq_descs @ IRQ96, assuming pre-allocated Modules linked in: Backtrace: [<c00185d8>] (dump_backtrace+0x0/0x10c) from [<c03294e8>] (dump_stack+0x18/0x1c) r6:000002f5 r5:c042c62c r4:c044ff40 r3:c045f240 [<c03294d0>] (dump_stack+0x0/0x1c) from [<c00292c8>] (warn_slowpath_common+0x54/0x6c) [<c0029274>] (warn_slowpath_common+0x0/0x6c) from [<c0029384>] (warn_slowpath_fmt+0x38/0x40) [<c002934c>] (warn_slowpath_fmt+0x0/0x40) from [<c042c62c>] (gic_init_bases+0x12c/0x2ec) [<c042c500>] (gic_init_bases+0x0/0x2ec) from [<c042cdc8>] (gic_init_irq+0x8c/0xd8) [<c042cd3c>] (gic_init_irq+0x0/0xd8) from [<c042827c>] (init_IRQ+0x1c/0x24) [<c0428260>] (init_IRQ+0x0/0x24) from [<c04256c8>] (start_kernel+0x1a4/0x300) [<c0425524>] (start_kernel+0x0/0x300) from [<70008070>] (0x70008070) ---[ end trace 1b75b31a2719ed1c ]--- ------------[ cut here ]------------ WARNING: at /home/rmk/git/linux-rmk/kernel/irq/irqdomain.c:234 irq_domain_add_legacy+0x80/0x140() Modules linked in: Backtrace: [<c00185d8>] (dump_backtrace+0x0/0x10c) from [<c03294e8>] (dump_stack+0x18/0x1c) r6:000000ea r5:c0081a38 r4:00000000 r3:c045f240 [<c03294d0>] (dump_stack+0x0/0x1c) from [<c00292c8>] (warn_slowpath_common+0x54/0x6c) [<c0029274>] (warn_slowpath_common+0x0/0x6c) from [<c0029304>] (warn_slowpath_null+0x24/0x2c) [<c00292e0>] (warn_slowpath_null+0x0/0x2c) from [<c0081a38>] (irq_domain_add_legacy+0x80/0x140) [<c00819b8>] (irq_domain_add_legacy+0x0/0x140) from [<c042c64c>] (gic_init_bases+0x14c/0x2ec) [<c042c500>] (gic_init_bases+0x0/0x2ec) from [<c042cdc8>] (gic_init_irq+0x8c/0xd8) [<c042cd3c>] (gic_init_irq+0x0/0xd8) from [<c042827c>] (init_IRQ+0x1c/0x24) [<c0428260>] (init_IRQ+0x0/0x24) from [<c04256c8>] (start_kernel+0x1a4/0x300) [<c0425524>] (start_kernel+0x0/0x300) from [<70008070>] (0x70008070) ---[ end trace 1b75b31a2719ed1d ]--- ------------[ cut here ]------------ WARNING: at /home/rmk/git/linux-rmk/arch/arm/common/gic.c:762 gic_init_bases+0x170/0x2ec() Modules linked in: Backtrace: [<c00185d8>] (dump_backtrace+0x0/0x10c) from [<c03294e8>] (dump_stack+0x18/0x1c) r6:000002fa r5:c042c670 r4:00000000 r3:c045f240 [<c03294d0>] (dump_stack+0x0/0x1c) from [<c00292c8>] (warn_slowpath_common+0x54/0x6c) [<c0029274>] (warn_slowpath_common+0x0/0x6c) from [<c0029304>] (warn_slowpath_null+0x24/0x2c) [<c00292e0>] (warn_slowpath_null+0x0/0x2c) from [<c042c670>] (gic_init_bases+0x170/0x2ec) [<c042c500>] (gic_init_bases+0x0/0x2ec) from [<c042cdc8>] (gic_init_irq+0x8c/0xd8) [<c042cd3c>] (gic_init_irq+0x0/0xd8) from [<c042827c>] (init_IRQ+0x1c/0x24) [<c0428260>] (init_IRQ+0x0/0x24) from [<c04256c8>] (start_kernel+0x1a4/0x300) [<c0425524>] (start_kernel+0x0/0x300) from [<70008070>] (0x70008070) ---[ end trace 1b75b31a2719ed1e ]--- Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-02-08ARM: GIC: fix GIC cpumask initializationRussell King
Punit Agrawal reports: > I was trying to boot 3.8-rc5 on Realview EB 11MPCore using > realview-smp_defconfig as a starting point but the kernel failed to > progress past the log below (config attached). > > Pawel suggested I try reverting 384a290283f - "ARM: gic: use a private > mapping for CPU target interfaces" that you've authored. With this > commit reverted the kernel boots. > > I am not quite sure why the commit breaks 11MPCore but Pawel (cc'd) > might be able to shed light on that. Some early GIC implementations return zero for the first distributor CPU routing register. This means we can't rely on that telling us which CPU interface we're connected to. We know that these platforms implement PPIs for IRQs 29-31 - but we shouldn't assume that these will always be populated. So, instead, scan for a non-zero CPU routing register in the first 32 IRQs and use that as our CPU mask. Reported-by: Punit Agrawal <punit.agrawal@arm.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-02-05pinctrl: exynos: change PINCTRL_EXYNOS optionKukjin Kim
Since pinctrl-exynos can support exynos4 and exynos5 so changed the option name to PINCTRL_EXYNOS for more clarity. Cc: Thomas Abraham <Thomas.abraham@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-31ARM: highbank: mask cluster id from cpu_logical_mapRob Herring
With commit a0ae0240 (ARM: kernel: add device tree init map function), the cpu id value may include the cluster id and is no longer 0-3, so we need to mask it now to get the right hard cpu index. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
2013-01-31ARM: scu: mask cluster id from cpu_logical_mapRob Herring
With commit a0ae0240 (ARM: kernel: add device tree init map function), the cpu id value may include the cluster id and is no longer 0-3, so we need to mask it in scu_power_mode to get the local cpu number. Since we are only dealing with the cpu we are running on, the cluster id should not ever be needed. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
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