diff options
Diffstat (limited to 'arch/arm/boot/dts/hi3620.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/hi3620.dtsi | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index 242a47c8401a..34221f717c88 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -116,6 +116,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc26m &pclk>; + hiword; clock-output-names = "rclk_uart0"; /* reg_offset, enable_bits */ hisilicon,clkmux-reg = <0x100 0x80>; @@ -125,6 +126,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc26m &pclk>; + hiword; clock-output-names = "rclk_uart1"; hisilicon,clkmux-reg = <0x100 0x100>; hisilicon,clkmux-table = <0 0x100>; @@ -133,6 +135,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc26m &pclk>; + hiword; clock-output-names = "rclk_uart2"; hisilicon,clkmux-reg = <0x100 0x200>; hisilicon,clkmux-table = <0 0x200>; @@ -141,6 +144,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc26m &pclk>; + hiword; clock-output-names = "rclk_uart3"; hisilicon,clkmux-reg = <0x100 0x400>; hisilicon,clkmux-table = <0 0x400>; @@ -149,6 +153,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc26m &pclk>; + hiword; clock-output-names = "rclk_uart4"; hisilicon,clkmux-reg = <0x100 0x800>; hisilicon,clkmux-table = <0 0x800>; @@ -158,6 +163,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&pll_usb &pll_peri>; + hiword; clock-output-names = "rclk_hsic"; hisilicon,clkmux-reg = <0x130 0x4>; hisilicon,clkmux-table = <0 0x4>; @@ -184,6 +190,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc26m &refclk_cfgaxi>; + hiword; clock-output-names = "rclk_spi0"; hisilicon,clkmux-reg = <0x100 0x1000>; hisilicon,clkmux-table = <0 0x1000>; @@ -192,6 +199,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc26m &refclk_cfgaxi>; + hiword; clock-output-names = "rclk_spi1"; hisilicon,clkmux-reg = <0x100 0x2000>; hisilicon,clkmux-table = <0 0x2000>; @@ -200,6 +208,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc26m &refclk_cfgaxi>; + hiword; clock-output-names = "rclk_spi2"; hisilicon,clkmux-reg = <0x100 0x4000>; hisilicon,clkmux-table = <0 0x4000>; @@ -279,6 +288,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&pll_usb &pll_peri>; + hiword; clock-output-names = "rclk_shareAXI"; hisilicon,clkmux-reg = <0x24 0x8000>; hisilicon,clkmux-table = <0 0x8000>; @@ -287,6 +297,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&pll_peri &pll_usb>; + hiword; clock-output-names = "rclk_mmc1"; hisilicon,clkmux-reg = <0x108 0x200>; hisilicon,clkmux-table = <0 0x200>; @@ -295,6 +306,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&pll_peri &pll_usb>; + hiword; clock-output-names = "rclk_mmc2"; hisilicon,clkmux-reg = <0x140 0x10>; hisilicon,clkmux-table = <0 0x10>; @@ -303,6 +315,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&pll_peri &pll_usb>; + hiword; clock-output-names = "rclk_mmc3"; hisilicon,clkmux-reg = <0x140 0x200>; hisilicon,clkmux-table = <0 0x200>; @@ -311,6 +324,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&pll_peri &pll_usb>; + hiword; clock-output-names = "rclk_sd"; hisilicon,clkmux-reg = <0x108 0x10>; hisilicon,clkmux-table = <0 0x10>; @@ -318,6 +332,7 @@ refclk_mmc1_parent: refclk@27 { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; + hiword; clocks = <&osc26m &div_mmc1>; clock-output-names = "rclk_mmc1_parent"; hisilicon,clkmux-reg = <0x108 0x400>; @@ -326,6 +341,7 @@ refclk_venc: refclk@28 { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; + hiword; clocks = <&pll_peri &pll_usb>; clock-output-names = "rclk_venc"; hisilicon,clkmux-reg = <0x10c 0x800>; @@ -334,6 +350,7 @@ refclk_g2d: refclk@29 { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; + hiword; clocks = <&pll_peri &pll_usb>; clock-output-names = "rclk_g2d"; hisilicon,clkmux-reg = <0x10c 0x20>; @@ -342,6 +359,7 @@ refclk_vdec: refclk@30 { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; + hiword; clocks = <&pll_peri &pll_usb>; clock-output-names = "rclk_vdec"; hisilicon,clkmux-reg = <0x110 0x20>; @@ -350,6 +368,7 @@ refclk_vpp: refclk@31 { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; + hiword; clocks = <&pll_peri &pll_usb>; clock-output-names = "rclk_vpp"; hisilicon,clkmux-reg = <0x110 0x800>; @@ -358,6 +377,7 @@ refclk_ldi0: refclk@32 { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; + hiword; clocks = <&pll_peri &pll_usb &pll_hdmi>; clock-output-names = "rclk_ldi0"; hisilicon,clkmux-reg = <0x114 0x6000>; @@ -366,6 +386,7 @@ refclk_ldi1: refclk@33 { compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; + hiword; clocks = <&pll_peri &pll_usb &pll_hdmi>; clock-output-names = "rclk_ldi1"; hisilicon,clkmux-reg = <0x118 0xc000>; @@ -639,6 +660,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc32k &pwm_divider>; + hiword; clock-output-names = "pwm0_mux"; hisilicon,clkmux-reg = <0x104 0x400>; hisilicon,clkmux-table = <0 0x400>; @@ -647,6 +669,7 @@ compatible = "hisilicon,hi3620-clk-mux"; #clock-cells = <0>; clocks = <&osc32k &pwm_divider>; + hiword; clock-output-names = "pwm1_mux"; hisilicon,clkmux-reg = <0x104 0x800>; hisilicon,clkmux-table = <0 0x800>; |