diff options
| -rw-r--r-- | arch/arm/boot/dts/hi3620.dtsi | 49 | ||||
| -rw-r--r-- | arch/arm/boot/dts/hi4511.dts | 74 |
2 files changed, 103 insertions, 20 deletions
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index a6c0a5035be8..677cccb21800 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -15,6 +15,10 @@ aliases { serial0 = &uart0; serial1 = &uart1; + mshc0 = &dwmmc_0; + mshc1 = &dwmmc_1; + mshc2 = &dwmmc_2; + mshc3 = &dwmmc_3; }; amba { @@ -36,6 +40,11 @@ reg = <0xfca08000 0x1000>; }; + pctrl: pctrl@fca09000 { + compatible = "hisilicon,pctrl"; + reg = <0xfca09000 0x1000>; + }; + /*clocks begins*/ clocks { #address-cells = <1>; @@ -1266,5 +1275,45 @@ clocks = <&clk_i2c3>; status = "disabled"; }; + + /* unremovable emmc as mmcblk0 */ + dwmmc_1: dwmmc1@fcd04000 { + compatible = "hisilicon,hi4511-dw-mshc"; + reg = <0xfcd04000 0x1000>; + interrupts = <0 17 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_mmc1>, <&clk_ddrc_per>; + clock-names = "ciu", "biu"; + }; + + /* sd as mmcblk1 */ + dwmmc_0: dwmmc0@fcd03000 { + compatible = "hisilicon,hi4511-dw-mshc"; + reg = <0xfcd03000 0x1000>; + interrupts = <0 16 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_sd>, <&clk_ddrc_per>; + clock-names = "ciu", "biu"; + }; + + dwmmc_2: dwmmc2@fcd05000 { + compatible = "hisilicon,hi4511-dw-mshc"; + reg = <0xfcd05000 0x1000>; + interrupts = <0 18 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_mmc2>; + }; + + dwmmc_3: dwmmc3@fcd06000 { + compatible = "hisilicon,hi4511-dw-mshc"; + reg = <0xfcd06000 0x1000>; + interrupts = <0 19 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_mmc3>; + }; }; }; diff --git a/arch/arm/boot/dts/hi4511.dts b/arch/arm/boot/dts/hi4511.dts index 01848218cb7a..d7e02589cb45 100644 --- a/arch/arm/boot/dts/hi4511.dts +++ b/arch/arm/boot/dts/hi4511.dts @@ -215,6 +215,7 @@ sd_pmx_pins: pinmux_sd_pins { pinctrl-single,pins = < 0x0bc 0x0 /* SD_CLK, SD_CMD, SD_DATA[0:2] */ + 0x0c0 0x0 /* SD_DATA[3] */ >; }; uart0_pmx_func: pinmux_uart0_pins@0 { @@ -384,18 +385,12 @@ emmc_pmx_func: pinmux_emmc_pins@0 { pinctrl-single,pins = < 0x030 0x2 /* eMMC_CMD/eMMC_CLK (IOMG12) */ - 0x018 0x0 /* NAND_CS3_N (IOMG6) */ - 0x024 0x0 /* NAND_BUSY2_N (IOMG8) */ - 0x028 0x0 /* NAND_BUSY3_N (IOMG9) */ 0x02c 0x2 /* eMMC_DATA[0:7] (IOMG10) */ >; }; emmc_pmx_idle: pinmux_emmc_pins@1 { pinctrl-single,pins = < 0x030 0x0 /* GPIO (IOMG12) */ - 0x018 0x1 /* GPIO (IOMG6) */ - 0x024 0x1 /* GPIO (IOMG8) */ - 0x028 0x1 /* GPIO (IOMG9) */ 0x02c 0x1 /* GPIO (IOMG10) */ >; }; @@ -677,10 +672,6 @@ emmc_cfg_func: pincfg_emmc_pins@0 { pinctrl-single,pins = < 0x0ac 0 /* eMMC_CMD (IOCFG40) */ - 0x0b0 0 /* eMMC_CLK (IOCFG41) */ - 0x058 0 /* NAND_CS3_N (IOCFG19) */ - 0x064 0 /* NAND_BUSY2_N (IOCFG22) */ - 0x068 0 /* NAND_BUSY3_N (IOCFG23) */ 0x08c 0 /* NAND_DATA8 (IOCFG32) */ 0x090 0 /* NAND_DATA9 (IOCFG33) */ 0x094 0 /* NAND_DATA10 (IOCFG34) */ @@ -694,24 +685,32 @@ pinctrl-single,bias-pullup = <1 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; + emmc_cfg_clk_func: pincfg_emmc_clk_pins@0 { + pinctrl-single,pins = < + 0x0b0 0 /* eMMC_CLK (IOCFG41) */ + >; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,drive-strength = <0x30 0xf0>; + }; sd_cfg_func1: pincfg_sd_f1_pins@0 { pinctrl-single,pins = < 0x18c 0 /* SD_CLK (IOCFG107) */ - 0x190 0 /* SD_CMD (IOCFG108) */ >; - pinctrl-single,bias-pulldown = <2 2 0 2>; + pinctrl-single,bias-pulldown = <0 2 0 2>; pinctrl-single,bias-pullup = <0 1 0 1>; pinctrl-single,drive-strength = <0x30 0xf0>; }; sd_cfg_func2: pincfg_sd_f2_pins@0 { pinctrl-single,pins = < + 0x190 0 /* SD_CMD (IOCFG108) */ 0x194 0 /* SD_DATA0 (IOCFG109) */ 0x198 0 /* SD_DATA1 (IOCFG110) */ 0x19c 0 /* SD_DATA2 (IOCFG111) */ 0x1a0 0 /* SD_DATA3 (IOCFG112) */ >; - pinctrl-single,bias-pulldown = <2 2 0 2>; - pinctrl-single,bias-pullup = <0 1 0 1>; + pinctrl-single,bias-pulldown = <0 2 0 2>; + pinctrl-single,bias-pullup = <1 1 0 1>; pinctrl-single,drive-strength = <0x70 0xf0>; }; nand_cfg_func1: pincfg_nand_f1_pins@0 { @@ -791,6 +790,43 @@ pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; }; + dwmmc1@fcd04000 { + num-slots = <1>; + vmmc-supply = <&ldo0>; + /* emmc fifo register value is incorrect */ + fifo-depth = <0x100>; + broken-cd; + supports-highspeed; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pmx_func &emmc_cfg_func &emmc_cfg_clk_func>; + slot@0 { + reg = <0>; + bus-width = <8>; + }; + }; + + dwmmc0@fcd03000 { + num-slots = <1>; + vmmc-supply = <&ldo12>; + fifo-depth = <0x100>; + supports-highspeed; + pinctrl-names = "default"; + pinctrl-0 = <&sd_pmx_pins &sd_cfg_func1 &sd_cfg_func2>; + slot@0 { + reg = <0>; + bus-width = <4>; + hisilicon,cd-pinmux-gpio = <&gpio10 3 0>; + }; + }; + + dwmmc2@fcd05000 { + status = "disabled"; + }; + + dwmmc3@fcd06000 { + status = "disabled"; + }; + regulators { compatible = "hisilicon,hi6421-pmic"; reg = <0xfcc00000 0x0180>; /* 0x60 << 2 */ @@ -798,10 +834,8 @@ ldo0: ldo@20 { compatible = "hisilicon,hi6421-ldo"; regulator-name = "LDO0"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; hisilicon,hi6421-ctrl = <0x20 0x10 0x20>; hisilicon,hi6421-vset = <0x20 0x07>; hisilicon,hi6421-n-voltages = <8>; @@ -1020,8 +1054,8 @@ ldo12: ldo@2c { compatible = "hisilicon,hi6421-ldo"; regulator-name = "LDO12"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; hisilicon,hi6421-ctrl = <0x2c 0x10 0x20>; hisilicon,hi6421-vset = <0x2c 0x07>; hisilicon,hi6421-n-voltages = <8>; |