ARM: hs: hi3716 dts modification

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>

2 files changed, 151 insertions, 135 deletions

diff --git a/arch/arm/boot/dts/hi3716-dkb.dts b/arch/arm/boot/dts/hi3716-dkb.dts
index 9bc2e725fe97..eae01c19f03c 100644
--- a/arch/arm/boot/dts/hi3716-dkb.dts
+++ b/arch/arm/boot/dts/hi3716-dkb.dts
@@ -21,13 +21,15 @@
 		reg = <0x00000000 0x20000000>;
 	};
 
-	amba {
-		timer0: timer@f8002000 {
-			status = "ok";
-		};
+	soc {
+		amba {
+			timer0: timer@f8002000 {
+				status = "ok";
+			};
 
-		uart0: uart@f8b00000 {
-			status = "ok";
+			uart0: uart@f8b00000 {
+				status = "ok";
+			};
 		};
 	};
 };
diff --git a/arch/arm/boot/dts/hi3716.dtsi b/arch/arm/boot/dts/hi3716.dtsi
index ae3670c97e60..05b70a0ae419 100644
--- a/arch/arm/boot/dts/hi3716.dtsi
+++ b/arch/arm/boot/dts/hi3716.dtsi
@@ -15,32 +15,156 @@
 		serial0 = &uart0;
 	};
 
-	amba {
+	intc: interrupt-controller@fc001000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		/* gic dist base, gic cpu base */
+		reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
+	};
+
+	soc {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "arm,amba-bus";
+		compatible = "simple-bus";
+		device_type = "soc";
 		interrupt-parent = <&intc>;
 		ranges;
 
-		pclk: clk@0 {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <54000000>;
-			clock-output-names = "apb_pclk";
-		};
-
-		timclk0: clk@1 {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <24000000>;
-			clock-output-names = "timerclk0";
+		amba {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "arm,amba-bus";
+			ranges;
+
+			timer0: timer@f8002000 {
+				compatible = "arm,sp804", "arm,primecell";
+				reg = <0xf8002000 0x1000>;
+				/* timer00 & timer01 */
+				interrupts = <0 24 4>;
+				clocks = <&timclk0>, <&timclk1>;
+				clock-names = "timer0", "timer1";
+				status = "disabled";
+			};
+
+			timer1: timer@f8a29000 {
+				/*
+				 * Only used in NORMAL state, not available ins
+				 * SLOW or DOZE state.
+				 * The rate is fixed in 24MHz.
+				 */
+				compatible = "arm,sp804", "arm,primecell";
+				reg = <0xf8a29000 0x1000>;
+				/* timer10 & timer11 */
+				interrupts = <0 25 4>;
+				clocks = <&timclk0>, <&timclk1>;
+				clock-names = "timer0", "timer1";
+				status = "disabled";
+			};
+
+			timer2: timer@f8a2a000 {
+				compatible = "arm,sp804", "arm,primecell";
+				reg = <0xf8a2a000 0x1000>;
+				/* timer20 & timer21 */
+				interrupts = <0 26 4>;
+				clocks = <&timclk0>, <&timclk1>;
+				clock-names = "timer0", "timer1";
+				status = "disabled";
+			};
+
+			timer3: timer@f8a2b000 {
+				compatible = "arm,sp804", "arm,primecell";
+				reg = <0xf8a2b000 0x1000>;
+				/* timer30 & timer31 */
+				interrupts = <0 27 4>;
+				clocks = <&timclk0>, <&timclk1>;
+				clock-names = "timer0", "timer1";
+				status = "disabled";
+			};
+
+			timer4: timer@f8a81000 {
+				compatible = "arm,sp804", "arm,primecell";
+				reg = <0xf8a81000 0x1000>;
+				/* timer30 & timer31 */
+				interrupts = <0 28 4>;
+				clocks = <&timclk0>, <&timclk1>;
+				clock-names = "timer0", "timer1";
+				status = "disabled";
+			};
+
+			uart0: uart@f8b00000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xf8b00000 0x1000>;
+				/* reg = <0x101fb000 0x1000>; */
+				interrupts = <0 49 4>;
+				clocks = <&pclk>;
+				clock-names = "apb_pclk";
+				status = "disabled";
+			};
+
+			uart1: uart@f8006000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xf8006000 0x1000>;
+				interrupts = <0 50 4>;
+				clocks = <&pclk>;
+				clock-names = "apb_pclk";
+				status = "disabled";
+			};
+
+			uart2: uart@f8b02000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xf8b02000 0x1000>;
+				interrupts = <0 51 4>;
+				clocks = <&pclk>;
+				clock-names = "apb_pclk";
+				status = "disabled";
+			};
+
+			uart3: uart@f8b03000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xf8b03000 0x1000>;
+				interrupts = <0 52 4>;
+				clocks = <&pclk>;
+				clock-names = "apb_pclk";
+				status = "disabled";
+			};
+
+			uart4: uart@f8b04000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0xf8b04000 0x1000>;
+				interrupts = <0 53 4>;
+				clocks = <&pclk>;
+				clock-names = "apb_pclk";
+				status = "disabled";
+			};
 		};
 
-		timclk1: clk@2 {
-			compatible = "fixed-clock";
-			#clock-cells = <0>;
-			clock-frequency = <24000000>;
-			clock-output-names = "timerclk1";
+		clocks {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			pclk: clk@0 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <54000000>;
+				clock-output-names = "apb_pclk";
+			};
+
+			timclk0: clk@1 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <24000000>;
+				clock-output-names = "timerclk0";
+			};
+
+			timclk1: clk@2 {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-frequency = <24000000>;
+				clock-output-names = "timerclk1";
+			};
 		};
 
 		l2: l2-cache {
@@ -50,115 +174,5 @@
 			cache-unified;
 			cache-level = <2>;
 		};
-
-		intc: interrupt-controller@fc001000 {
-			compatible = "arm,cortex-a9-gic";
-			#interrupt-cells = <3>;
-			#address-cells = <0>;
-			interrupt-controller;
-			/* gic dist base, gic cpu base */
-			reg = <0xf8a01000 0x1000>, <0xf8a00100 0x100>;
-		};
-
-		timer0: timer@f8002000 {
-			compatible = "arm,sp804", "arm,primecell";
-			reg = <0xf8002000 0x1000>;
-			/* timer00 & timer01 */
-			interrupts = <0 24 4>;
-			clocks = <&timclk0>, <&timclk1>;
-			clock-names = "timer0", "timer1";
-			status = "disabled";
-		};
-
-		timer1: timer@f8a29000 {
-			/*
-			 * Only used in NORMAL state, not available ins
-			 * SLOW or DOZE state.
-			 * The rate is fixed in 24MHz.
-			 */
-			compatible = "arm,sp804", "arm,primecell";
-			reg = <0xf8a29000 0x1000>;
-			/* timer10 & timer11 */
-			interrupts = <0 25 4>;
-			clocks = <&timclk0>, <&timclk1>;
-			clock-names = "timer0", "timer1";
-			status = "disabled";
-		};
-
-		timer2: timer@f8a2a000 {
-			compatible = "arm,sp804", "arm,primecell";
-			reg = <0xf8a2a000 0x1000>;
-			/* timer20 & timer21 */
-			interrupts = <0 26 4>;
-			clocks = <&timclk0>, <&timclk1>;
-			clock-names = "timer0", "timer1";
-			status = "disabled";
-		};
-
-		timer3: timer@f8a2b000 {
-			compatible = "arm,sp804", "arm,primecell";
-			reg = <0xf8a2b000 0x1000>;
-			/* timer30 & timer31 */
-			interrupts = <0 27 4>;
-			clocks = <&timclk0>, <&timclk1>;
-			clock-names = "timer0", "timer1";
-			status = "disabled";
-		};
-
-		timer4: timer@f8a81000 {
-			compatible = "arm,sp804", "arm,primecell";
-			reg = <0xf8a81000 0x1000>;
-			/* timer30 & timer31 */
-			interrupts = <0 28 4>;
-			clocks = <&timclk0>, <&timclk1>;
-			clock-names = "timer0", "timer1";
-			status = "disabled";
-		};
-
-		uart0: uart@f8b00000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0xf8b00000 0x1000>;
-			/* reg = <0x101fb000 0x1000>; */
-			interrupts = <0 49 4>;
-			clocks = <&pclk>;
-			clock-names = "apb_pclk";
-			status = "disabled";
-		};
-
-		uart1: uart@f8006000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0xf8006000 0x1000>;
-			interrupts = <0 50 4>;
-			clocks = <&pclk>;
-			clock-names = "apb_pclk";
-			status = "disabled";
-		};
-
-		uart2: uart@f8b02000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0xf8b02000 0x1000>;
-			interrupts = <0 51 4>;
-			clocks = <&pclk>;
-			clock-names = "apb_pclk";
-			status = "disabled";
-		};
-
-		uart3: uart@f8b03000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0xf8b03000 0x1000>;
-			interrupts = <0 52 4>;
-			clocks = <&pclk>;
-			clock-names = "apb_pclk";
-			status = "disabled";
-		};
-
-		uart4: uart@f8b04000 {
-			compatible = "arm,pl011", "arm,primecell";
-			reg = <0xf8b04000 0x1000>;
-			interrupts = <0 53 4>;
-			clocks = <&pclk>;
-			clock-names = "apb_pclk";
-			status = "disabled";
-		};
 	};
 };