diff options
| author | Zhangfei Gao <zhangfei.gao@linaro.org> | 2013-03-19 14:52:32 +0800 |
|---|---|---|
| committer | Zhangfei Gao <zhangfei.gao@linaro.org> | 2013-03-19 14:52:32 +0800 |
| commit | fb1be4799a98e158e316d3caf07c459ef0ac6438 (patch) | |
| tree | 47cab173e981334e3f905e039fd277950b7baf32 /arch/arm/boot/dts/hi3620.dtsi | |
| parent | e048346955a2661d5f8fedd5840df45df1ec9ff0 (diff) | |
mmc: dw-mmc-hisilicon add workaround
to be reverted
Since clk driver still can not choose parent accordingly, add testsdclk and
access register directly for simplicity
The patch can be reverted if clk driver is enhanced
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/hi3620.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/hi3620.dtsi | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index 677cccb21800..1487514455ad 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -107,6 +107,12 @@ clock-frequency = <1440000000>; clock-output-names = "clk_armpll2"; }; + testsdclk: testsd { + compatible = "hisilicon,pll"; + #clock-cells = <0>; + clocks = <&peripll>; + clock-frequency = <100000000>; + }; usbpll: pll3 { compatible = "hisilicon,pll"; #clock-cells = <0>; @@ -641,7 +647,8 @@ clk_mmc1: mmc1 { compatible = "hisilicon,periclock"; #clock-cells = <0>; - clocks = <&clk_mmc1_parent>; + clocks = <&testsdclk>; + /* clocks = <&clk_mmc1_parent>; */ hisilicon,hi3620-clkgate = <0x50 21>; }; @@ -662,7 +669,8 @@ clk_sd: sd { compatible = "hisilicon,periclock"; #clock-cells = <0>; - clocks = <&clk_div_sd>; + /* clocks = <&clk_div_sd>; */ + clocks = <&testsdclk>; hisilicon,hi3620-clkgate = <0x50 20>; }; |