diff options
author | Zhangfei Gao <zhangfei.gao@linaro.org> | 2013-03-19 14:26:07 +0800 |
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committer | Zhangfei Gao <zhangfei.gao@linaro.org> | 2013-03-19 14:52:06 +0800 |
commit | e048346955a2661d5f8fedd5840df45df1ec9ff0 (patch) | |
tree | 6f079cd6a195289fea9eeaa75c7e4a50c8935846 /arch/arm/boot/dts/hi3620.dtsi | |
parent | 33cf0c22628147b6016fe63d28dec0e9b2abbbad (diff) |
ARM: dts: add mmc resource
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/hi3620.dtsi')
-rw-r--r-- | arch/arm/boot/dts/hi3620.dtsi | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index a6c0a5035be8..677cccb21800 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -15,6 +15,10 @@ aliases { serial0 = &uart0; serial1 = &uart1; + mshc0 = &dwmmc_0; + mshc1 = &dwmmc_1; + mshc2 = &dwmmc_2; + mshc3 = &dwmmc_3; }; amba { @@ -36,6 +40,11 @@ reg = <0xfca08000 0x1000>; }; + pctrl: pctrl@fca09000 { + compatible = "hisilicon,pctrl"; + reg = <0xfca09000 0x1000>; + }; + /*clocks begins*/ clocks { #address-cells = <1>; @@ -1266,5 +1275,45 @@ clocks = <&clk_i2c3>; status = "disabled"; }; + + /* unremovable emmc as mmcblk0 */ + dwmmc_1: dwmmc1@fcd04000 { + compatible = "hisilicon,hi4511-dw-mshc"; + reg = <0xfcd04000 0x1000>; + interrupts = <0 17 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_mmc1>, <&clk_ddrc_per>; + clock-names = "ciu", "biu"; + }; + + /* sd as mmcblk1 */ + dwmmc_0: dwmmc0@fcd03000 { + compatible = "hisilicon,hi4511-dw-mshc"; + reg = <0xfcd03000 0x1000>; + interrupts = <0 16 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_sd>, <&clk_ddrc_per>; + clock-names = "ciu", "biu"; + }; + + dwmmc_2: dwmmc2@fcd05000 { + compatible = "hisilicon,hi4511-dw-mshc"; + reg = <0xfcd05000 0x1000>; + interrupts = <0 18 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_mmc2>; + }; + + dwmmc_3: dwmmc3@fcd06000 { + compatible = "hisilicon,hi4511-dw-mshc"; + reg = <0xfcd06000 0x1000>; + interrupts = <0 19 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_mmc3>; + }; }; }; |