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| author | Haojian Zhuang <haojian.zhuang@linaro.org> | 2014-02-10 18:05:25 +0800 |
|---|---|---|
| committer | Haojian Zhuang <haojian.zhuang@linaro.org> | 2014-02-10 18:11:39 +0800 |
| commit | c4f71426b4dd3c46ec99549567b3e268ee001bea (patch) | |
| tree | 9ff24cd1c5f3a516d35539b62ebd9381f3256050 | |
| parent | 487b0e7cf0c757011bf9663441eb17fae53033c7 (diff) | |
ARM: dts: correct L2 register address of Hi3620hilt-core-track-20140210
Correct the register address of L2 controller in Hi3620 DTS file.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/hi3620.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index c227a221943f..6836795040ad 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -73,7 +73,7 @@ L2: l2-cache { compatible = "arm,pl310-cache"; - reg = <0xfc10000 0x100000>; + reg = <0x100000 0x100000>; interrupts = <0 15 4>; cache-unified; cache-level = <2>; |