ether: polish hip04

Also solve eth1 down/up error

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>

3 files changed, 164 insertions, 164 deletions

diff --git a/Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt b/Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt
index 6bc542a58d37..c918f0871165 100644
--- a/Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt
+++ b/Documentation/devicetree/bindings/net/hisilicon-hip04-net.txt
@@ -1,28 +1,74 @@
-* Hisilicon hip04 Ethernet Controller
+Hisilicon hip04 Ethernet Controller
+
+* Ethernet controller node
 
 Required properties:
 - compatible: should be "hisilicon,hip04-mac".
 - reg: address and length of the register set for the device.
 - interrupts: interrupt for the device.
-- port: port number combined with the controller: range from 0 to 31.
+- port: ppe port number connected to the controller: range from 0 to 31.
 - speed: 100 (100M) or 1000 (1000M).
+- id: should be different and fe should be 0.
+
+Optional Properties:
+- phy-handle : the phandle to a PHY node
 
-Example:
-	ge0: ethernet@2800000 {
-		compatible = "hisilicon,hip04-mac";
-		reg = <0x2800000 0x10000>;
-		interrupts = <0 434 4>;
-		port = <0>;
-		speed = <1000>;
-	};
 
-* Hisilicon hip04 Ethernet ppe: control rx & rx fifos of all ethnet controllers
+* Ethernet ppe node: control rx & tx fifos of all ethernet controllers
 
 Required properties:
-- compatible: should be "hisilicon,ppebase".
+- compatible: should be "hisilicon,hip04-ppebase".
+- reg: address and length of the register set for the node.
+
+
+* MDIO bus node:
+
+Required properties:
+
+- compatible: "hisilicon,hip04-mdio"
+- Inherets from MDIO bus node binding[1]
+[1] Documentation/devicetree/bindings/net/phy.txt
 
 Example:
+	mdio {
+		compatible = "hisilicon,hip04-mdio";
+		reg = <0x28f1000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		phy0: ethernet-phy@0 {
+			reg = <0>;
+			marvell,reg-init = <18 0x14 0 0x8001>;
+			device_type = "ethernet-phy";
+		};
+
+		phy1: ethernet-phy@1 {
+			reg = <1>;
+			marvell,reg-init = <18 0x14 0 0x8001>;
+			device_type = "ethernet-phy";
+		};
+	};
+
 	ppebase: ppebase@28c0000 {
-		compatible = "hisilicon,ppebase";
+		compatible = "hisilicon,hip04-ppebase";
 		reg = <0x28c0000 0x10000>;
 	};
+
+	fe: ethernet@28b0000 {
+		compatible = "hisilicon,hip04-mac";
+		reg = <0x28b0000 0x10000>;
+		interrupts = <0 413 4>;
+		port = <31>;
+		speed = <100>;
+		id = <0>;
+	};
+
+	ge0: ethernet@2800000 {
+		compatible = "hisilicon,hip04-mac";
+		reg = <0x2800000 0x10000>;
+		interrupts = <0 402 4>;
+		port = <0>;
+		speed = <1000>;
+		id = <1>;
+		phy-handle = <&phy0>;
+	};
diff --git a/drivers/net/ethernet/hisilicon/hip04_eth.c b/drivers/net/ethernet/hisilicon/hip04_eth.c
index 9621e1b77a40..877526b95ed3 100644
--- a/drivers/net/ethernet/hisilicon/hip04_eth.c
+++ b/drivers/net/ethernet/hisilicon/hip04_eth.c
@@ -17,53 +17,54 @@
 #include <linux/phy.h>
 #include <linux/of_mdio.h>
 
-#define PPE_CFG_RX_CFF_ADDR	0x100
-#define PPE_CFG_POOL_GRP	0x300
-#define PPE_CFG_RX_BUF_SIZE	0x400
-#define PPE_CFG_RX_FIFO_SIZE	0x500
-#define PPE_CURR_BUF_CNT_REG	0xa200
-
-#define GE_DUPLEX_TYPE		0x8
-#define GE_PORT_MODE		0x40
-#define GE_PORT_EN		0x44
-#define GE_MODE_CHANGE_EN	0x1b4
-#define GE_STATION_MAC_ADDRESS	0x210
-#define PPE_CFG_TX_PKT_BD_ADDR	0x420
-#define PPE_CFG_RX_CTRL_REG	0x428
-#define PPE_CFG_QOS_VMID_GEN	0x500
-#define PPE_CFG_RX_PKT_INT	0x538
-#define PPE_INTEN		0x600
-#define PPE_INTSTS		0x608
-#define PPE_RINT		0x604
-#define PPE_CFG_STS_MODE	0x700
-#define PPE_HIS_RX_PKT_CNT	0x804
-
-#define GE_MAX_FRM_SIZE_REG	0x3c
-#define GE_SHORT_RUNTS_THR_REG	0x50
-#define GE_TX_LOCAL_PAGE_REG	0x5c
-#define GE_TRANSMIT_CONTROL_REG	0x60
-#define GE_CF_CRC_STRIP_REG	0x1b0
-#define GE_RECV_CONTROL_REG	0x1e0
+#define PPE_CFG_RX_CFF_ADDR		0x100
+#define PPE_CFG_POOL_GRP		0x300
+#define PPE_CFG_RX_BUF_SIZE		0x400
+#define PPE_CFG_RX_FIFO_SIZE		0x500
+#define PPE_CURR_BUF_CNT_REG		0xa200
+
+#define GE_DUPLEX_TYPE			0x8
+#define GE_PORT_MODE			0x40
+#define GE_PORT_EN			0x44
+#define GE_MODE_CHANGE_EN		0x1b4
+#define GE_STATION_MAC_ADDRESS		0x210
+#define PPE_CFG_TX_PKT_BD_ADDR		0x420
+#define PPE_CFG_RX_CTRL_REG		0x428
+#define PPE_CFG_QOS_VMID_GEN		0x500
+#define PPE_CFG_RX_PKT_INT		0x538
+#define PPE_INTEN			0x600
+#define PPE_INTSTS			0x608
+#define PPE_RINT			0x604
+#define PPE_CFG_STS_MODE		0x700
+#define PPE_HIS_RX_PKT_CNT		0x804
+
+#define GE_MAX_FRM_SIZE_REG		0x3c
+#define GE_SHORT_RUNTS_THR_REG		0x50
+#define GE_TX_LOCAL_PAGE_REG		0x5c
+#define GE_TRANSMIT_CONTROL_REG		0x60
+#define GE_CF_CRC_STRIP_REG		0x1b0
+#define GE_RECV_CONTROL_REG		0x1e0
 #define PPE_CFG_MAX_FRAME_LEN_REG	0x408
-#define PPE_CFG_BUS_CTRL_REG	0x424
-#define PPE_CFG_RX_PKT_MODE_REG	0x438
-#define GMAC_PPE_RX_PKT_MAX_LEN  (379)
-#define GMAC_MAX_PKT_LEN         1516
-
-/* REG_INTERRUPT_MASK */
-#define RCV_INT			BIT(10)
-#define RCV_NOBUF		BIT(8)
-#define DEF_INT_MASK		0x41fdf
-
-#define RX_DESC_NUM		64
-#define TX_DESC_NUM		64
-#define TX_NEXT(N)		(((N) + 1) & (TX_DESC_NUM-1))
-#define RX_NEXT(N)		(((N) + 1) & (RX_DESC_NUM-1))
-
-#define DESC_DEF_CFG		0x14
-#define RX_BUF_SIZE		1600
-#define TX_TIMEOUT		(6 * HZ)
-#define DRV_NAME		"hip04-ether"
+#define PPE_CFG_BUS_CTRL_REG		0x424
+#define PPE_CFG_RX_PKT_MODE_REG		0x438
+#define GMAC_PPE_RX_PKT_MAX_LEN		379
+#define GMAC_MAX_PKT_LEN		1516
+
+/* REG_INTERRUPT */
+#define RCV_INT				BIT(10)
+#define RCV_NOBUF			BIT(8)
+#define DEF_INT_MASK			0x41fdf
+
+#define RX_DESC_NUM			64
+#define TX_DESC_NUM			64
+#define TX_NEXT(N)			(((N) + 1) & (TX_DESC_NUM-1))
+#define RX_NEXT(N)			(((N) + 1) & (RX_DESC_NUM-1))
+
+#define DESC_DEF_CFG			0x14
+#define RX_BUF_SIZE			1600
+#define TX_TIMEOUT			(6 * HZ)
+
+#define DRV_NAME			"hip04-ether"
 
 #define OBSOLETE_BUFFER
 
@@ -78,7 +79,7 @@ struct tx_desc {
 struct rx_desc {
 	u16 pkt_len;
 	u16 reserved_16;
-	u32 reserve[8];		/* simplified */
+	u32 reserve[8];
 };
 
 struct hip04_priv {
@@ -114,38 +115,31 @@ static void __iomem *ppebase;
 
 static void hip04_config_port(struct hip04_priv *priv, u32 speed, u32 duplex)
 {
-	u32 val, reg;
+	u32 val;
 
 	priv->speed = speed;
 	priv->duplex = duplex;
 
 	switch (speed) {
 	case SPEED_1000:
-		reg = 8;
+		val = 8;
 		break;
 	case SPEED_100:
-		if (!priv->id)
-			reg = 1;
+		if (priv->id)
+			val = 7;
 		else
-			reg = 7;
+			val = 1;
 		break;
 	default:
-		reg = 0;
+		val = 0;
 		break;
 	}
-	val = readl_relaxed(priv->base + GE_PORT_MODE);
-	val &= ~(0xf);
-	val |= reg;
 	writel_relaxed(val, priv->base + GE_PORT_MODE);
 
-	reg = (duplex) ? BIT(0) : 0;
-	val = readl_relaxed(priv->base + GE_DUPLEX_TYPE);
-	val &= ~(0x1);
-	val |= reg;
+	val = (duplex) ? BIT(0) : 0;
 	writel_relaxed(val, priv->base + GE_DUPLEX_TYPE);
 
-	val = readl_relaxed(priv->base + GE_MODE_CHANGE_EN);
-	val |= BIT(0);
+	val = BIT(0);
 	writel_relaxed(val, priv->base + GE_MODE_CHANGE_EN);
 }
 
@@ -165,90 +159,69 @@ static void hip04_config_fifo(struct hip04_priv *priv)
 	u32 val;
 
 	val = readl_relaxed(priv->base + PPE_CFG_STS_MODE);
-	val |= BIT(12);		/* PPE_HIS_RX_PKT_CNT read clear */
+	val |= BIT(12);			/* PPE_HIS_RX_PKT_CNT read clear */
 	writel_relaxed(val, priv->base + PPE_CFG_STS_MODE);
 
-	val = readl_relaxed(ppebase + priv->port * 4 + PPE_CFG_POOL_GRP);
-	val |= BIT(priv->port);
+	val = BIT(priv->port);
 	writel_relaxed(val, ppebase + priv->port * 4 + PPE_CFG_POOL_GRP);
 
-	val = readl_relaxed(priv->base + PPE_CFG_QOS_VMID_GEN);
-	val &= ~(0x7f00);		/* [14:8]*/
+	val = priv->port << 8;
 	val |= BIT(14);
-	val |= priv->port << 8;
 	writel_relaxed(val, priv->base + PPE_CFG_QOS_VMID_GEN);
 
-	val = readl_relaxed(ppebase + priv->port * 4 + PPE_CFG_RX_BUF_SIZE);
-	val &= ~(0xffff);		/* [15:0]*/
-	val |= RX_BUF_SIZE;
+	val = RX_BUF_SIZE;
 	writel_relaxed(val, ppebase + priv->port * 4 + PPE_CFG_RX_BUF_SIZE);
 
-	val = readl_relaxed(ppebase + priv->port * 4 + PPE_CFG_RX_FIFO_SIZE);
-	val &= ~(0xfff0fff);			/* [27:16] [11:0]*/
-	val |= RX_DESC_NUM << 16;		/* depth */
-	val |= BIT(11);				/* seq: first set first ues */
-	val |= RX_DESC_NUM * priv->id;		/* start_addr */
+	val = RX_DESC_NUM << 16;	/* depth */
+	val |= BIT(11);			/* seq: first set first ues */
+	val |= RX_DESC_NUM * priv->id;	/* start_addr */
 	writel_relaxed(val, ppebase + priv->port * 4 + PPE_CFG_RX_FIFO_SIZE);
 
 	/* pkt store format */
-	val = readl_relaxed(priv->base + PPE_CFG_RX_CTRL_REG);
-	val &= ~(0x1f80f);		/* [16:11] [3:0]*/
-	val |= 2 << 11;			/* align */
+	val = NET_IP_ALIGN << 11;	/* align */
 	writel_relaxed(val, priv->base + PPE_CFG_RX_CTRL_REG);
 
 	/* following cfg required for 1000M */
 	/* pkt mode */
-	val = readl_relaxed(priv->base + PPE_CFG_RX_PKT_MODE_REG);
-	val &= ~(0xc0000);		/* [19:18] */
-	val |= 1 << 18;			/* align */
+	val = BIT(18);			/* align */
 	writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_MODE_REG);
 
 	/* set bus ctrl */
-	val = 1 << 14;	/* buffer locally release */
-	val |= 1;	/* big endian */
+	val = BIT(14);			/* buffer locally release */
+	val |= BIT(0);			/* big endian */
 	writel_relaxed(val, priv->base + PPE_CFG_BUS_CTRL_REG);
 
 	/* set max pkt len, curtail if exceed */
-	val = readl_relaxed(priv->base + PPE_CFG_MAX_FRAME_LEN_REG);
-	val &= ~(0x3fff);		/* [13:0]*/
-	val |= GMAC_PPE_RX_PKT_MAX_LEN;	/* max buffer len */
+	val = GMAC_PPE_RX_PKT_MAX_LEN;	/* max buffer len */
 	writel_relaxed(val, priv->base + PPE_CFG_MAX_FRAME_LEN_REG);
 
 	/* set max len of each pkt */
-	val = readl_relaxed(priv->base + GE_MAX_FRM_SIZE_REG);
-	val &= ~(0xffff);		/* [15:0]*/
-	val |= GMAC_MAX_PKT_LEN;	/* max buffer len */
+	val = GMAC_MAX_PKT_LEN;		/* max buffer len */
 	writel_relaxed(val, priv->base + GE_MAX_FRM_SIZE_REG);
 
 	/* set min len of each pkt */
-	val = readl_relaxed(priv->base + GE_SHORT_RUNTS_THR_REG);
-	val |= 31;			/* min buffer len */
+	val = 31;			/* min buffer len */
 	writel_relaxed(val, priv->base + GE_SHORT_RUNTS_THR_REG);
 
 	/* tx */
 	val = readl_relaxed(priv->base + GE_TRANSMIT_CONTROL_REG);
-	val |= 1 << 5;			/* tx auto neg */
-	val |= 1 << 6;			/* tx add crc */
-	val |= 1 << 7;			/* tx short pad through */
+	val |= BIT(5);			/* tx auto neg */
+	val |= BIT(6);			/* tx add crc */
+	val |= BIT(7);			/* tx short pad through */
 	writel_relaxed(val, priv->base + GE_TRANSMIT_CONTROL_REG);
 
 	/* rx crc */
-	val = readl_relaxed(priv->base + GE_CF_CRC_STRIP_REG);
-	val |= 1;			/* rx strip crc */
+	val = BIT(0);			/* rx strip crc */
 	writel_relaxed(val, priv->base + GE_CF_CRC_STRIP_REG);
 
 	/* rx */
 	val = readl_relaxed(priv->base + GE_RECV_CONTROL_REG);
-	val |= 1 << 3;			/* rx strip pad */
-	val |= 1 << 4;			/* run pkt en */
+	val |= BIT(3);			/* rx strip pad */
+	val |= BIT(4);			/* run pkt en */
 	writel_relaxed(val, priv->base + GE_RECV_CONTROL_REG);
 
 	/* auto neg control */
-	val = readl_relaxed(priv->base + GE_TX_LOCAL_PAGE_REG);
-	val |= 1;
-	val &= ~(0x1e0);	/* [8:5] = 0*/
-	val &= ~(0x3c0);	/* [13:10] = 0*/
-	val &= ~(0x8000);	/* [15] = 0*/
+	val = BIT(0);
 	writel_relaxed(val, priv->base + GE_TX_LOCAL_PAGE_REG);
 }
 
@@ -260,8 +233,8 @@ static void hip04_mac_enable(struct net_device *ndev, bool enable)
 	if (enable) {
 		/* enable tx & rx */
 		val = readl_relaxed(priv->base + GE_PORT_EN);
-		val |= 0x1 << 1;	/* rx*/
-		val |= 0x1 << 2;	/* tx*/
+		val |= BIT(1);		/* rx*/
+		val |= BIT(2);		/* tx*/
 		writel_relaxed(val, priv->base + GE_PORT_EN);
 
 		/* enable interrupt */
@@ -273,9 +246,7 @@ static void hip04_mac_enable(struct net_device *ndev, bool enable)
 		writel_relaxed(val, priv->base + PPE_RINT);
 
 		/* config recv int*/
-		val = readl_relaxed(priv->base + PPE_CFG_RX_PKT_INT);
-		val &= ~(0x0fff);	/* [11:0] */
-		val |= 0x1 << 6;	/* int threshold 1 package */
+		val = BIT(6);		/* int threshold 1 package */
 		val |= 0x4;		/* recv timeout */
 		writel_relaxed(val, priv->base + PPE_CFG_RX_PKT_INT);
 	} else {
@@ -285,8 +256,8 @@ static void hip04_mac_enable(struct net_device *ndev, bool enable)
 
 		/* disable tx & rx */
 		val = readl_relaxed(priv->base + GE_PORT_EN);
-		val &= ~(0x1 << 1);	/* rx*/
-		val &= ~(0x1 << 2);	/* tx*/
+		val &= ~(BIT(1));	/* rx*/
+		val &= ~(BIT(2));	/* tx*/
 		writel_relaxed(val, priv->base + GE_PORT_EN);
 	}
 }
@@ -319,12 +290,7 @@ static void hip04_update_mac_address(struct net_device *ndev)
 
 static int hip04_set_mac_address(struct net_device *ndev, void *addr)
 {
-	struct sockaddr *address = addr;
-
-	if (!is_valid_ether_addr(address->sa_data))
-		return -EADDRNOTAVAIL;
-
-	memcpy(ndev->dev_addr, address->sa_data, ndev->addr_len);
+	eth_mac_addr(ndev, addr);
 	hip04_update_mac_address(ndev);
 
 	return 0;
@@ -513,8 +479,10 @@ static void hip04_adjust_link(struct net_device *ndev)
 	struct hip04_priv *priv = netdev_priv(ndev);
 	struct phy_device *phy = priv->phy;
 
-	if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex))
+	if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex)) {
 		hip04_config_port(priv, phy->speed, phy->duplex);
+		phy_print_status(phy);
+	}
 }
 
 static int hip04_mac_open(struct net_device *ndev)
@@ -522,15 +490,21 @@ static int hip04_mac_open(struct net_device *ndev)
 	struct hip04_priv *priv = netdev_priv(ndev);
 	int i;
 
-#ifndef OBSOLETE_BUFFER
 	hip04_reset_ppe(priv);
 	for (i = 0; i < RX_DESC_NUM; i++) {
+#ifdef OBSOLETE_BUFFER
+		struct sk_buff *skb = NULL;
+		skb = priv->rx_skb[i];
+		dma_map_single(&ndev->dev, (skb->data),
+				RX_BUF_SIZE, DMA_TO_DEVICE);
+		hip04_set_recv_desc(priv, virt_to_phys(skb->data));
+#else
 		dma_map_single(&ndev->dev, priv->rx_buf[i],
 				RX_BUF_SIZE, DMA_TO_DEVICE);
 		hip04_set_recv_desc(priv, virt_to_phys(priv->rx_buf[i]));
+#endif
 	}
 	priv->rx_head = 0;
-#endif
 	priv->tx_head = 0;
 	priv->tx_tail = 0;
 	priv->tx_count = 0;
@@ -553,13 +527,15 @@ static int hip04_mac_stop(struct net_device *ndev)
 {
 	struct hip04_priv *priv = netdev_priv(ndev);
 
+	if (priv->phy)
+		phy_disconnect(priv->phy);
+	priv->phy = NULL;
+
 	napi_disable(&priv->napi);
 	netif_stop_queue(ndev);
 	hip04_mac_enable(ndev, false);
 	hip04_tx_reclaim(ndev, true);
-#ifndef OBSOLETE_BUFFER
 	hip04_reset_ppe(priv);
-#endif
 	return 0;
 }
 
@@ -583,17 +559,13 @@ static struct net_device_ops hip04_netdev_ops = {
 static int hip04_rx_ring_init(struct net_device *dev)
 {
 	struct hip04_priv *priv = netdev_priv(dev);
-	struct sk_buff      *skb       = NULL;
+	struct sk_buff      *skb = NULL;
 	unsigned int         i;
 
 	for (i = 0; i < RX_DESC_NUM; i++) {
 		skb = dev_alloc_skb(RX_BUF_SIZE);
 		if (NULL == skb)
 			return -ENOMEM;
-		memset(skb->data, 0x0, RX_BUF_SIZE);
-		dma_map_single(&dev->dev, (skb->data),
-				RX_BUF_SIZE, DMA_TO_DEVICE);
-		hip04_set_recv_desc(priv, virt_to_phys(skb->data));
 		priv->rx_skb[i] = skb;
 	}
 	priv->rx_head = 0;
@@ -714,7 +686,6 @@ static int hip04_mac_probe(struct platform_device *pdev)
 		priv->speed = SPEED_1000;
 	priv->duplex = DUPLEX_FULL;
 
-	/* fixme any id can be used directly? */
 	ret = of_property_read_u32(node, "id", &priv->id);
 	if (ret) {
 		dev_warn(d, "not find id info\n");
@@ -751,7 +722,7 @@ static int hip04_mac_probe(struct platform_device *pdev)
 					0, pdev->name, ndev);
 	if (ret) {
 		netdev_err(ndev, "devm_request_irq failed\n");
-		goto init_fail;
+		goto alloc_fail;
 	}
 
 	priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
@@ -759,7 +730,7 @@ static int hip04_mac_probe(struct platform_device *pdev)
 	ret = register_netdev(ndev);
 	if (ret) {
 		free_netdev(ndev);
-		goto init_fail;
+		goto alloc_fail;
 	}
 
 	return 0;
@@ -778,9 +749,8 @@ static int hip04_remove(struct platform_device *pdev)
 
 	unregister_netdev(ndev);
 	free_irq(ndev->irq, ndev);
-	free_netdev(ndev);
-	free_netdev(ndev);
 	of_node_put(priv->phy_node);
+	free_netdev(ndev);
 
 	return 0;
 }
diff --git a/drivers/net/ethernet/hisilicon/hip04_mdio.c b/drivers/net/ethernet/hisilicon/hip04_mdio.c
index d9764e306d79..fb65f2ebbdd0 100644
--- a/drivers/net/ethernet/hisilicon/hip04_mdio.c
+++ b/drivers/net/ethernet/hisilicon/hip04_mdio.c
@@ -8,19 +8,11 @@
  * (at your option) any later version.
  */
 
-#include <linux/init.h>
-#include <linux/kernel.h>
 #include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/phy.h>
-#include <linux/interrupt.h>
 #include <linux/platform_device.h>
-#include <linux/delay.h>
 #include <linux/io.h>
-#include <linux/clk.h>
 #include <linux/of_mdio.h>
-#include <linux/sched.h>
-#include <linux/wait.h>
+#include <linux/delay.h>
 
 #define MDIO_CMD_REG		0x0
 #define MDIO_ADDR_REG		0x4
@@ -34,11 +26,10 @@
 #define MDIO_WRITE	        (BIT(12) | BIT(10) | MDIO_START)
 
 struct hip04_mdio_priv {
-	struct mutex lock;
 	void __iomem *base;
 };
 
-#define WAIT_TIMEOUT		10
+#define WAIT_TIMEOUT 10
 static int hip04_mdio_wait_ready(struct mii_bus *bus)
 {
 	struct hip04_mdio_priv *priv = bus->priv;
@@ -58,7 +49,6 @@ static int hip04_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 	struct hip04_mdio_priv *priv = bus->priv;
 	u32 val;
 	int ret;
-	mutex_lock(&priv->lock);
 
 	ret = hip04_mdio_wait_ready(bus);
 	if (ret < 0)
@@ -79,7 +69,6 @@ static int hip04_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 	val = readl_relaxed(priv->base + MDIO_RDATA_REG);
 	ret = val & 0xFFFF;
 out:
-	mutex_unlock(&priv->lock);
 	return ret;
 }
 
@@ -90,8 +79,6 @@ static int hip04_mdio_write(struct mii_bus *bus, int mii_id,
 	u32 val;
 	int ret;
 
-	mutex_lock(&priv->lock);
-
 	ret = hip04_mdio_wait_ready(bus);
 	if (ret < 0)
 		goto out;
@@ -100,7 +87,6 @@ static int hip04_mdio_write(struct mii_bus *bus, int mii_id,
 	val = (regnum & 0x1f) | ((mii_id & 0x1f) << 5) | MDIO_WRITE;
 	writel_relaxed(val, priv->base + MDIO_CMD_REG);
 out:
-	mutex_unlock(&priv->lock);
 	return ret;
 }
 
@@ -127,7 +113,7 @@ static int hip04_mdio_probe(struct platform_device *pdev)
 	struct resource *r;
 	struct mii_bus *bus;
 	struct hip04_mdio_priv *priv;
-	int i, ret;
+	int ret;
 
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!r) {
@@ -156,8 +142,6 @@ static int hip04_mdio_probe(struct platform_device *pdev)
 		goto out_mdio;
 	}
 
-	mutex_init(&priv->lock);
-
 	ret = of_mdiobus_register(bus, pdev->dev.of_node);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);