ARM: hip04: drop temporary vsemiphy init code

The Vsemi Serdes initialization code of SATA was moved into UEFI,
so drop them form kernel.

Signed-off-by: Kefeng Wang <kefeng.wang@linaro.org>

3 files changed, 1 insertions, 739 deletions

diff --git a/arch/arm/mach-hisi/ahci_vsemiphy.c b/arch/arm/mach-hisi/ahci_vsemiphy.c
deleted file mode 100644
index cd00e52a357e..000000000000
--- a/arch/arm/mach-hisi/ahci_vsemiphy.c
+++ /dev/null
@@ -1,507 +0,0 @@
-#include "ahci_vsemiphy.h"
-#include <linux/delay.h>
-
-#define SERDES_DEBUG_OPEN	(0)
-#define gulDebugOpen		(0)
-
-static void __iomem *sys_ctrl_base, *io_ctrl_base;
-
-static void hi_sata_init_ok(void)
-{
-	HI_IOCTRL1_IOSTAT1_0_UNION tmp_val;
-	printk(" ******sata init start test 000********* ");
-
-	do {
-		tmp_val.uiIoctrl1Iostat10Reg = readl_relaxed(io_ctrl_base + 0x400);
-	}while((tmp_val.strIoctrl1Iostat10RegEach.ChTxMultiRdy != 0xf)
-		||(tmp_val.strIoctrl1Iostat10RegEach.ChRxMultiRdy != 0xf)
-		||(tmp_val.strIoctrl1Iostat10RegEach.ChRxMultiStatus != 0xf)
-		||(tmp_val.strIoctrl1Iostat10RegEach.ChTxPmaStatus != 0xf));
-	printk(" ******sata init start test 111********* ");
-}
-
-static void osSerdesWait(UINT32 ulLoop)
-{
-	while (ulLoop--)
-		;
-}
-
-static void SERDES_REG_WRITE (void __iomem *pRegBase, UINT32 ulRegIndex, UINT32  ulValue)
-{
-#if SERDES_DEBUG_OPEN
-	/*printk( "addr:0x%8x,ulValue:0x%8x\n", pRegBase, ulValue );*/
-	msleep(10);
-
-#endif
-	writel_relaxed(ulValue, pRegBase + ulRegIndex);
-}
-
-#define SERDES_REG_READ(addr, index, data)	((data) = *(volatile unsigned int *)(addr+index))
-
-static void osSerdes2Write(UINT32 ulPage, UINT32 ulType, UINT32 ulOffset, UINT32 ulValue)
-{
-	/*1、:write addr[ioctrl1_base_addr+0x48],data[bit31-27=all 0,*/
-	/*bit26=0,bit25=1,bit24=1,bit23-16=x4,bit15-13=x1,bit12=x2,bit11-0=x3]*/
-	UINT32 ulTemp = 0;
-	UINT32 ulRdata = 0;
-	INT32 ulLoop = 0x100000;
-	UINT32 ulStepChoose = 0;
-	ulTemp = ( ( ulTemp | 0x3000000 ) | ( ulValue << 16 ) | \
-	       ( ulOffset & 0xfff ) | ( ulType << 12 ) | ( ulPage << 13 ) );
-	SERDES_REG_WRITE(io_ctrl_base + 0x48, 0, ulTemp );
-	SERDES_REG_READ(io_ctrl_base + 0x428, 0 ,ulRdata);
-
-	/*2:write addr[ioctrl1_base_addr+0x48],*/
-	/*data[bit31-27=all 0,bit26=0,bit25=0,bit24=1,*/
-	/*bit23-16=x4,bit15-13=x1,bit12=x2,bit11-0=x3]*/
-	SERDES_REG_WRITE(io_ctrl_base + 0x48, 0, ulTemp & 0xFDFFFFFF );
-
-	/*第3步：read addr[ioctrl1_base_addr+0x428], 回读的数据为rdata*/
-	SERDES_REG_READ(io_ctrl_base + 0x428, 0 ,ulRdata);
-#if SERDES_DEBUG_OPEN
-	/*printk( "check HI_IOCONTROL1_REG_BASE_ADDR + 0x428 == 0x100\n" );*/
-	msleep(20);
-#else
-	/*第4步：如果第3步中rdata[bit8==0],回到第3步；如果1ms内，*/
-	/*rdata[bit8==1],走到第5步；如果超过1ms后，直接走到第6步*/
-	while ( --ulLoop )
-	{
-		if ( 0x100 == ( ulRdata & 0x100 ) )
-		{
-			ulStepChoose = 5;
-			break;
-		}
-		else
-		{
-			SERDES_REG_READ(io_ctrl_base + 0x428, 0 ,ulRdata );
-		}
-	}
-#endif
-	if(gulDebugOpen)
-	{
-
-		if ( 5 == ulStepChoose )
-		{
-			printk( "serdes2 read ok page=%x sel=%x offset=%x rdata=%x", ulPage, ulType, ulOffset, ulRdata );
-		}
-	}
-	if ( ulLoop <= 0 )
-	{
-		printk( "serdes2 read outoftime page=%x sel=%x offset=%x value=%x", ulPage, ulType, ulOffset, ulValue );
-	}
-	/*第7步：write addr[ioctrl1_base_addr+0x48],*/
-	/*data[bit31-27=all 0,bit26=1,bit25=0,bit24=1,bit23-16=x4,bit15-13=x1,*/
-	/*bit12=x2,bit11-0=x3]*/
-	ulTemp = 0;
-	ulTemp = ( ulTemp | 0x5000000 ) | ( ulPage << 13 ) | ( ulType << 12 ) | ( ulOffset & 0xfff ) | (ulValue << 16);
-	SERDES_REG_WRITE(io_ctrl_base + 0x48, 0, ulTemp );
-
-	osSerdesWait(1000);
-}
-
-static void osSerdesBitWrite(void __iomem *ulAddr, UINT32 ulOrMask, UINT32 ulAndMask )
-{
-	UINT32 ulValue = 0;
-	SERDES_REG_READ(ulAddr, 0, ulValue);
-	ulValue = ( ulValue | ulOrMask ) & ulAndMask;
-	SERDES_REG_WRITE(ulAddr, 0, ulValue);
-}
-
-static void hi_sata_init_config_all(void)
-{
-	printk("hi_sata_init_config_all begin\n");
-
-	sys_ctrl_base = ioremap(0xe3e00000, 0x100000);
-	if (!sys_ctrl_base) {
-		pr_err("failed to map sysctrl registers in sata serdes\n");
-		return;
-	}
-	io_ctrl_base = ioremap(0xe8002000, 0x1000);
-	if (!io_ctrl_base) {
-		pr_err("failed to map ioctrl registers in sata serdes\n");
-		return;
-	}
-	/* 复位SATA */
-	writel_relaxed(0x30000, sys_ctrl_base + 0x600);
-	//printk("\r\n sata begin reset");
-	/*关闭SATA的tx/rx时钟 */
-	writel_relaxed(0, io_ctrl_base + 0x8);
-
-	/* 关闭SATA的AHB/AXI时钟 */
-	writel_relaxed(0x0, sys_ctrl_base + 0x310);
-	writel_relaxed(0x3, sys_ctrl_base + 0x314);
-	dsb();
-	//printk("\r\n sata begin close AHB/AXI");
-
-	/* serdes2  initialization */
-	//1.    POR
-	osSerdesBitWrite(sys_ctrl_base + 0x0588,0x80000,0xffffffff);
-	//1(1) set multi-mode:
-	osSerdesBitWrite(io_ctrl_base + 0xc,0x1400,0xFFFFF7FF);
-	//1(2) set pcie-mode:
-	//2.    Release POR
-	osSerdesBitWrite(sys_ctrl_base +0x058c,0x80000,0xffffffff);
-
-	//4.	Hard Reset
-	osSerdes2Write(0x0,0x0,0x2,0x2);
-	osSerdes2Write(0x1,0x0,0x2,0x2);
-	osSerdes2Write(0x2,0x0,0x2,0x2);
-	osSerdes2Write(0x3,0x0,0x2,0x2);
-	osSerdes2Write(0x4,0x0,0x2,0x1);
-
-	// 5.	Load Different Data Rate Settings
-
-	osSerdes2Write (0,0,101,201);
-	osSerdes2Write (0,0,102,201);
-	osSerdes2Write (0,0,103,7);
-	osSerdes2Write (0,0,104,7);
-	osSerdes2Write (0,0,105,24);
-	osSerdes2Write (0,0,106,24);
-	osSerdes2Write (0,0,107,1);
-	osSerdes2Write (0,0,108,1);
-	osSerdes2Write (0,0,109,34);
-	osSerdes2Write (0,0,110,5);
-	osSerdes2Write (1,0,101,201);
-	osSerdes2Write (1,0,102,201);
-	osSerdes2Write (1,0,103,7);
-	osSerdes2Write (1,0,104,7);
-	osSerdes2Write (1,0,105,24);
-	osSerdes2Write (1,0,106,24);
-	osSerdes2Write (1,0,107,1);
-	osSerdes2Write (1,0,108,1);
-	osSerdes2Write (1,0,109,34);
-	osSerdes2Write (1,0,110,5);
-	osSerdes2Write (2,0,101,201);
-	osSerdes2Write (2,0,102,201);
-	osSerdes2Write (2,0,103,7);
-	osSerdes2Write (2,0,104,7);
-	osSerdes2Write (2,0,105,24);
-	osSerdes2Write (2,0,106,24);
-	osSerdes2Write (2,0,107,1);
-	osSerdes2Write (2,0,108,1);
-	osSerdes2Write (2,0,109,34);
-	osSerdes2Write (2,0,110,5);
-	osSerdes2Write (3,0,101,201);
-	osSerdes2Write (3,0,102,201);
-	osSerdes2Write (3,0,103,7);
-	osSerdes2Write (3,0,104,7);
-	osSerdes2Write (3,0,105,24);
-	osSerdes2Write (3,0,106,24);
-	osSerdes2Write (3,0,107,1);
-	osSerdes2Write (3,0,108,1);
-	osSerdes2Write (3,0,109,34);
-	osSerdes2Write (3,0,110,5);
-	osSerdes2Write (4,0,101,170);
-	osSerdes2Write (4,0,102,0);
-	osSerdes2Write (4,0,103,69);
-	osSerdes2Write (4,0,104,201);
-	osSerdes2Write (4,0,105,201);
-	osSerdes2Write (4,0,106,7);
-	osSerdes2Write (4,0,107,7);
-	osSerdes2Write (4,0,108,24);
-	osSerdes2Write (4,0,109,24);
-	osSerdes2Write (4,0,110,5);
-	osSerdes2Write (4,0,111,5);
-	osSerdes2Write (4,0,112,16);
-	osSerdes2Write (4,0,113,0);
-	osSerdes2Write (4,0,114,16);
-	osSerdes2Write (4,0,115,0);
-	osSerdes2Write (4,0,116,255);
-	osSerdes2Write (4,0,117,207);
-	osSerdes2Write (4,0,118,247);
-	osSerdes2Write (4,0,119,225);
-	osSerdes2Write (4,0,120,245);
-	osSerdes2Write (4,0,121,253);
-	osSerdes2Write (4,0,122,253);
-	osSerdes2Write (4,0,123,255);
-	osSerdes2Write (4,0,124,255);
-	osSerdes2Write (4,0,125,255);
-	osSerdes2Write (4,0,126,255);
-	osSerdes2Write (4,0,127,227);
-	osSerdes2Write (4,0,128,231);
-	osSerdes2Write (4,0,129,219);
-	osSerdes2Write (4,0,130,245);
-	osSerdes2Write (4,0,131,253);
-	osSerdes2Write (4,0,132,253);
-	osSerdes2Write (4,0,133,245);
-	osSerdes2Write (4,0,134,245);
-	osSerdes2Write (4,0,135,255);
-	osSerdes2Write (4,0,136,255);
-	osSerdes2Write (4,0,137,227);
-	osSerdes2Write (4,0,138,231);
-	osSerdes2Write (4,0,139,219);
-	osSerdes2Write (4,0,140,245);
-	osSerdes2Write (4,0,141,253);
-	osSerdes2Write (4,0,142,253);
-	osSerdes2Write (4,0,143,245);
-	osSerdes2Write (4,0,144,245);
-	osSerdes2Write (4,0,145,255);
-	osSerdes2Write (4,0,146,255);
-	osSerdes2Write (4,0,147,255);
-	osSerdes2Write (4,0,148,245);
-	osSerdes2Write (4,0,149,63);
-	osSerdes2Write (4,0,150,0);
-	osSerdes2Write (4,0,151,50);
-	osSerdes2Write (4,0,152,0);
-	osSerdes2Write (4,0,153,2);
-	osSerdes2Write (4,0,154,1);
-	osSerdes2Write (4,0,155,5);
-	osSerdes2Write (4,0,156,5);
-	osSerdes2Write (4,0,157,4);
-	osSerdes2Write (4,0,158,0);
-	osSerdes2Write (4,0,159,0);
-	osSerdes2Write (4,0,160,8);
-	osSerdes2Write (4,0,161,4);
-	osSerdes2Write (4,0,162,0);
-	osSerdes2Write (4,0,163,0);
-	osSerdes2Write (4,0,164,4);
-	osSerdes2Write (0,0,7,0);
-	osSerdes2Write (1,0,7,0);
-	osSerdes2Write (2,0,7,0);
-	osSerdes2Write (3,0,7,0);
-	osSerdes2Write (4,0,13,16);
-	osSerdes2Write (4,0,48,0);
-	osSerdes2Write (4,0,49,0);
-	osSerdes2Write (4,0,54,0);
-	osSerdes2Write (4,0,55,176);
-	osSerdes2Write (4,0,93,2);
-	osSerdes2Write (4,0,165,2);
-	osSerdes2Write (0,0,41,6);
-	osSerdes2Write (1,0,41,6);
-	osSerdes2Write (2,0,41,6);
-	osSerdes2Write (3,0,41,6);
-	osSerdes2Write (4,0,354,3);
-	osSerdes2Write (4,0,355,58);
-	osSerdes2Write (4,0,356,9);
-	osSerdes2Write (4,0,357,3);
-	osSerdes2Write (4,0,358,62);
-	osSerdes2Write (4,0,359,12);
-	osSerdes2Write (0,0,701,0);
-	osSerdes2Write (1,0,701,0);
-	osSerdes2Write (2,0,701,0);
-	osSerdes2Write (3,0,701,0);
-	/* add something */
-
-	writel_relaxed(0x3099032, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x5099032, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x30E9033, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x50E9033, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x31D9034, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x51D9034, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x3219035, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x5219035, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x3089036, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x5089036, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x30B9037, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x50B9037, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x35A9038, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x55A9038, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x3649039, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x5649039, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x301903A, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x501903A, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x3A3902E, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x5A3902E, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x3539030, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-	writel_relaxed(0x5539030, io_ctrl_base +0x48);
-	readl_relaxed(io_ctrl_base + 0x428);
-	dsb();
-
-	// 6.   Overwrite 由0x4c改成0xdc
-	osSerdes2Write (0x0,0x0,0x55,0xdc);
-	osSerdes2Write (0x0,0x0,0x56,0xe6);
-	osSerdes2Write (0x0,0x0,0x57,0x1f);
-	osSerdes2Write (0x0,0x0,0xe6,0xfe);
-
-	osSerdes2Write (0x1,0x0,0x55,0xdc);
-	osSerdes2Write (0x1,0x0,0x56,0xe6);
-	osSerdes2Write (0x1,0x0,0x57,0x1f);
-	osSerdes2Write (0x1,0x0,0xe6,0xfe);
-
-	osSerdes2Write (0x2,0x0,0x55,0xdc);
-	osSerdes2Write (0x2,0x0,0x56,0xe6);
-	osSerdes2Write (0x2,0x0,0x57,0x1f);
-	osSerdes2Write (0x2,0x0,0xe6,0xfe);
-
-	osSerdes2Write (0x3,0x0,0x55,0xdc);
-	osSerdes2Write (0x3,0x0,0x56,0xe6);
-	osSerdes2Write (0x3,0x0,0x57,0x1f);
-	osSerdes2Write (0x3,0x0,0xe6,0xfe);
-
-	osSerdes2Write (0x4,0x0,0x5f,0xc3);
-
-	// 7.   Set to IDDQ state
-
-	osSerdes2Write (0x0,0x0,0x3,0x1);
-	osSerdes2Write (0x0,0x0,0x4,0x1);
-	osSerdes2Write (0x1,0x0,0x3,0x1);
-	osSerdes2Write (0x1,0x0,0x4,0x1);
-	osSerdes2Write (0x2,0x0,0x3,0x1);
-	osSerdes2Write (0x2,0x0,0x4,0x1);
-	osSerdes2Write (0x3,0x0,0x3,0x1);
-	osSerdes2Write (0x3,0x0,0x4,0x1);
-	osSerdes2Write (0x4,0x0,0x3,0x1);
-
-	// 8.   Release Hard Reset
-
-	osSerdes2Write (0x0,0x0,0x2,0x3);
-	osSerdes2Write (0x1,0x0,0x2,0x3);
-	osSerdes2Write (0x2,0x0,0x2,0x3);
-	osSerdes2Write (0x3,0x0,0x2,0x3);
-	osSerdes2Write (0x4,0x0,0x2,0x3);
-
-	// 9(1). PRBS pattern
-
-	osSerdes2Write (0x4,0x0,0x50,0x1);
-
-	// 10.	RXEQ setting
-
-	osSerdes2Write (0x0,0x0,0x18,0x0);
-	osSerdes2Write (0x0,0x0,0x19,0x0);
-	osSerdes2Write (0x0,0x0,0x1a,0x8);
-	osSerdes2Write (0x0,0x0,0x1b,0x78);
-	osSerdes2Write (0x0,0x0,0x1c,0x0);
-
-	osSerdes2Write (0x1,0x0,0x18,0x0);
-	osSerdes2Write (0x1,0x0,0x19,0x0);
-	osSerdes2Write (0x1,0x0,0x1a,0x8);
-	osSerdes2Write (0x1,0x0,0x1b,0x78);
-	osSerdes2Write (0x1,0x0,0x1c,0x0);
-
-	osSerdes2Write (0x2,0x0,0x18,0x0);
-	osSerdes2Write (0x2,0x0,0x19,0x0);
-	osSerdes2Write (0x2,0x0,0x1a,0x8);
-	osSerdes2Write (0x2,0x0,0x1b,0x78);
-	osSerdes2Write (0x2,0x0,0x1c,0x0);
-
-	osSerdes2Write (0x3,0x0,0x18,0x0);
-	osSerdes2Write (0x3,0x0,0x19,0x0);
-	osSerdes2Write (0x3,0x0,0x1a,0x8);
-	osSerdes2Write (0x3,0x0,0x1b,0x78);
-	osSerdes2Write (0x3,0x0,0x1c,0x0);
-
-	osSerdes2Write (0x4,0x0,0x53,0x2);
-
-	// 11.	TXIODRIVER setting
-
-	osSerdes2Write (0x0,0x0,0x15,0xdf);
-	osSerdes2Write (0x0,0x0,0x16,0x0);
-	osSerdes2Write (0x0,0x0,0x17,0x0);
-	osSerdes2Write (0x1,0x0,0x15,0xdf);
-	osSerdes2Write (0x1,0x0,0x16,0x0);
-	osSerdes2Write (0x1,0x0,0x17,0x0);
-	osSerdes2Write (0x2,0x0,0x15,0xdf);
-	osSerdes2Write (0x2,0x0,0x16,0x0);
-	osSerdes2Write (0x2,0x0,0x17,0x0);
-	osSerdes2Write (0x3,0x0,0x15,0xdf);
-	osSerdes2Write (0x3,0x0,0x16,0x0);
-	osSerdes2Write (0x3,0x0,0x17,0x0);
-
-	/*由于3G问题注释*/
-	#if 0
-	// 12.	Change Data Width to 10 bits
-
-	osSerdes2Write (0x0,0x0,0x5,0x11);
-	osSerdes2Write (0x1,0x0,0x5,0x11);
-	osSerdes2Write (0x2,0x0,0x5,0x11);
-	osSerdes2Write (0x3,0x0,0x5,0x11);
-	// 13.	Change DIVRATE
-	osSerdes2Write (0x0,0x0,0x6,0x11);
-	osSerdes2Write (0x1,0x0,0x6,0x11);
-	osSerdes2Write (0x2,0x0,0x6,0x11);
-	osSerdes2Write (0x3,0x0,0x6,0x11);
-	#endif
-
-	// 15.	Enable PCS TX
-	osSerdes2Write (0x4,0x0,0x8,0x54);
-
-
-	// 16.	Overwrite Enable for Lock2Ref
-	osSerdes2Write (0x0,0x0,0x27,0x2);
-	osSerdes2Write (0x1,0x0,0x27,0x2);
-	osSerdes2Write (0x2,0x0,0x27,0x2);
-	osSerdes2Write (0x3,0x0,0x27,0x2);
-
-	// 17.	Power Up to P0
-
-	osSerdes2Write (0x0,0x0,0x3,0x10);
-	osSerdes2Write (0x0,0x0,0x4,0x10);
-
-	osSerdes2Write (0x1,0x0,0x3,0x10);
-	osSerdes2Write (0x1,0x0,0x4,0x10);
-
-	osSerdes2Write (0x2,0x0,0x3,0x10);
-	osSerdes2Write (0x2,0x0,0x4,0x10);
-
-	osSerdes2Write (0x3,0x0,0x3,0x10);
-	osSerdes2Write (0x3,0x0,0x4,0x10);
-
-	osSerdes2Write (0x4,0x0,0x3,0x10);
-}
-
-static void hi_vsemi_init(void __iomem *mmio)
-{
-	hi_sata_init_config_all();
-
-	msleep(20);
-	hi_sata_init_ok();
-
-	writel_relaxed(0x1, io_ctrl_base +8);
-	writel_relaxed(0x30000, sys_ctrl_base +0x604);
-
-	writel_relaxed(0x3, sys_ctrl_base +0x310);
-	writel_relaxed(0x0, sys_ctrl_base +0x314);
-
-	writel_relaxed(0x1111, io_ctrl_base +0);
-
-#if 0
-	int i, n_ports = 4;
-	unsigned int tmp = 0xa400000;
-
-	printk("----------------------------------------\n");
-	for (i = 0; i < n_ports; i++)
-		writel(tmp, (mmio + 0x100 + i*0x80 + HI_SATA_PORT_PHYCTL));
-#endif
-}
diff --git a/arch/arm/mach-hisi/ahci_vsemiphy.h b/arch/arm/mach-hisi/ahci_vsemiphy.h
deleted file mode 100644
index 6ebd7afbd1fc..000000000000
--- a/arch/arm/mach-hisi/ahci_vsemiphy.h
+++ /dev/null
@@ -1,209 +0,0 @@
-#ifndef __HI_ATA_SYS_VSEMI_H
-#define __HI_ATA_SYS_VSEMI_H
-
-/* sata使用的系统和IOCONTROL寄存器地址定义 */
-
-
-#define HI_SATA_PORT_PHYCTL     0x74
-#define UINT32 unsigned int
-#define INT32 signed int
-
-
-/* 寄存器 数据结构定义 */
-/* serdes2的复位请求寄存器 */
-typedef struct tagHI_SC_SERDES_RESET_REQ1_REG_S {
-    unsigned int  Sds1SynthtRst:1;            /* Serdes1的 multi hard synth的软复位位 */
-    unsigned int  Sds1MltRst:4;               /* Serdes1的multi hard 复位位，每一位代表一个端口*/
-    unsigned int  Sds1PipRst:4;               /* Serdes1的PIP line 复位位，每一位代表一个端口 */
-    unsigned int  Sds1rst:1;                  /* Serdes1的端口复位位 */
-    unsigned int  Sds2SynthtRst:1;            /* Serdes2的 multi hard synth的软复位位 */
-    unsigned int  Sds2MltRst:4;               /* Serdes2的multi hard 复位位，每一位代表一个端口*/
-    unsigned int  Sds2PipRst:4;               /* Serdes2的PIP line 复位位，每一位代表一个端口 */
-    unsigned int  Sds2rst:1;                  /* Serdes2的端口复位位 */
-    unsigned int  Reserve:14;                 /* 保留位 */
-} HI_SC_SERDES_RESET_REQ1_REG_STRU;
-
-typedef union tagHI_SC_SERDES_RESET_REQ1_REG_U {
-    unsigned int uiScSdsRstReq1Reg;
-    HI_SC_SERDES_RESET_REQ1_REG_STRU strScSdsRstReq1RegEach;
-} HI_SC_SERDES_RESET_REQ1_REG_UNION;
-
-/* SERDES2去复位请求寄存器 */
-typedef struct tagHI_SC_SERDES_RESET_DREQ1_REG_S {
-    unsigned int  Sds1SynthtRst:1;            /* Serdes1的 multi hard synth的软复位位 */
-    unsigned int  Sds1MltRst:4;               /* Serdes1的multi hard 复位位，每一位代表一个端口*/
-    unsigned int  Sds1PipRst:4;               /* Serdes1的PIP line 复位位，每一位代表一个端口 */
-    unsigned int  Sds1rst:1;                  /* Serdes1的端口复位位 */
-    unsigned int  Sds2SynthtRst:1;            /* Serdes2的 multi hard synth的软复位位 */
-    unsigned int  Sds2MltRst:4;               /* Serdes2的multi hard 复位位，每一位代表一个端口*/
-    unsigned int  Sds2PipRst:4;               /* Serdes2的PIP line 复位位，每一位代表一个端口 */
-    unsigned int  Sds2rst:1;                  /* Serdes2的端口复位位 */
-    unsigned int  Reserve:14;                 /* 保留位 */
-} HI_SC_SERDES_RESET_DREQ1_REG_STRU;
-
-typedef union tagHI_SC_SERDES_RESET_DREQ1_REG_U {
-    unsigned int uiScSdsRstDreq1Reg;
-    HI_SC_SERDES_RESET_DREQ1_REG_STRU strScSdsRstDreq1RegEach;
-} HI_SC_SERDES_RESET_DREQ1_REG_UNION;
-
-/* IOCTRL1_0寄存器定义，配置SERDES工作模式 */
-typedef struct tagHI_IOCTRL1_0_REG_S {
-    unsigned int  L0Sel:4;                  /* Serdes2的Lane0的功能选择:0x0表示Gmac3;0x1表示SATA；0x2表示sRIO */
-    unsigned int  L1Sel:4;                  /* Serdes2的Lane1的功能选择:0x0表示Gmac3;0x1表示SATA；0x2表示sRIO*/
-    unsigned int  L2Sel:4;                  /* Serdes2的Lane2的功能选择:0x0表示Gmac3;0x1表示SATA；0x2表示sRIO */
-    unsigned int  L3Sel:4;                  /* Serdes2的Lane3的功能选择:0x0表示Gmac3;0x1表示SATA；0x2表示sRIO */
-    unsigned int  Reserve:16;               /* 保留位 */
-} HI_IOCTRL1_0_REG_STRU;
-
-typedef union tagHI_IOCTRL1_0_REG_U {
-    unsigned int uiIoctrl10Reg;
-    HI_IOCTRL1_0_REG_STRU struiIoctrl10RegEach;
-} HI_IOCTRL1_0_REG_UNION;
-
-
-/* 寄存器 数据结构定义 */
-typedef struct tagHI_IOCTRL1_2_REG_S {
-    unsigned int  ClkEn:6;                  /* SATA接收/发送时钟使能:0表示不使能，1表示使能 */
-    unsigned int  Reserve:26;               /* 保留位 */
-} HI_IOCTRL1_2_REG_STRU;
-
-typedef union tagHI_IOCTRL1_2_REG_U {
-    unsigned int uiIoctrl12Reg;
-    HI_IOCTRL1_2_REG_STRU struiIoctrl12RegEach;
-} HI_IOCTRL1_2_REG_UNION;
-
-
-/* 寄存器 数据结构定义 */
-typedef struct tagHI_IOCTRL0_4_REG_S {
-    unsigned int  RxTxChPowerCtl:8;  /* 通道发送/接收disable/power-down控制 */
-    unsigned int  RxDatawidthl0:3;   /* Ch0 发送数据位宽选择 000:8bit;001:10bit;010:16bit;011:20bit;100:32bit;101:40bit */
-    unsigned int  RxDatawidthl1:3;   /* Ch1 发送数据位宽选择 000:8bit;001:10bit;010:16bit;011:20bit;100:32bit;101:40bit */
-    unsigned int  RxDatawidthl2:3;   /* Ch2 发送数据位宽选择 000:8bit;001:10bit;010:16bit;011:20bit;100:32bit;101:40bit */
-    unsigned int  RxDatawidthl3:3;   /* Ch3 发送数据位宽选择 000:8bit;001:10bit;010:16bit;011:20bit;100:32bit;101:40bit */
-    unsigned int  TxDatawidthl0:3;   /* Ch0 发送数据位宽选择 000:8bit;001:10bit;010:16bit;011:20bit;100:32bit;101:40bit */
-    unsigned int  TxDatawidthl1:3;   /* Ch1 发送数据位宽选择 000:8bit;001:10bit;010:16bit;011:20bit;100:32bit;101:40bit */
-    unsigned int  TxDatawidthl2:3;   /* Ch2 发送数据位宽选择 000:8bit;001:10bit;010:16bit;011:20bit;100:32bit;101:40bit */
-    unsigned int  TxDatawidthl3:3;   /* Ch3 发送数据位宽选择 000:8bit;001:10bit;010:16bit;011:20bit;100:32bit;101:40bit */
-} HI_IOCTRL0_4_REG_STRU;
-
-typedef union tagHI_IOCTRL0_4_REG_U {
-    unsigned int uiIoctrl04Reg;
-    HI_IOCTRL0_4_REG_STRU struiIoctrl04RegEach;
-} HI_IOCTRL0_4_REG_UNION;
-
-
-typedef struct tagHI_IOCTRL0_5_REG_S {
-    unsigned int  RxRatel0:3;    /* ch0 PMA接收速率选择 */
-    unsigned int  RxRatel1:3;    /* ch1 PMA接收速率选择 */
-    unsigned int  RxRatel2:3;    /* ch2 PMA接收速率选择 */
-    unsigned int  RxRatel3:3;    /* ch3 PMA接收速率选择 */
-    unsigned int  TxRatel0:3;    /* ch0 PMA发送速率选择*/
-    unsigned int  TxRatel1:3;    /* ch1 PMA发送速率选择 */
-    unsigned int  TxRatel2:3;    /* ch2 PMA发送速率选择 */
-    unsigned int  TxRatel3:3;    /* ch3 PMA发送速率选择 */
-    unsigned int  Pstatel0:2;    /* ch0 power down状态控制 11: Coma Power State;10:Slumber;01:Doze;00:Wake*/
-    unsigned int  Pstatel1:2;    /* ch1 power down状态控制 11: Coma Power State;10:Slumber;01:Doze;00:Wake*/
-    unsigned int  Pstatel2:2;    /* ch2 power down状态控制 11: Coma Power State;10:Slumber;01:Doze;00:Wake*/
-    unsigned int  Pstatel3:2;    /* ch3 power down状态控制 11: Coma Power State;10:Slumber;01:Doze;00:Wake*/
-} HI_IOCTRL0_5_REG_STRU;
-
-typedef union tagHI_IOCTRL0_5_REG_U {
-    unsigned int uiIoctrl05Reg;
-    HI_IOCTRL0_5_REG_STRU struiIoctrl05RegEach;
-} HI_IOCTRL0_5_REG_UNION;
-
-typedef struct tagHI_IOCTRL1_12_REG_S {
-    unsigned int  RxLockEn:4;              /* PCS CDR锁定控制使能 */
-    unsigned int  RxLock:4;                /* PCS CDR锁定控制   */
-    unsigned int  TxampEn:4;               /* 发送摆幅配置使能，每一位代表一个ch*/
-    unsigned int  Txampl0:3;               /* CH0发送幅度控制 */
-    unsigned int  Txampl1:3;               /* CH1发送幅度控制 */
-    unsigned int  Txampl2:3;               /* CH2发送幅度控制 */
-    unsigned int  Txampl3:3;               /* CH3发送幅度控制 */
-    unsigned int  TxBeacon:4;              /* CH3 Beacon发送使能，每一位代表一个ch；0:禁止;1:使能 */
-    unsigned int  TxDtctRxReq:4;           /* 发送接收器检测请求，每一位代表一个通道 */
-} HI_IOCTRL1_12_REG_STRU;
-
-typedef union tagHI_IOCTRL1_12_REG_U {
-    unsigned int uiIoctrl112Reg;
-    HI_IOCTRL1_12_REG_STRU struiIoctrl112RegEach;
-} HI_IOCTRL1_12_REG_UNION;
-
-/* 定义 IOCTRL1_18寄存器 */
-typedef struct tagHI_IOCTRL1_18_REG_S {
-    unsigned int  IctlMemAddr:12;            /* memory地址 */
-    unsigned int  IdatPma:1;                 /* memory的PMA */
-    unsigned int  IdatPage:3;                /* memory写地址 */
-    unsigned int  IdatMemWdat:8;             /* memory写数据 */
-    unsigned int  IctlMemWr:1;               /* memory读写标志 */
-    unsigned int  IctlMemReq:1;              /* memory请求 */
-    unsigned int  ClrOctlMemAck:1;           /* 清除octl_mem_ack响应 */
-    unsigned int  Reserve:5;                 /* 保留位 */
-} HI_IOCTRL1_18_REG_STRU;
-
-typedef union tagHI_IOCTRL1_18_REG_U {
-    unsigned int uiIoctrl118Reg;
-    HI_IOCTRL1_18_REG_STRU struiIoctrl118RegEach;
-} HI_IOCTRL1_18_REG_UNION;
-
-
-typedef struct tagHI_SC_USB_RESET_REQ_REG_S {
-    unsigned int  Reserve1:16;               /* 保留位 */
-    unsigned int  SataSftRst:2;             /* SATA软复位:0x3表示软复位；0x0表示没有软复位 */
-    unsigned int  Reserve0:14;               /* 保留位 */
-} HI_SC_USB_RESET_REQ_STRU;
-
-typedef union tagHI_SC_USB_RESET_REQ_U {
-    unsigned int uiScUsbRstReqReg;
-    HI_SC_USB_RESET_REQ_STRU strScUsbRstReqEach;
-} HI_SC_USB_RESET_REQ_UNION;
-
-typedef struct tagHI_SC_SATA_CLK_EN_REG_S {
-    unsigned int  SataClkEn:2;             /* SATA时钟复位使能位 */
-    unsigned int  Reserve0:30;               /* 保留位 */
-} HI_SC_SATA_CLK_EN_STRU;
-
-typedef union tagHI_SC_SATA_CLK_EN_U {
-    unsigned int uiScSataClkEnReg;
-    HI_SC_SATA_CLK_EN_STRU strScSataClkEnRegEach;
-} HI_SC_SATA_CLK_EN_UNION;
-
-typedef struct tagHI_SC_SATA_CLK_DIS_REG_S {
-    unsigned int  SataClkDis:2;             /* SATA时钟禁止位 */
-    unsigned int  Reserve0:30;               /* 保留位 */
-} HI_SC_SATA_CLK_DIS_STRU;
-
-typedef union tagHI_SC_SATA_CLK_DIS_U {
-    unsigned int uiScSataClkDisReg;
-    HI_SC_SATA_CLK_DIS_STRU strScSataClkDisRegEach;
-} HI_SC_SATA_CLK_DIS_UNION;
-
-typedef struct tagHI_IOCTRL1_IOSTAT1_0_S {
-    unsigned int  ChRxMultiStatus:4;          /* CH 接收通道状态跳转请求响应指示  */
-    unsigned int  ChRxMultiRdy:4;             /* CH 接收通道Ready指示   */
-    unsigned int  ChTxMultiRdy:4;             /* CH 发送通道Ready指示  */
-    unsigned int  ChTxPmaStatus:4;            /* CH 发送通道状态跳转请求响应指示  */
-    unsigned int  ChRxSgnlDetc:4;             /* CH 接收数据检测状态指示 */
-    unsigned int  ChRxBistDone:4;             /* CH RX BIST完成指示，高有效*/
-    unsigned int  ChRxBistLocked:4;           /* CH RX BIST 已锁定指示  */
-    unsigned int  ChRxBistOverFlow:4;         /* CH RX BIST error count 上溢指示,每一位代表一个通道 */
-} HI_IOCTRL1_IOSTAT1_0_STRU;
-
-typedef union tagHI_IOCTRL1_IOSTAT1_0_U {
-    unsigned int uiIoctrl1Iostat10Reg;
-    HI_IOCTRL1_IOSTAT1_0_STRU strIoctrl1Iostat10RegEach;
-} HI_IOCTRL1_IOSTAT1_0_UNION;
-
-
-typedef struct tagHI_SC_USB_RESET_DREQ_REG_S {
-    unsigned int  Reserve1:16;               /* 保留位 */
-    unsigned int  SataDereset:2;             /* SATA 去软复位 */
-    unsigned int  Reserve0:14;               /* 保留位 */
-} HI_SC_USB_RESET_DREQ_STRU;
-
-typedef union tagHI_SC_USB_RESET_DREQ_U {
-    unsigned int uiScUsbRstDreqReg;
-    HI_SC_USB_RESET_DREQ_STRU strScUsbRstDreqRegEach;
-} HI_SC_USB_RESET_DREQ_UNION;
-
-#endif
diff --git a/arch/arm/mach-hisi/hip04.c b/arch/arm/mach-hisi/hip04.c
index 3997db38fcb4..bdb3f798c875 100644
--- a/arch/arm/mach-hisi/hip04.c
+++ b/arch/arm/mach-hisi/hip04.c
@@ -11,7 +11,6 @@
  * published by the Free Software Foundation.
 */
 
-#include <linux/ahci_platform.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
@@ -28,8 +27,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "ahci_vsemiphy.c"
-
 #define BOOTWRAPPER_PHYS		0x10c00000
 #define BOOTWRAPPER_MAGIC		0xa5a5a5a5
 #define BOOTWRAPPER_SIZE		0x00010000
@@ -300,29 +297,10 @@ static const char *hip04_compat[] __initconst = {
 	NULL,
 };
 
-#define HIP04_SATA_BASE		(0xea000000)
-
-static int sata_vsemiphy_init(struct device *dev, void __iomem *addr)
-{
-	hi_vsemi_init(addr);
-	return 0;
-}
-
-static struct ahci_platform_data hip04_sata_pdata = {
-	.init	= sata_vsemiphy_init,
-};
-
-static struct of_dev_auxdata hip04_auxdata_lookup[] __initdata = {
-	OF_DEV_AUXDATA("hisilicon,hisi-ahci", HIP04_SATA_BASE,
-			NULL, &hip04_sata_pdata),
-	{},
-};
-
 static void __init hip04_init_machine(void)
 {
 	unsigned int data, mask;
-	of_platform_populate(NULL, of_default_bus_match_table,
-			hip04_auxdata_lookup, NULL);
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
 	gb3 = ioremap(0xe4003000, 0x1000);
 	if (!gb3) {