blob: 019966b42948fa6e357560fe3176a6e05f892b45 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
|
/*
* Arm SCP/MCP Software
* Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef RDN1E1_SDS_H
#define RDN1E1_SDS_H
#include <mod_sds.h>
/*
* Structure identifiers.
*/
enum rdn1e1_sds_struct_id {
RDN1E1_SDS_CPU_INFO = 1 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS),
RDN1E1_SDS_FIRMWARE_VERSION = 2 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS),
RDN1E1_SDS_PLATFORM_ID = 3 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS),
RDN1E1_SDS_RESET_SYNDROME = 4 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS),
RDN1E1_SDS_FEATURE_AVAILABILITY =
5 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS),
RDN1E1_SDS_CPU_BOOTCTR = 6 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS),
RDN1E1_SDS_CPU_FLAGS = 7 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS),
};
/*
* Structure sizes.
*/
#define RDN1E1_SDS_CPU_INFO_SIZE 4
#define RDN1E1_SDS_FIRMWARE_VERSION_SIZE 4
#define RDN1E1_SDS_PLATFORM_ID_SIZE 8
#define RDN1E1_SDS_RESET_SYNDROME_SIZE 4
#define RDN1E1_SDS_FEATURE_AVAILABILITY_SIZE 4
#define RDN1E1_SDS_CPU_BOOTCTR_SIZE 256
#define RDN1E1_SDS_CPU_FLAGS_SIZE 256
/*
* Field masks and offsets for the RDN1E1_SDS_AP_CPU_INFO structure.
*/
#define RDN1E1_SDS_CPU_INFO_PRIMARY_MASK 0xFFFFFFFF
#define RDN1E1_SDS_CPU_INFO_PRIMARY_POS 0
/*
* Platform information
*/
struct rdn1e1_sds_platid {
/* Subsystem part number */
uint32_t platform_identifier;
/* Platform type information */
uint32_t platform_type_identifier;
};
/*
* Field masks and offsets for the RDN1E1_SDS_FEATURE_AVAILABILITY structure.
*/
#define RDN1E1_SDS_FEATURE_FIRMWARE_MASK 0x1
#define RDN1E1_SDS_FEATURE_DMC_MASK 0x2
#define RDN1E1_SDS_FEATURE_MESSAGING_MASK 0x4
#define RDN1E1_SDS_FEATURE_FIRMWARE_POS 0
#define RDN1E1_SDS_FEATURE_DMC_POS 1
#define RDN1E1_SDS_FEATURE_MESSAGING_POS 2
#endif /* RDN1E1_SDS_H */
|
