From 1c77f89ab929c4876d040cbb4e5c7a2658970e6e Mon Sep 17 00:00:00 2001 From: Vijayenthiran Subramaniam Date: Tue, 24 Nov 2020 22:17:05 +0530 Subject: product/rddanielxlr: fix pik_clock's modulator_reg of cluster 1 Cluster 1's modulator register is pointing to CLUSTER_PIK_PTR(0) which corresponds to Cluster 0's PIK register space instead of Cluster 1's. Fix this by pointing to CLUSTER_PIK_PTR(1). Fixes https://github.com/ARM-software/SCP-firmware/issues/342 Signed-off-by: Vijayenthiran Subramaniam Change-Id: I8fe1493c594b25a7993fb73af95729bfc44287ba --- product/rddanielxlr/scp_ramfw/config_pik_clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/product/rddanielxlr/scp_ramfw/config_pik_clock.c b/product/rddanielxlr/scp_ramfw/config_pik_clock.c index c4d1dca1..9a4e3873 100644 --- a/product/rddanielxlr/scp_ramfw/config_pik_clock.c +++ b/product/rddanielxlr/scp_ramfw/config_pik_clock.c @@ -115,7 +115,7 @@ static const struct fwk_element pik_clock_element_table[] = { .is_group_member = true, .control_reg = &CLUSTER_PIK_PTR(1)->CORECLK[0].CTRL, .divext_reg = &CLUSTER_PIK_PTR(1)->CORECLK[0].DIV, - .modulator_reg = &CLUSTER_PIK_PTR(0)->CORECLK[0].MOD, + .modulator_reg = &CLUSTER_PIK_PTR(1)->CORECLK[0].MOD, .rate_table = rate_table_cpu_group, .rate_count = FWK_ARRAY_SIZE(rate_table_cpu_group), }), -- cgit v1.2.3