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Cluster 1's modulator register is pointing to CLUSTER_PIK_PTR(0) which
corresponds to Cluster 0's PIK register space instead of Cluster 1's.
Fix this by pointing to CLUSTER_PIK_PTR(1).
Fixes https://github.com/ARM-software/SCP-firmware/issues/342
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I8fe1493c594b25a7993fb73af95729bfc44287ba
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Cluster 1's modulator register is pointing to CLUSTER_PIK_PTR(0) which
corresponds to Cluster 0's PIK register space instead of Cluster 1's.
Fix this by pointing to CLUSTER_PIK_PTR(1).
Fixes https://github.com/ARM-software/SCP-firmware/issues/342
Change-Id: Ie2feb3b1e7fa545a541811d5286038e025e9fe4a
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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Add the product.mk file for RD-Evans platform and make it available to
the scp build system as a product.
Change-Id: Ic11252bff3cc1755abe36cdf21d989b1074c6c29
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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MCP ROM and RAM firmware, does not provide any specific functionality
yet. MCP ROM firmware loads the MCP RAM firmware which then executes
a WFI to enter idle state.
Change-Id: I6301601d9b3b60b5dc4e612c35ae5c765202b851
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Add linker script and makefile to support the build of SCP RAM firmware.
Change-Id: I0df11f104a28c12fe72880178683a1bacd963ae5
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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The system power driver manages the SYSTOP power domain. Provide the
details such as the base adresses of System PPU's and the SOC IRQ's for
the same.
Change-Id: I0097f0a8be671708f5cf05b2276ccbbc57a69b5a
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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The system module performs the function of initializing the SYSTOP
domain, turning on the primary core, setting up of the SCMI services
and SDS messaging stack.
Change-Id: I9a115344c1f162f3518af9a930d0e29978e82d84
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Provide the configuration data for scmi system power module to manage
system states.
Change-Id: Ib19f0e750a31b876f3e5f321014547ca43e5e668
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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There is no specific configuration data to be supplied to the scmi
power domain module.
Change-Id: Icbd8aca4deb0b763de47dd31216de03ea0502d11
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Provide configuration data to enable support request for PSCI services
from the AP core to the SCMI platform for RD-Evans pltform. At present
only the PSCI service for power management is supported.
Change-Id: I5923b7c3b669b1684c15de57debf25e6e09d77fb
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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SDS module is used to pass runtime data from SCP firmware to the
firmware on AP core using shared memory. Provide the base address
and size for the same and also the payloads to be passed.
Change-Id: I1682e325f19e8d94932012d9588c927427c79a6e
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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AP context module is used to zero out the shared memory region used by
SCP and AP on every initializaion or interconnect reset. Provide the
base address and size of the shared memory region and also the clock id
of the interconnect to subscribe to.
Change-Id: I7372af0cdbff7ea49f6b8d4979343ad3fbd6356a
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Provide the details of the MHUv2 channels used for messaging from the
application cores to the SCP and add it to interrupt map.
Change-Id: Icdc48325ba67d5131f2f99fa4fdd0555d079685a
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Provide the configuration data for timer hal which includes the id for
the timer element and the IRQ number.
Change-Id: I8b4cacae5f2d717aef83dd88295fa060f5e547e0
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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The configuration data for generic timer driver includes the base
adresses of timer register, counter register and control register along
with the initial frequency and the id of clock device on which the timer
depends.
Change-Id: I4801c2f4a645d9dd3770f6c6290ba19492d84396
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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CMN-700 is the interconnect used in RD-Evans platform. Add configuration
data such as base address, memory region map, SNF table and mesh sizes.
Change-Id: If81d6d6121d98bc671d86f77be869f9235c8ba06
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Provide the configuration data for clock hal which includes the clock
driver id, api id and the power domain source.
Change-Id: If26f5ba081fb774dede88e6d096c23c8006f3901
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Provide the config data such as ppu base addresses for the ppu driver
and config data for power domain hal to construct the power domain tree.
Change-Id: I25b14c6a339b1c462a5db39e2a09ef562f59b72f
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Functions to obtain the platform topology information such as core
count, cluster count help in adding configuration data dynamically and
can be used by modules to add the configuration data dynamically.
Change-Id: Iadb7c7bb77c290517e2b596b71d3a3fed3d3c927
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Provide setup data i.e source pll, member table and rate table for css
clocks.
Change-Id: I364db8652a29c5f9a9567d0844ba1de74025d9b8
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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The configuration data for PIK clock devices includes the base address
of control registers and the rate table with initial rate.
Change-Id: Iec4dcdf90770ac5ac6991997f0c5b4969a3646dd
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Add the base address of the control registers and the initial rates for
the PLL hardware in RD-Evans.
Change-Id: Id685d2c68d1bc05112ba5e453301b7faf1c5bcdc
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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System PIK includes registers for clock control of System PPU,
CMN Kampos Interconnect and DMC. Add the register space declaration
and base address from element management peripheral space.
Change-Id: Ie251919d4ce9dca822400efeb905f7b7d1291800
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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CPU PIK includes registers for configuration and clock control for AP
cores. Add the register space declaration and the base address macro for
the CPU PIK.
Change-Id: I5b0e76d310579563af5c2b536d3323c4c1c1d24c
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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SCP PIK includes registers for various system configuration and status.
SCP PIK is first one to come out of reset and it generates all the reset
conrols for SCP. Add the register space declaration for SCP PIK and the
subsequent base address from element management peripheral space.
Change-Id: Ic4c61d07875092d045b1e97b01b74811ffb1500b
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Add platform specific definitions for callback functions for cmsis rtx.
Change-Id: Iaaa9b3e6887696932d23ed6a42b2f224819f7a54
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Add configuration data for MPU module. The SCP RAMs, trusted RAM and
non-trusted memory regions are specified.
Change-Id: Ie1d55ee59b8dfe4308747f9cb35fb46f16b63cdf
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Add the linker script and makefile to support the build of the SCP ROM
firmware.
Change-Id: Ic2f19b7d6afacc231206c19a58c590d54571e1dc
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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The bootloader module is used to load the SCP RAM firmware from the NOR
flash to SCP RAM. Provide the base address and size of the firmware
image to be loaded from and the base address of the location to which
the firmware is loaded to.
Change-Id: Ia7be81442ef67225f7a85182a96a3feabcae3492
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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The clock module config data is empty for scp rom firmware image as
this structure is required only to resolve build time dependencies
across modules.
Change-Id: I48efdaa55f53b5c74f9f451e1b49a41291822ddc
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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PL011 controller is used as a console port for debug and log messages.
Add configuration data of this controller including base address and
input clock frequency for the PL011 module to use.
Change-Id: I125920a32114c81d213430c37c1550b526e0a32c
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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System Info Module provides API to obtain platform data in
platform independent manner. Provide configuration data for the same.
Change-Id: I1e4dfac7639d4239343bf4d9cb77a7f4d166ef57
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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SID peripheral on this platform provides information about the platform
ID and config ID. So add the configuration data for SID module. The
base address of the SID register block is provided for the SID module
to read out the IDs from the SID registers.
Change-Id: Ie6fa5a4c1c4694818bfad82d19406ab7710f2f1d
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Add framework header file which sets the framework's standard input and
output handling entity as PL011 module.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I639f850c310d5efe76e1f83e71e8b24bdb5c2971
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Add initial support for CMN-700 interconnect controller. This include
discovery of mesh, configuring SAM tables, programming the nodes and
sufficient support for single chip operation. When compared to previous
CMN generations (such as CMN-600 or CMN-650), CMN-700 supports
crosspoints (XP) with more than 2 ports and is compliant with CXL
protocol standard.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: Ibee8ff2d1711b20b5793d36b8f9f4ee06367a266
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Commit 78e405e ("build: allow platforms to choose the c library to
build with") switched the RD platforms to use standard newlib library
instead of newlib-nano for SCP RAM firmware. With the latest GCC
toolchain (GCC-8.3 and GCC-9 2020 q2 update), SCP RAM firmware boot
hangs rddanielxlr platform when build with LOG_LEVEL set to trace. This
problem is not observed with the older version of toolchain
(GCC-5.4 2016 q3). Until this problem is investigated, switch
rddanielxlr's RAM firmware to use newlib-nano library.
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
Change-Id: I9fd5ffc292cd7d4d14c99be0465cd45e96b226aa
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Migrate from using mscp_rom module to isys_rom module as the boot ROM
for both SCP and MCP controllers. As there is no support yet for MCP
RAM firmware, the config data for the bootloader module is set to NULL.
The isys_rom module ensures that the MCP processor is held in a idle
state.
Change-Id: Icfe6f6a0d01c49f63d432d188e9b5c98a492fd47
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Migrate from using mscp_rom module to isys_rom module as the boot ROM
for both SCP and MCP controllers. As there is no support yet for MCP
RAM firmware, the config data for the bootloader module is set to NULL.
The isys_rom module ensures that the MCP processor is held in a idle
state.
Change-Id: I1cf16ec1f5447a6771b55783b3c3be9b045c6b5d
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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Allow MCP ROM firmware to use the isys_rom module in order to load
the RAM firmware. As there is no support yet for MCP RAM firmware,
the config data for the bootloader module is set to NULL. The
isys_rom module ensures that the MCP processor is held in a idle
state
Change-Id: I8807d3020317c4253c9a8ab9a6c89fe1d6e7413b
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
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Allow MCP ROM firmware to use the isys_rom module in order to load
the RAM firmware. As there is no support yet for MCP RAM firmware,
the config data for the bootloader module is set to NULL. The
isys_rom module ensures that the MCP processor is held in a idle
state
Change-Id: Ieb5455587afe5ff7897ac16a95d878dd299b1e18
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
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On failure to boot from RAM firmware, ensure that the processor is
held in a idle state.
Change-Id: I5376c18062c54a17b577266cafda099218aefee4
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
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Prior to using the module config data, ensure that there is a valid
config data to use.
Change-Id: I899fe4b53b076f354f5215a723cbb2d1d1bd0b68
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
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The PID controller implements give of the eight PCID registers. So
remove a check on all the eight PCID registers.
Change-Id: I523243dcf8509e58afde4947106d6307b43dbd43
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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This patch creates a new type called fwk_optional_id_t which can
be left into undefined. This allows any non-mandatory configuration
to be left unassigned reducing code-size and improving upgradability.
Change-Id: I28243b6a9394ce7c476f6574c45e6fc55a9fd6c6
Signed-off-by: Leandro Belli <leandro.belli@arm.com>
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This patch impelemnts some minor optimisations for the
fwk_thread_put_event critical code path.
Signed-off-by: Jim Quigley <jim.quigley@arm.com>
Change-Id: I0ccf2e9e95be2059242786c735ecb597bd4b47e7
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The firmware build currently uses the newlib-nano as standard C library
for optimized code size. Newlib-nano does not have some features that
were added after C89 [1]. For example, it does not have 64-bit integer
support in format IO due to which it is not possible to print a 64-bit
integer. GCC toolchain by default supports standard newlib C library.
This patch makes newlib/nosys.specs as the default library while
building the firmware and introduce build flag
`BS_FIRMWARE_USE_NEWLIB_NANO_SPECS` to allow the platform to choose the
newlib-nano library over the default library. Except for Arm's
infrastructure reference platforms (SGI575, RDN1E1, RD-Daniel,
RD-Daniel-XLR and N1SDP), all other platforms are made to use
newlib-nano library to generate optimized code size.
[1]: https://community.arm.com/developer/ip-products/system/b/embedded-blog/posts/shrink-your-mcu-code-size-with-gcc-arm-embedded-4-7
Change-Id: Ia2ce178827f7661ae770c1edc4d534f4330a42cd
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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In this change , when resource permission module is disabled if a
protocol is listed in the disabled protocols for PSCI agent then
this protocol couldn't be accessed by PSCI agent and SCMI_DENIED_ERROR
is returned.
Change-Id: Id35ba35628eabd9b7bca7bb48b7016f60155dcec
Signed-off-by: Ahmed Gadallah <ahmed.gadallah@arm.com>
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This patch adds a new tag exit_unexpected to remove multiple
calls to fwk_unexpected function. This allows to reduce and
simplify code.
Change-Id: I004e22b73506a59517cfd911b4fea3be4178cf6f
Signed-off-by: Leandro Belli <leandro.belli@arm.com>
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This patch includes a callback function for SENSOR_TRIP_POINT_NOTIFY
and checks sensor-id parameter. It adds a notification api for sensor
trip point.
To enable this feature the build flag BUILD_HAS_SCMI_SENSOR_EVENTS
and BUILD_HAS_SCMI_NOTIFICATIONS should be set.
Change-Id: I14ba2edf2d2e5430f920966d46e3f94456f9dc2c
Signed-off-by: Leandro Belli <leandro.belli@arm.com>
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This patch includes a callback function for SENSOR_TRIP_POINT_CONFIG
and checks sensor-id parameter. It allows setting a trip point value
with all the settings enabled. Every sensor should specify the
mod_sensor_trip_point_info struct inside the sensor configuration if
needed.
To enable this feature the build flag BUILD_HAS_SCMI_SENSOR_EVENTS
should be set.
Change-Id: I4acbc74ef284bd53d60e0bcd4c4e992921f2f5a4
Signed-off-by: Leandro Belli <leandro.belli@arm.com>
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