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-rw-r--r--product/rdn2/include/clock_soc.h26
-rw-r--r--product/rdn2/include/scp_mmap.h1
-rw-r--r--product/rdn2/include/scp_soc_mmap.h23
-rw-r--r--product/rdn2/scp_ramfw/config_system_pll.c260
4 files changed, 310 insertions, 0 deletions
diff --git a/product/rdn2/include/clock_soc.h b/product/rdn2/include/clock_soc.h
index 6f7848c2..c1112d3c 100644
--- a/product/rdn2/include/clock_soc.h
+++ b/product/rdn2/include/clock_soc.h
@@ -12,4 +12,30 @@
#define CLOCK_RATE_REFCLK (100UL * FWK_MHZ)
+/*
+ * PLL clock indexes.
+ */
+enum clock_pll_idx {
+ CLOCK_PLL_IDX_CPU0,
+ CLOCK_PLL_IDX_CPU1,
+ CLOCK_PLL_IDX_CPU2,
+ CLOCK_PLL_IDX_CPU3,
+ CLOCK_PLL_IDX_CPU4,
+ CLOCK_PLL_IDX_CPU5,
+ CLOCK_PLL_IDX_CPU6,
+ CLOCK_PLL_IDX_CPU7,
+ CLOCK_PLL_IDX_CPU8,
+ CLOCK_PLL_IDX_CPU9,
+ CLOCK_PLL_IDX_CPU10,
+ CLOCK_PLL_IDX_CPU11,
+ CLOCK_PLL_IDX_CPU12,
+ CLOCK_PLL_IDX_CPU13,
+ CLOCK_PLL_IDX_CPU14,
+ CLOCK_PLL_IDX_CPU15,
+ CLOCK_PLL_IDX_SYS,
+ CLOCK_PLL_IDX_DMC,
+ CLOCK_PLL_IDX_INTERCONNECT,
+ CLOCK_PLL_IDX_COUNT
+};
+
#endif /* CLOCK_SOC_H */
diff --git a/product/rdn2/include/scp_mmap.h b/product/rdn2/include/scp_mmap.h
index 3bf67a15..71f75925 100644
--- a/product/rdn2/include/scp_mmap.h
+++ b/product/rdn2/include/scp_mmap.h
@@ -12,6 +12,7 @@
#define SCP_ITC_RAM_BASE 0x00800000
#define SCP_SOC_EXPANSION1_BASE 0x01000000
#define SCP_DTC_RAM_BASE 0x20000000
+#define SCP_SOC_EXPANSION3_BASE 0x40000000
#define SCP_PERIPHERAL_BASE 0x44000000
#define SCP_PIK_BASE 0x50000000
#define SCP_SYSTEM_ACCESS_PORT1_BASE 0xA0000000
diff --git a/product/rdn2/include/scp_soc_mmap.h b/product/rdn2/include/scp_soc_mmap.h
index 68265847..056ddb58 100644
--- a/product/rdn2/include/scp_soc_mmap.h
+++ b/product/rdn2/include/scp_soc_mmap.h
@@ -12,4 +12,27 @@
#define SCP_NOR0_FLASH_BASE (SCP_SOC_EXPANSION1_BASE + 0x07000000)
+#define SCP_PLL_BASE (SCP_SOC_EXPANSION3_BASE + 0x03000000)
+
+#define SCP_PLL_SYSPLL (SCP_PLL_BASE + 0x00000000)
+#define SCP_PLL_DMC (SCP_PLL_BASE + 0x00000010)
+#define SCP_PLL_INTERCONNECT (SCP_PLL_BASE + 0x00000020)
+
+#define SCP_PLL_CPU0 (SCP_PLL_BASE + 0x00000100)
+#define SCP_PLL_CPU1 (SCP_PLL_BASE + 0x00000104)
+#define SCP_PLL_CPU2 (SCP_PLL_BASE + 0x00000108)
+#define SCP_PLL_CPU3 (SCP_PLL_BASE + 0x0000010C)
+#define SCP_PLL_CPU4 (SCP_PLL_BASE + 0x00000110)
+#define SCP_PLL_CPU5 (SCP_PLL_BASE + 0x00000114)
+#define SCP_PLL_CPU6 (SCP_PLL_BASE + 0x00000118)
+#define SCP_PLL_CPU7 (SCP_PLL_BASE + 0x0000011C)
+#define SCP_PLL_CPU8 (SCP_PLL_BASE + 0x00000120)
+#define SCP_PLL_CPU9 (SCP_PLL_BASE + 0x00000124)
+#define SCP_PLL_CPU10 (SCP_PLL_BASE + 0x00000128)
+#define SCP_PLL_CPU11 (SCP_PLL_BASE + 0x0000012c)
+#define SCP_PLL_CPU12 (SCP_PLL_BASE + 0x00000130)
+#define SCP_PLL_CPU13 (SCP_PLL_BASE + 0x00000134)
+#define SCP_PLL_CPU14 (SCP_PLL_BASE + 0x00000138)
+#define SCP_PLL_CPU15 (SCP_PLL_BASE + 0x0000013C)
+
#endif /* SCP_SOC_MMAP_H */
diff --git a/product/rdn2/scp_ramfw/config_system_pll.c b/product/rdn2/scp_ramfw/config_system_pll.c
new file mode 100644
index 00000000..40684a42
--- /dev/null
+++ b/product/rdn2/scp_ramfw/config_system_pll.c
@@ -0,0 +1,260 @@
+/*
+ * Arm SCP/MCP Software
+ * Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "clock_soc.h"
+#include "scp_pik.h"
+#include "scp_soc_mmap.h"
+
+#include <mod_system_pll.h>
+
+#include <fwk_element.h>
+#include <fwk_id.h>
+#include <fwk_macros.h>
+#include <fwk_module.h>
+
+static const struct fwk_element system_pll_element_table[] = {
+ [CLOCK_PLL_IDX_CPU0] = {
+ .name = "CPU_PLL_0",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_CPU0,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+ .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(0),
+ .initial_rate = 2600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_CPU1] = {
+ .name = "CPU_PLL_1",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_CPU1,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+ .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(1),
+ .initial_rate = 2600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_CPU2] = {
+ .name = "CPU_PLL_2",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_CPU2,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+ .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(2),
+ .initial_rate = 2600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_CPU3] = {
+ .name = "CPU_PLL_3",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_CPU3,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+ .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(3),
+ .initial_rate = 2600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_CPU4] = {
+ .name = "CPU_PLL_4",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_CPU4,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+ .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(4),
+ .initial_rate = 2600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_CPU5] = {
+ .name = "CPU_PLL_5",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_CPU5,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+ .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(5),
+ .initial_rate = 2600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_CPU6] = {
+ .name = "CPU_PLL_6",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_CPU6,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+ .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(6),
+ .initial_rate = 2600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_CPU7] = {
+ .name = "CPU_PLL_7",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_CPU7,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+ .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(7),
+ .initial_rate = 2600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_CPU8] = {
+ .name = "CPU_PLL_8",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_CPU8,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+ .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(8),
+ .initial_rate = 2600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_CPU9] = {
+ .name = "CPU_PLL_9",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_CPU9,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+ .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(9),
+ .initial_rate = 2600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_CPU10] = {
+ .name = "CPU_PLL_10",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_CPU10,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+ .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(10),
+ .initial_rate = 2600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_CPU11] = {
+ .name = "CPU_PLL_11",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_CPU11,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+ .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(11),
+ .initial_rate = 2600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_CPU12] = {
+ .name = "CPU_PLL_12",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_CPU12,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+ .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(12),
+ .initial_rate = 2600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_CPU13] = {
+ .name = "CPU_PLL_13",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_CPU13,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+ .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(13),
+ .initial_rate = 2600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_CPU14] = {
+ .name = "CPU_PLL_14",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_CPU14,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+ .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(14),
+ .initial_rate = 2600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_CPU15] = {
+ .name = "CPU_PLL_15",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_CPU15,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[1],
+ .lock_flag_mask = PLL_STATUS_CPUPLLLOCK(15),
+ .initial_rate = 2600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+
+ [CLOCK_PLL_IDX_SYS] = {
+ .name = "SYS_PLL",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_SYSPLL,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0],
+ .lock_flag_mask = PLL_STATUS_0_SYSPLLLOCK,
+ .initial_rate = 2000 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_DMC] = {
+ .name = "DMC_PLL",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_DMC,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0],
+ .lock_flag_mask = PLL_STATUS_0_DDRPLLLOCK,
+ .initial_rate = 1600 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_INTERCONNECT] = {
+ .name = "INT_PLL",
+ .data = &((struct mod_system_pll_dev_config) {
+ .control_reg = (void *)SCP_PLL_INTERCONNECT,
+ .status_reg = (void *)&SCP_PIK_PTR->PLL_STATUS[0],
+ .lock_flag_mask = PLL_STATUS_0_INTPLLLOCK,
+ .initial_rate = 2000 * FWK_MHZ,
+ .min_rate = MOD_SYSTEM_PLL_MIN_RATE,
+ .max_rate = MOD_SYSTEM_PLL_MAX_RATE,
+ .min_step = MOD_SYSTEM_PLL_MIN_INTERVAL,
+ }),
+ },
+ [CLOCK_PLL_IDX_COUNT] = { 0 }, /* Termination description. */
+};
+
+static const struct fwk_element *system_pll_get_element_table
+ (fwk_id_t module_id)
+{
+ return system_pll_element_table;
+}
+
+const struct fwk_module_config config_system_pll = {
+ .elements = FWK_MODULE_DYNAMIC_ELEMENTS(system_pll_get_element_table),
+};
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 10:55:56 +0000