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-rw-r--r--product/tc0/include/clock_soc.h4
-rw-r--r--product/tc0/include/cpu_pik.h109
-rw-r--r--product/tc0/include/dpu_pik.h50
-rw-r--r--product/tc0/include/scp_css_mmap.h43
-rw-r--r--product/tc0/include/scp_mmap.h14
-rw-r--r--product/tc0/include/scp_pik.h157
-rw-r--r--product/tc0/include/scp_soc_mmap.h20
-rw-r--r--product/tc0/include/scp_software_mmap.h49
-rw-r--r--product/tc0/include/system_pik.h100
-rw-r--r--product/tc0/include/tc0_core.h6
-rw-r--r--product/tc0/include/tc0_power_domain.h11
-rw-r--r--product/tc0/include/tc0_sds.h37
12 files changed, 291 insertions, 309 deletions
diff --git a/product/tc0/include/clock_soc.h b/product/tc0/include/clock_soc.h
index d129c872..1303cf5f 100644
--- a/product/tc0/include/clock_soc.h
+++ b/product/tc0/include/clock_soc.h
@@ -10,8 +10,8 @@
#include <fwk_macros.h>
-#define CLOCK_RATE_REFCLK (100UL * FWK_MHZ)
-#define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ)
+#define CLOCK_RATE_REFCLK (100UL * FWK_MHZ)
+#define CLOCK_RATE_SYSPLLCLK (2000UL * FWK_MHZ)
/*
* PLL clock indexes.
diff --git a/product/tc0/include/cpu_pik.h b/product/tc0/include/cpu_pik.h
index 5ec66456..ab3fd95a 100644
--- a/product/tc0/include/cpu_pik.h
+++ b/product/tc0/include/cpu_pik.h
@@ -14,78 +14,77 @@
#include <stdint.h>
-
/*!
* \brief PE Static Configuration register definitions
*/
struct static_config_reg {
- FWK_RW uint32_t STATIC_CONFIG;
- FWK_RW uint32_t RVBARADDR_LW;
- FWK_RW uint32_t RVBARADDR_UP;
- uint32_t RESERVED;
+ FWK_RW uint32_t STATIC_CONFIG;
+ FWK_RW uint32_t RVBARADDR_LW;
+ FWK_RW uint32_t RVBARADDR_UP;
+ uint32_t RESERVED;
};
/*!
* \brief AP cores clock control register definitions
*/
struct coreclk_reg {
- FWK_RW uint32_t CTRL;
- FWK_RW uint32_t DIV;
- uint32_t RESERVED;
- FWK_RW uint32_t MOD;
+ FWK_RW uint32_t CTRL;
+ FWK_RW uint32_t DIV;
+ uint32_t RESERVED;
+ FWK_RW uint32_t MOD;
};
/*!
* \brief CPU (V8.2) PIK register definitions
*/
struct pik_cpu_reg {
- FWK_RW uint32_t CLUSTER_CONFIG;
- uint8_t RESERVED0[0x10 - 0x4];
+ FWK_RW uint32_t CLUSTER_CONFIG;
+ uint8_t RESERVED0[0x10 - 0x4];
struct static_config_reg STATIC_CONFIG[16];
- uint8_t RESERVED1[0x800 - 0x110];
- FWK_RW uint32_t PPUCLK_CTRL;
- FWK_RW uint32_t PPUCLK_DIV1;
- uint8_t RESERVED2[0x810 - 0x808];
- FWK_RW uint32_t PCLK_CTRL;
- uint8_t RESERVED3[0x820 - 0x814];
- FWK_RW uint32_t DBGCLK_CTRL;
- FWK_RW uint32_t DBGCLK_DIV1;
- uint8_t RESERVED4[0x830 - 0x828];
- FWK_RW uint32_t GICCLK_CTRL;
- uint8_t RESERVED5[0x840 - 0x834];
- FWK_RW uint32_t AMBACLK_CTRL;
- uint8_t RESERVED6[0x850 - 0x844];
- FWK_RW uint32_t CLUSCLK_CTRL;
- FWK_RW uint32_t CLUSCLK_DIV1;
- uint8_t RESERVED7[0x860 - 0x858];
- struct coreclk_reg CORECLK[8];
- uint8_t RESERVED8[0xA00 - 0x8E0];
- FWK_R uint32_t CLKFORCE_STATUS;
- FWK_W uint32_t CLKFORCE_SET;
- FWK_W uint32_t CLKFORCE_CLR;
- uint8_t RESERVED9[0xB00 - 0xA0C];
- FWK_R uint32_t NERRIQ_INT_STATUS;
- FWK_R uint32_t NFAULTIQ_INT_STATUS;
- uint8_t RESERVED10[0xFB4 - 0xB08];
- FWK_R uint32_t CAP3;
- FWK_R uint32_t CAP2;
- FWK_R uint32_t CAP;
- FWK_R uint32_t PCL_CONFIG;
- uint8_t RESERVED11[0xFD0 - 0xFC4];
- FWK_R uint32_t PID4;
- FWK_R uint32_t PID5;
- FWK_R uint32_t PID6;
- FWK_R uint32_t PID7;
- FWK_R uint32_t PID0;
- FWK_R uint32_t PID1;
- FWK_R uint32_t PID2;
- FWK_R uint32_t PID3;
- FWK_R uint32_t ID0;
- FWK_R uint32_t ID1;
- FWK_R uint32_t ID2;
- FWK_R uint32_t ID3;
+ uint8_t RESERVED1[0x800 - 0x110];
+ FWK_RW uint32_t PPUCLK_CTRL;
+ FWK_RW uint32_t PPUCLK_DIV1;
+ uint8_t RESERVED2[0x810 - 0x808];
+ FWK_RW uint32_t PCLK_CTRL;
+ uint8_t RESERVED3[0x820 - 0x814];
+ FWK_RW uint32_t DBGCLK_CTRL;
+ FWK_RW uint32_t DBGCLK_DIV1;
+ uint8_t RESERVED4[0x830 - 0x828];
+ FWK_RW uint32_t GICCLK_CTRL;
+ uint8_t RESERVED5[0x840 - 0x834];
+ FWK_RW uint32_t AMBACLK_CTRL;
+ uint8_t RESERVED6[0x850 - 0x844];
+ FWK_RW uint32_t CLUSCLK_CTRL;
+ FWK_RW uint32_t CLUSCLK_DIV1;
+ uint8_t RESERVED7[0x860 - 0x858];
+ struct coreclk_reg CORECLK[8];
+ uint8_t RESERVED8[0xA00 - 0x8E0];
+ FWK_R uint32_t CLKFORCE_STATUS;
+ FWK_W uint32_t CLKFORCE_SET;
+ FWK_W uint32_t CLKFORCE_CLR;
+ uint8_t RESERVED9[0xB00 - 0xA0C];
+ FWK_R uint32_t NERRIQ_INT_STATUS;
+ FWK_R uint32_t NFAULTIQ_INT_STATUS;
+ uint8_t RESERVED10[0xFB4 - 0xB08];
+ FWK_R uint32_t CAP3;
+ FWK_R uint32_t CAP2;
+ FWK_R uint32_t CAP;
+ FWK_R uint32_t PCL_CONFIG;
+ uint8_t RESERVED11[0xFD0 - 0xFC4];
+ FWK_R uint32_t PID4;
+ FWK_R uint32_t PID5;
+ FWK_R uint32_t PID6;
+ FWK_R uint32_t PID7;
+ FWK_R uint32_t PID0;
+ FWK_R uint32_t PID1;
+ FWK_R uint32_t PID2;
+ FWK_R uint32_t PID3;
+ FWK_R uint32_t ID0;
+ FWK_R uint32_t ID1;
+ FWK_R uint32_t ID2;
+ FWK_R uint32_t ID3;
};
-#define CLUSTER_PIK_PTR(IDX) ((struct pik_cpu_reg *) SCP_PIK_CLUSTER_BASE(IDX))
+#define CLUSTER_PIK_PTR(IDX) ((struct pik_cpu_reg *)SCP_PIK_CLUSTER_BASE(IDX))
-#endif /* CPU_PIK_H */
+#endif /* CPU_PIK_H */
diff --git a/product/tc0/include/dpu_pik.h b/product/tc0/include/dpu_pik.h
index bce45dbb..25af0404 100644
--- a/product/tc0/include/dpu_pik.h
+++ b/product/tc0/include/dpu_pik.h
@@ -18,31 +18,31 @@
* \brief DPU PIK register definitions
*/
struct pik_dpu_reg {
- FWK_R uint8_t RESERVED0[0x830];
- FWK_RW uint32_t ACLKDP_CTRL;
- FWK_RW uint32_t ACLKDP_DIV1;
- FWK_RW uint32_t ACLKDP_DIV2;
- uint8_t RESERVED3[0xA00 - 0x83C];
- FWK_R uint32_t CLKFORCE_STATUS;
- FWK_W uint32_t CLKFORCE_SET;
- FWK_W uint32_t CLKFORCE_CLR;
- uint8_t RESERVED4[0xFC0 - 0xA0C];
- FWK_RW uint32_t PCL_CONFIG;
- uint8_t RESERVED5[0xFD0 - 0xFC4];
- FWK_R uint32_t PID4;
- FWK_R uint32_t PID5;
- FWK_R uint32_t PID6;
- FWK_R uint32_t PID7;
- FWK_R uint32_t PID0;
- FWK_R uint32_t PID1;
- FWK_R uint32_t PID2;
- FWK_R uint32_t PID3;
- FWK_R uint32_t ID0;
- FWK_R uint32_t ID1;
- FWK_R uint32_t ID2;
- FWK_R uint32_t ID3;
+ FWK_R uint8_t RESERVED0[0x830];
+ FWK_RW uint32_t ACLKDP_CTRL;
+ FWK_RW uint32_t ACLKDP_DIV1;
+ FWK_RW uint32_t ACLKDP_DIV2;
+ uint8_t RESERVED3[0xA00 - 0x83C];
+ FWK_R uint32_t CLKFORCE_STATUS;
+ FWK_W uint32_t CLKFORCE_SET;
+ FWK_W uint32_t CLKFORCE_CLR;
+ uint8_t RESERVED4[0xFC0 - 0xA0C];
+ FWK_RW uint32_t PCL_CONFIG;
+ uint8_t RESERVED5[0xFD0 - 0xFC4];
+ FWK_R uint32_t PID4;
+ FWK_R uint32_t PID5;
+ FWK_R uint32_t PID6;
+ FWK_R uint32_t PID7;
+ FWK_R uint32_t PID0;
+ FWK_R uint32_t PID1;
+ FWK_R uint32_t PID2;
+ FWK_R uint32_t PID3;
+ FWK_R uint32_t ID0;
+ FWK_R uint32_t ID1;
+ FWK_R uint32_t ID2;
+ FWK_R uint32_t ID3;
};
-#define DPU_PIK_PTR ((struct pik_dpu_reg *) SCP_PIK_DPU_BASE)
+#define DPU_PIK_PTR ((struct pik_dpu_reg *)SCP_PIK_DPU_BASE)
-#endif /* DPU_PIK_H */
+#endif /* DPU_PIK_H */
diff --git a/product/tc0/include/scp_css_mmap.h b/product/tc0/include/scp_css_mmap.h
index f9f7975b..301c4d43 100644
--- a/product/tc0/include/scp_css_mmap.h
+++ b/product/tc0/include/scp_css_mmap.h
@@ -10,35 +10,32 @@
#include "scp_mmap.h"
-#define SCP_CMN_BOOKER_BASE (SCP_SYSTEM_ACCESS_PORT0_BASE + 0x10000000)
+#define SCP_CMN_BOOKER_BASE (SCP_SYSTEM_ACCESS_PORT0_BASE + 0x10000000)
-#define SCP_REFCLK_CNTCONTROL_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x2A430000)
-#define SCP_REFCLK_CNTCTL_BASE (SCP_PERIPHERAL_BASE + 0x0000)
-#define SCP_REFCLK_CNTBASE0_BASE (SCP_PERIPHERAL_BASE + 0x1000)
-#define SCP_UART_BASE (SCP_PERIPHERAL_BASE + 0x2000)
-#define SCP_MHU_AP_BASE (SCP_PERIPHERAL_BASE + 0x1000000)
+#define SCP_REFCLK_CNTCONTROL_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x2A430000)
+#define SCP_REFCLK_CNTCTL_BASE (SCP_PERIPHERAL_BASE + 0x0000)
+#define SCP_REFCLK_CNTBASE0_BASE (SCP_PERIPHERAL_BASE + 0x1000)
+#define SCP_UART_BASE (SCP_PERIPHERAL_BASE + 0x2000)
+#define SCP_MHU_AP_BASE (SCP_PERIPHERAL_BASE + 0x1000000)
-#define SCP_PIK_SCP_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE)
-#define SCP_PIK_CLUSTER_BASE(n) ((SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE \
- + 0x60000) + ((n) * 0x20000))
-#define SCP_PIK_SYSTEM_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE \
- + 0x40000)
+#define SCP_PIK_SCP_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE)
+#define SCP_PIK_CLUSTER_BASE(n) \
+ ((SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x60000) + ((n)*0x20000))
+#define SCP_PIK_SYSTEM_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x40000)
-#define SCP_PIK_DPU_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE \
- + 0x860000)
+#define SCP_PIK_DPU_BASE (SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE + 0x860000)
-#define SCP_PPU_CLUSTER_BASE(n) (SCP_PIK_CLUSTER_BASE((n)) + 0x1000)
-#define SCP_PPU_CORE_BASE(n, m) (SCP_PPU_CLUSTER_BASE((n)) + \
- ((m) + 1) * 0x1000)
+#define SCP_PPU_CLUSTER_BASE(n) (SCP_PIK_CLUSTER_BASE((n)) + 0x1000)
+#define SCP_PPU_CORE_BASE(n, m) (SCP_PPU_CLUSTER_BASE((n)) + ((m) + 1) * 0x1000)
-#define SCP_PPU_SYS0_BASE (SCP_PIK_SYSTEM_BASE + 0x1000)
-#define SCP_PPU_SYS1_BASE (SCP_PIK_SYSTEM_BASE + 0x5000)
+#define SCP_PPU_SYS0_BASE (SCP_PIK_SYSTEM_BASE + 0x1000)
+#define SCP_PPU_SYS1_BASE (SCP_PIK_SYSTEM_BASE + 0x5000)
-#define SCP_PPU_BASE(n) (SCP_PIK_CLUSTER_BASE(n) + 0x2000)
+#define SCP_PPU_BASE(n) (SCP_PIK_CLUSTER_BASE(n) + 0x2000)
-#define SCP_MHU_SCP_AP_SND_NS_CLUS0 (SCP_MHU_AP_BASE + 0x00000)
-#define SCP_MHU_SCP_AP_RCV_NS_CLUS0 (SCP_MHU_AP_BASE + 0x10000)
-#define SCP_MHU_SCP_AP_SND_S_CLUS0 (SCP_MHU_AP_BASE + 0x400000)
-#define SCP_MHU_SCP_AP_RCV_S_CLUS0 (SCP_MHU_AP_BASE + 0x410000)
+#define SCP_MHU_SCP_AP_SND_NS_CLUS0 (SCP_MHU_AP_BASE + 0x00000)
+#define SCP_MHU_SCP_AP_RCV_NS_CLUS0 (SCP_MHU_AP_BASE + 0x10000)
+#define SCP_MHU_SCP_AP_SND_S_CLUS0 (SCP_MHU_AP_BASE + 0x400000)
+#define SCP_MHU_SCP_AP_RCV_S_CLUS0 (SCP_MHU_AP_BASE + 0x410000)
#endif /* SCP_CSS_MMAP_H */
diff --git a/product/tc0/include/scp_mmap.h b/product/tc0/include/scp_mmap.h
index e048ce7a..68bc7ad1 100644
--- a/product/tc0/include/scp_mmap.h
+++ b/product/tc0/include/scp_mmap.h
@@ -8,13 +8,13 @@
#ifndef SCP_MMAP_H
#define SCP_MMAP_H
-#define SCP_BOOT_ROM_BASE 0x00000000
-#define SCP_ITC_RAM_BASE 0x00800000
-#define SCP_DTC_RAM_BASE 0x20000000
-#define SCP_SOC_EXPANSION3_BASE 0x40000000
-#define SCP_PERIPHERAL_BASE 0x44000000
+#define SCP_BOOT_ROM_BASE 0x00000000
+#define SCP_ITC_RAM_BASE 0x00800000
+#define SCP_DTC_RAM_BASE 0x20000000
+#define SCP_SOC_EXPANSION3_BASE 0x40000000
+#define SCP_PERIPHERAL_BASE 0x44000000
#define SCP_ELEMENT_MANAGEMENT_PERIPHERAL_BASE 0x50000000
-#define SCP_SYSTEM_ACCESS_PORT0_BASE 0x60000000
-#define SCP_SYSTEM_ACCESS_PORT1_BASE 0xA0000000
+#define SCP_SYSTEM_ACCESS_PORT0_BASE 0x60000000
+#define SCP_SYSTEM_ACCESS_PORT1_BASE 0xA0000000
#endif /* SCP_MMAP_H */
diff --git a/product/tc0/include/scp_pik.h b/product/tc0/include/scp_pik.h
index a90efda9..1a6df42c 100644
--- a/product/tc0/include/scp_pik.h
+++ b/product/tc0/include/scp_pik.h
@@ -21,88 +21,87 @@
* \brief SCP PIK register definitions
*/
struct pik_scp_reg {
- uint8_t RESERVED0[0x10 - 0x0];
- FWK_RW uint32_t RESET_SYNDROME;
- uint8_t RESERVED1[0x20 - 0x14];
- FWK_RW uint32_t SURVIVAL_RESET_STATUS;
- uint8_t RESERVED2[0x34 - 0x24];
- FWK_RW uint32_t ADDR_TRANS;
- FWK_RW uint32_t DBG_ADDR_TRANS;
- uint8_t RESERVED3[0x40 - 0x3C];
- FWK_RW uint32_t WS1_TIMER_MATCH;
- FWK_RW uint32_t WS1_TIMER_EN;
- uint8_t RESERVED4[0x200 - 0x48];
- FWK_R uint32_t SS_RESET_STATUS;
- FWK_W uint32_t SS_RESET_SET;
- FWK_W uint32_t SS_RESET_CLR;
- uint8_t RESERVED5[0x810 - 0x20C];
- FWK_RW uint32_t CORECLK_CTRL;
- FWK_RW uint32_t CORECLK_DIV1;
- uint8_t RESERVED6[0x820 - 0x818];
- FWK_RW uint32_t ACLK_CTRL;
- FWK_RW uint32_t ACLK_DIV1;
- uint8_t RESERVED7[0x830 - 0x828];
- FWK_RW uint32_t GTSYNCCLK_CTRL;
- FWK_RW uint32_t GTSYNCCLK_DIV1;
- uint8_t RESERVED8[0xA10 - 0x838];
- FWK_R uint32_t PLL_STATUS[17];
- uint8_t RESERVED9[0xA60 - 0xA54];
- FWK_R uint32_t CONS_MMUTCU_INT_STATUS;
- FWK_R uint32_t CONS_MMUTBU_INT_STATUS0;
- FWK_R uint32_t CONS_MMUTBU_INT_STATUS1;
- FWK_W uint32_t CONS_MMUTCU_INT_CLR;
- FWK_W uint32_t CONS_MMUTBU_INT_CLR0;
- FWK_W uint32_t CONS_MMUTBU_INT_CLR1;
- uint8_t RESERVED10[0xB00 - 0xA78];
- FWK_R uint32_t MHU_NS_INT_STATUS;
- FWK_R uint32_t MHU_S_INT_STATUS;
- uint8_t RESERVED11[0xB20 - 0xB08];
- FWK_R uint32_t CPU_PPU_INT_STATUS[8];
- FWK_R uint32_t CLUS_PPU_INT_STATUS;
- uint8_t RESERVED12[0xB60 - 0xB44];
- FWK_R uint32_t TIMER_INT_STATUS[8];
- FWK_R uint32_t CPU_PLL_LOCK_STATUS[8];
- uint8_t RESERVED13[0xBC0 - 0xBA0];
- FWK_R uint32_t CPU_PLL_UNLOCK_STATUS[8];
- uint8_t RESERVED14[0xBF0 - 0xBE0];
- FWK_R uint32_t CLUSTER_PLL_LOCK_STATUS;
- FWK_R uint32_t CLUSTER_PLL_UNLOCK_STATUS;
- uint8_t RESERVED15[0xC00 - 0xBF8];
- FWK_R uint32_t CLUS_FAULT_INT_STATUS;
- uint8_t RESERVED16[0xC30 - 0xC04];
- FWK_R uint32_t CLUSTER_ECCERR_INT_STATUS;
- uint8_t RESERVED17[0xD00 - 0xC34];
- FWK_R uint32_t DMC0_4_INT_STATUS;
- FWK_R uint32_t DMC1_5_INT_STATUS;
- FWK_R uint32_t DMC2_6_INT_STATUS;
- FWK_R uint32_t DMC3_7_INT_STATUS;
- uint8_t RESERVED18[0xFC0 - 0xD10];
- FWK_R uint32_t PCL_CFG;
- uint8_t RESERVED19[0xFD0 - 0xFC4];
- FWK_R uint32_t PID4;
- FWK_R uint32_t PID5;
- FWK_R uint32_t PID6;
- FWK_R uint32_t PID7;
- FWK_R uint32_t PID0;
- FWK_R uint32_t PID1;
- FWK_R uint32_t PID2;
- FWK_R uint32_t PID3;
- FWK_R uint32_t ID0;
- FWK_R uint32_t ID1;
- FWK_R uint32_t ID2;
- FWK_R uint32_t ID3;
+ uint8_t RESERVED0[0x10 - 0x0];
+ FWK_RW uint32_t RESET_SYNDROME;
+ uint8_t RESERVED1[0x20 - 0x14];
+ FWK_RW uint32_t SURVIVAL_RESET_STATUS;
+ uint8_t RESERVED2[0x34 - 0x24];
+ FWK_RW uint32_t ADDR_TRANS;
+ FWK_RW uint32_t DBG_ADDR_TRANS;
+ uint8_t RESERVED3[0x40 - 0x3C];
+ FWK_RW uint32_t WS1_TIMER_MATCH;
+ FWK_RW uint32_t WS1_TIMER_EN;
+ uint8_t RESERVED4[0x200 - 0x48];
+ FWK_R uint32_t SS_RESET_STATUS;
+ FWK_W uint32_t SS_RESET_SET;
+ FWK_W uint32_t SS_RESET_CLR;
+ uint8_t RESERVED5[0x810 - 0x20C];
+ FWK_RW uint32_t CORECLK_CTRL;
+ FWK_RW uint32_t CORECLK_DIV1;
+ uint8_t RESERVED6[0x820 - 0x818];
+ FWK_RW uint32_t ACLK_CTRL;
+ FWK_RW uint32_t ACLK_DIV1;
+ uint8_t RESERVED7[0x830 - 0x828];
+ FWK_RW uint32_t GTSYNCCLK_CTRL;
+ FWK_RW uint32_t GTSYNCCLK_DIV1;
+ uint8_t RESERVED8[0xA10 - 0x838];
+ FWK_R uint32_t PLL_STATUS[17];
+ uint8_t RESERVED9[0xA60 - 0xA54];
+ FWK_R uint32_t CONS_MMUTCU_INT_STATUS;
+ FWK_R uint32_t CONS_MMUTBU_INT_STATUS0;
+ FWK_R uint32_t CONS_MMUTBU_INT_STATUS1;
+ FWK_W uint32_t CONS_MMUTCU_INT_CLR;
+ FWK_W uint32_t CONS_MMUTBU_INT_CLR0;
+ FWK_W uint32_t CONS_MMUTBU_INT_CLR1;
+ uint8_t RESERVED10[0xB00 - 0xA78];
+ FWK_R uint32_t MHU_NS_INT_STATUS;
+ FWK_R uint32_t MHU_S_INT_STATUS;
+ uint8_t RESERVED11[0xB20 - 0xB08];
+ FWK_R uint32_t CPU_PPU_INT_STATUS[8];
+ FWK_R uint32_t CLUS_PPU_INT_STATUS;
+ uint8_t RESERVED12[0xB60 - 0xB44];
+ FWK_R uint32_t TIMER_INT_STATUS[8];
+ FWK_R uint32_t CPU_PLL_LOCK_STATUS[8];
+ uint8_t RESERVED13[0xBC0 - 0xBA0];
+ FWK_R uint32_t CPU_PLL_UNLOCK_STATUS[8];
+ uint8_t RESERVED14[0xBF0 - 0xBE0];
+ FWK_R uint32_t CLUSTER_PLL_LOCK_STATUS;
+ FWK_R uint32_t CLUSTER_PLL_UNLOCK_STATUS;
+ uint8_t RESERVED15[0xC00 - 0xBF8];
+ FWK_R uint32_t CLUS_FAULT_INT_STATUS;
+ uint8_t RESERVED16[0xC30 - 0xC04];
+ FWK_R uint32_t CLUSTER_ECCERR_INT_STATUS;
+ uint8_t RESERVED17[0xD00 - 0xC34];
+ FWK_R uint32_t DMC0_4_INT_STATUS;
+ FWK_R uint32_t DMC1_5_INT_STATUS;
+ FWK_R uint32_t DMC2_6_INT_STATUS;
+ FWK_R uint32_t DMC3_7_INT_STATUS;
+ uint8_t RESERVED18[0xFC0 - 0xD10];
+ FWK_R uint32_t PCL_CFG;
+ uint8_t RESERVED19[0xFD0 - 0xFC4];
+ FWK_R uint32_t PID4;
+ FWK_R uint32_t PID5;
+ FWK_R uint32_t PID6;
+ FWK_R uint32_t PID7;
+ FWK_R uint32_t PID0;
+ FWK_R uint32_t PID1;
+ FWK_R uint32_t PID2;
+ FWK_R uint32_t PID3;
+ FWK_R uint32_t ID0;
+ FWK_R uint32_t ID1;
+ FWK_R uint32_t ID2;
+ FWK_R uint32_t ID3;
};
-#define PLL_STATUS_0_REFCLK UINT32_C(0x00000001)
-#define PLL_STATUS_0_SYSPLLLOCK UINT32_C(0x00000002)
-#define PLL_STATUS_0_DDRPLLLOCK UINT32_C(0x00000004)
-#define PLL_STATUS_0_INTPLLLOCK UINT32_C(0x00000008)
-#define PLL_STATUS_0_DISPLAYPLLLOCK UINT32_C(0x00000040)
+#define PLL_STATUS_0_REFCLK UINT32_C(0x00000001)
+#define PLL_STATUS_0_SYSPLLLOCK UINT32_C(0x00000002)
+#define PLL_STATUS_0_DDRPLLLOCK UINT32_C(0x00000004)
+#define PLL_STATUS_0_INTPLLLOCK UINT32_C(0x00000008)
+#define PLL_STATUS_0_DISPLAYPLLLOCK UINT32_C(0x00000040)
-
-#define PLL_STATUS_CPUPLLLOCK(CPU) ((uint32_t)(1 << (CPU % 32)))
+#define PLL_STATUS_CPUPLLLOCK(CPU) ((uint32_t)(1 << (CPU % 32)))
/* Pointer to SCP PIK */
-#define SCP_PIK_PTR ((struct pik_scp_reg *) SCP_PIK_SCP_BASE)
+#define SCP_PIK_PTR ((struct pik_scp_reg *)SCP_PIK_SCP_BASE)
-#endif /* SCP_PIK_H */
+#endif /* SCP_PIK_H */
diff --git a/product/tc0/include/scp_soc_mmap.h b/product/tc0/include/scp_soc_mmap.h
index e59924c3..433f9092 100644
--- a/product/tc0/include/scp_soc_mmap.h
+++ b/product/tc0/include/scp_soc_mmap.h
@@ -10,17 +10,17 @@
#include "scp_mmap.h"
-#define SCP_PLL_BASE (SCP_SOC_EXPANSION3_BASE + 0x03000000)
+#define SCP_PLL_BASE (SCP_SOC_EXPANSION3_BASE + 0x03000000)
-#define SCP_PLL_SYSPLL (SCP_PLL_BASE + 0x00000000)
-#define SCP_PLL_DISPLAY (SCP_PLL_BASE + 0x00000014)
-#define SCP_PLL_PIX0 (SCP_PLL_BASE + 0x00000018)
-#define SCP_PLL_PIX1 (SCP_PLL_BASE + 0x0000001C)
-#define SCP_PLL_INTERCONNECT (SCP_PLL_BASE + 0x00000020)
+#define SCP_PLL_SYSPLL (SCP_PLL_BASE + 0x00000000)
+#define SCP_PLL_DISPLAY (SCP_PLL_BASE + 0x00000014)
+#define SCP_PLL_PIX0 (SCP_PLL_BASE + 0x00000018)
+#define SCP_PLL_PIX1 (SCP_PLL_BASE + 0x0000001C)
+#define SCP_PLL_INTERCONNECT (SCP_PLL_BASE + 0x00000020)
-#define SCP_PLL_CPU0 (SCP_PLL_BASE + 0x00000100)
-#define SCP_PLL_CPU1 (SCP_PLL_BASE + 0x00000104)
-#define SCP_PLL_CPU2 (SCP_PLL_BASE + 0x00000108)
-#define SCP_PLL_CPU3 (SCP_PLL_BASE + 0x0000010C)
+#define SCP_PLL_CPU0 (SCP_PLL_BASE + 0x00000100)
+#define SCP_PLL_CPU1 (SCP_PLL_BASE + 0x00000104)
+#define SCP_PLL_CPU2 (SCP_PLL_BASE + 0x00000108)
+#define SCP_PLL_CPU3 (SCP_PLL_BASE + 0x0000010C)
#endif /* SCP_SOC_MMAP_H */
diff --git a/product/tc0/include/scp_software_mmap.h b/product/tc0/include/scp_software_mmap.h
index 12d75406..93eefe65 100644
--- a/product/tc0/include/scp_software_mmap.h
+++ b/product/tc0/include/scp_software_mmap.h
@@ -8,51 +8,46 @@
#ifndef SCP_SOFTWARE_MMAP_H
#define SCP_SOFTWARE_MMAP_H
-
#include "scp_soc_mmap.h"
#include <fwk_macros.h>
/* SCP ROM and RAM firmware size loaded on main memory */
-#define SCP_BOOT_ROM_SIZE (64 * 1024)
-#define SCP_DTC_RAM_SIZE (256 * 1024)
-#define SCP_ITC_RAM_SIZE (256 * 1024)
+#define SCP_BOOT_ROM_SIZE (64 * 1024)
+#define SCP_DTC_RAM_SIZE (256 * 1024)
+#define SCP_ITC_RAM_SIZE (256 * 1024)
/* SCP trusted and non-trusted RAM base address */
-#define SCP_TRUSTED_RAM_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + \
- 0x04000000)
-#define SCP_NONTRUSTED_RAM_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + \
- 0x06000000)
+#define SCP_TRUSTED_RAM_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x04000000)
+#define SCP_NONTRUSTED_RAM_BASE (SCP_SYSTEM_ACCESS_PORT1_BASE + 0x06000000)
/* Secure Shared memory between AP and SCP */
-#define SCP_AP_SHARED_SECURE_BASE (SCP_TRUSTED_RAM_BASE)
-#define SCP_AP_SHARED_SECURE_SIZE (4 * FWK_KIB)
+#define SCP_AP_SHARED_SECURE_BASE (SCP_TRUSTED_RAM_BASE)
+#define SCP_AP_SHARED_SECURE_SIZE (4 * FWK_KIB)
/* Non-secure Shared memory between AP and SCP */
-#define SCP_AP_SHARED_NONSECURE_BASE (SCP_NONTRUSTED_RAM_BASE)
-#define SCP_AP_SHARED_NONSECURE_SIZE (4 * FWK_KIB)
+#define SCP_AP_SHARED_NONSECURE_BASE (SCP_NONTRUSTED_RAM_BASE)
+#define SCP_AP_SHARED_NONSECURE_SIZE (4 * FWK_KIB)
/* AP Context Area */
-#define SCP_AP_CONTEXT_BASE (SCP_AP_SHARED_SECURE_BASE + \
- SCP_AP_SHARED_SECURE_SIZE - \
- SCP_AP_CONTEXT_SIZE)
-#define SCP_AP_CONTEXT_SIZE (64)
+#define SCP_AP_CONTEXT_BASE \
+ (SCP_AP_SHARED_SECURE_BASE + SCP_AP_SHARED_SECURE_SIZE - \
+ SCP_AP_CONTEXT_SIZE)
+#define SCP_AP_CONTEXT_SIZE (64)
/* SDS Memory Region */
-#define SCP_SDS_MEM_BASE (SCP_AP_SHARED_SECURE_BASE)
-#define SCP_SDS_MEM_SIZE (3520)
+#define SCP_SDS_MEM_BASE (SCP_AP_SHARED_SECURE_BASE)
+#define SCP_SDS_MEM_SIZE (3520)
/* SCMI Secure Payload Areas */
-#define SCP_SCMI_PAYLOAD_SIZE (128)
-#define SCP_SCMI_PAYLOAD_S_A2P_BASE (SCP_SDS_MEM_BASE + \
- SCP_SDS_MEM_SIZE)
-#define SCP_SCMI_PAYLOAD_S_P2A_BASE (SCP_SCMI_PAYLOAD_S_A2P_BASE + \
- SCP_SCMI_PAYLOAD_SIZE)
+#define SCP_SCMI_PAYLOAD_SIZE (128)
+#define SCP_SCMI_PAYLOAD_S_A2P_BASE (SCP_SDS_MEM_BASE + SCP_SDS_MEM_SIZE)
+#define SCP_SCMI_PAYLOAD_S_P2A_BASE \
+ (SCP_SCMI_PAYLOAD_S_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE)
/* SCMI Non-Secure Payload Areas */
-#define SCP_SCMI_PAYLOAD_NS_A2P_BASE (SCP_AP_SHARED_NONSECURE_BASE)
-#define SCP_SCMI_PAYLOAD_NS_P2A_BASE (SCP_SCMI_PAYLOAD_NS_A2P_BASE + \
- SCP_SCMI_PAYLOAD_SIZE)
-
+#define SCP_SCMI_PAYLOAD_NS_A2P_BASE (SCP_AP_SHARED_NONSECURE_BASE)
+#define SCP_SCMI_PAYLOAD_NS_P2A_BASE \
+ (SCP_SCMI_PAYLOAD_NS_A2P_BASE + SCP_SCMI_PAYLOAD_SIZE)
#endif /* SCP_SOFTWARE_MMAP_H */
diff --git a/product/tc0/include/system_pik.h b/product/tc0/include/system_pik.h
index d83bd1de..495d0af7 100644
--- a/product/tc0/include/system_pik.h
+++ b/product/tc0/include/system_pik.h
@@ -18,62 +18,62 @@
* \brief TCU clock register definitions
*/
struct tcuclk_ctrl_reg {
- FWK_RW uint32_t TCUCLK_CTRL;
- FWK_RW uint32_t TCUCLK_DIV1;
+ FWK_RW uint32_t TCUCLK_CTRL;
+ FWK_RW uint32_t TCUCLK_DIV1;
};
/*!
* \brief System PIK register definitions
*/
struct pik_system_reg {
- uint8_t RESERVED0[0x800 - 0x0];
- FWK_RW uint32_t PPUCLK_CTRL;
- FWK_RW uint32_t PPUCLK_DIV1;
- uint8_t RESERVED1[0x820 - 0x808];
- FWK_RW uint32_t INTCLK_CTRL;
- FWK_RW uint32_t INTCLK_DIV1;
- uint8_t RESERVED2[0x830 - 0x828];
- struct tcuclk_ctrl_reg TCUCLK[4];
- FWK_RW uint32_t GICCLK_CTRL;
- FWK_RW uint32_t GICCLK_DIV1;
- uint8_t RESERVED3[0x860 - 0x858];
- FWK_RW uint32_t PCLKSCP_CTRL;
- FWK_RW uint32_t PCLKSCP_DIV1;
- uint8_t RESERVED4[0x870 - 0x868];
- FWK_RW uint32_t SYSPERCLK_CTRL;
- FWK_RW uint32_t SYSPERCLK_DIV1;
- uint8_t RESERVED5[0x880 - 0x878];
- FWK_RW uint32_t DMCCLK_CTRL;
- FWK_RW uint32_t DMCCLK_DIV1;
- uint8_t RESERVED6[0x890 - 0x888];
- FWK_RW uint32_t SYSPCLKDBG_CTRL;
- FWK_RW uint32_t SYSPCLKDBG_DIV1;
- uint8_t RESERVED7[0x8A0 - 0x898];
- FWK_RW uint32_t UARTCLK_CTRL;
- FWK_RW uint32_t UARTCLK_DIV1;
- uint8_t RESERVED8[0xA00 - 0x8A8];
- FWK_R uint32_t CLKFORCE_STATUS;
- FWK_W uint32_t CLKFORCE_SET;
- FWK_W uint32_t CLKFORCE_CLR;
- uint8_t RESERVED9[0xB0C - 0xA0C];
- FWK_RW uint32_t SYSTOP_RST_DLY;
- uint8_t RESERVED10[0xFC0 - 0xB10];
- FWK_R uint32_t PCL_CONFIG;
- uint8_t RESERVED11[0xFD0 - 0xFC4];
- FWK_R uint32_t PID4;
- FWK_R uint32_t PID5;
- FWK_R uint32_t PID6;
- FWK_R uint32_t PID7;
- FWK_R uint32_t PID0;
- FWK_R uint32_t PID1;
- FWK_R uint32_t PID2;
- FWK_R uint32_t PID3;
- FWK_R uint32_t ID0;
- FWK_R uint32_t ID1;
- FWK_R uint32_t ID2;
- FWK_R uint32_t ID3;
+ uint8_t RESERVED0[0x800 - 0x0];
+ FWK_RW uint32_t PPUCLK_CTRL;
+ FWK_RW uint32_t PPUCLK_DIV1;
+ uint8_t RESERVED1[0x820 - 0x808];
+ FWK_RW uint32_t INTCLK_CTRL;
+ FWK_RW uint32_t INTCLK_DIV1;
+ uint8_t RESERVED2[0x830 - 0x828];
+ struct tcuclk_ctrl_reg TCUCLK[4];
+ FWK_RW uint32_t GICCLK_CTRL;
+ FWK_RW uint32_t GICCLK_DIV1;
+ uint8_t RESERVED3[0x860 - 0x858];
+ FWK_RW uint32_t PCLKSCP_CTRL;
+ FWK_RW uint32_t PCLKSCP_DIV1;
+ uint8_t RESERVED4[0x870 - 0x868];
+ FWK_RW uint32_t SYSPERCLK_CTRL;
+ FWK_RW uint32_t SYSPERCLK_DIV1;
+ uint8_t RESERVED5[0x880 - 0x878];
+ FWK_RW uint32_t DMCCLK_CTRL;
+ FWK_RW uint32_t DMCCLK_DIV1;
+ uint8_t RESERVED6[0x890 - 0x888];
+ FWK_RW uint32_t SYSPCLKDBG_CTRL;
+ FWK_RW uint32_t SYSPCLKDBG_DIV1;
+ uint8_t RESERVED7[0x8A0 - 0x898];
+ FWK_RW uint32_t UARTCLK_CTRL;
+ FWK_RW uint32_t UARTCLK_DIV1;
+ uint8_t RESERVED8[0xA00 - 0x8A8];
+ FWK_R uint32_t CLKFORCE_STATUS;
+ FWK_W uint32_t CLKFORCE_SET;
+ FWK_W uint32_t CLKFORCE_CLR;
+ uint8_t RESERVED9[0xB0C - 0xA0C];
+ FWK_RW uint32_t SYSTOP_RST_DLY;
+ uint8_t RESERVED10[0xFC0 - 0xB10];
+ FWK_R uint32_t PCL_CONFIG;
+ uint8_t RESERVED11[0xFD0 - 0xFC4];
+ FWK_R uint32_t PID4;
+ FWK_R uint32_t PID5;
+ FWK_R uint32_t PID6;
+ FWK_R uint32_t PID7;
+ FWK_R uint32_t PID0;
+ FWK_R uint32_t PID1;
+ FWK_R uint32_t PID2;
+ FWK_R uint32_t PID3;
+ FWK_R uint32_t ID0;
+ FWK_R uint32_t ID1;
+ FWK_R uint32_t ID2;
+ FWK_R uint32_t ID3;
};
-#define SYSTEM_PIK_PTR ((struct pik_system_reg *) SCP_PIK_SYSTEM_BASE)
+#define SYSTEM_PIK_PTR ((struct pik_system_reg *)SCP_PIK_SYSTEM_BASE)
-#endif /* SYSTEM_PIK_H */
+#endif /* SYSTEM_PIK_H */
diff --git a/product/tc0/include/tc0_core.h b/product/tc0/include/tc0_core.h
index 508e3883..493086e0 100644
--- a/product/tc0/include/tc0_core.h
+++ b/product/tc0/include/tc0_core.h
@@ -12,8 +12,8 @@
#define TC0_CORE_PER_CLUSTER_MAX 4
-#define CORES_PER_CLUSTER 4
-#define NUMBER_OF_CLUSTERS 1
+#define CORES_PER_CLUSTER 4
+#define NUMBER_OF_CLUSTERS 1
static inline unsigned int tc0_core_get_cluster_count(void)
{
@@ -31,7 +31,7 @@ static inline unsigned int tc0_core_get_core_per_cluster_count(
static inline unsigned int tc0_core_get_core_count(void)
{
return tc0_core_get_core_per_cluster_count(0) *
- tc0_core_get_cluster_count();
+ tc0_core_get_cluster_count();
}
#endif /* TC0_CORE_H */
diff --git a/product/tc0/include/tc0_power_domain.h b/product/tc0/include/tc0_power_domain.h
index f7ef2363..6eab1612 100644
--- a/product/tc0/include/tc0_power_domain.h
+++ b/product/tc0/include/tc0_power_domain.h
@@ -11,15 +11,10 @@
#include <mod_power_domain.h>
/*! Mask for the cluster valid power states */
-#define TC0_CLUSTER_VALID_STATE_MASK ( \
- MOD_PD_STATE_OFF_MASK | \
- MOD_PD_STATE_ON_MASK \
- )
+#define TC0_CLUSTER_VALID_STATE_MASK \
+ (MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK)
/*! Mask for the core valid power states */
-#define TC0_CORE_VALID_STATE_MASK ( \
- MOD_PD_STATE_OFF_MASK | \
- MOD_PD_STATE_ON_MASK \
- )
+#define TC0_CORE_VALID_STATE_MASK (MOD_PD_STATE_OFF_MASK | MOD_PD_STATE_ON_MASK)
#endif /* TC0_POWER_DOMAIN_H */
diff --git a/product/tc0/include/tc0_sds.h b/product/tc0/include/tc0_sds.h
index e8d9ae25..ccf0d864 100644
--- a/product/tc0/include/tc0_sds.h
+++ b/product/tc0/include/tc0_sds.h
@@ -19,44 +19,41 @@ enum tc0_sds_struct_id {
TC0_SDS_BOOTLOADER = 9 | (1 << MOD_SDS_ID_VERSION_MAJOR_POS),
};
-enum tc0_sds_region_idx {
- TC0_SDS_REGION_SECURE,
- TC0_SDS_REGION_COUNT
-};
+enum tc0_sds_region_idx { TC0_SDS_REGION_SECURE, TC0_SDS_REGION_COUNT };
/*
* Structure sizes.
*/
-#define TC0_SDS_CPU_INFO_SIZE 4
+#define TC0_SDS_CPU_INFO_SIZE 4
#define TC0_SDS_FEATURE_AVAILABILITY_SIZE 4
-#define TC0_SDS_BOOTLOADER_SIZE 12
+#define TC0_SDS_BOOTLOADER_SIZE 12
/*
* Field masks and offsets for TC0_SDS_AP_CPU_INFO structure.
*/
-#define TC0_SDS_CPU_INFO_PRIMARY_MASK 0xFFFFFFFF
-#define TC0_SDS_CPU_INFO_PRIMARY_POS 0
+#define TC0_SDS_CPU_INFO_PRIMARY_MASK 0xFFFFFFFF
+#define TC0_SDS_CPU_INFO_PRIMARY_POS 0
/*
* Field masks and offsets for TC0_SDS_FEATURE_AVAILABILITY structure.
*/
-#define TC0_SDS_FEATURE_FIRMWARE_MASK 0x1
-#define TC0_SDS_FEATURE_DMC_MASK 0x2
-#define TC0_SDS_FEATURE_MESSAGING_MASK 0x4
+#define TC0_SDS_FEATURE_FIRMWARE_MASK 0x1
+#define TC0_SDS_FEATURE_DMC_MASK 0x2
+#define TC0_SDS_FEATURE_MESSAGING_MASK 0x4
-#define TC0_SDS_FEATURE_FIRMWARE_POS 0
-#define TC0_SDS_FEATURE_DMC_POS 1
-#define TC0_SDS_FEATURE_MESSAGING_POS 2
+#define TC0_SDS_FEATURE_FIRMWARE_POS 0
+#define TC0_SDS_FEATURE_DMC_POS 1
+#define TC0_SDS_FEATURE_MESSAGING_POS 2
/*
* Field masks and offsets for the TC0_SDS_BOOTLOADER structure.
*/
-#define TC0_SDS_BOOTLOADER_VALID_MASK 0x1
-#define TC0_SDS_BOOTLOADER_OFFSET_MASK 0xFFFFFFFF
-#define TC0_SDS_BOOTLOADER_SIZE_MASK 0xFFFFFFFF
+#define TC0_SDS_BOOTLOADER_VALID_MASK 0x1
+#define TC0_SDS_BOOTLOADER_OFFSET_MASK 0xFFFFFFFF
+#define TC0_SDS_BOOTLOADER_SIZE_MASK 0xFFFFFFFF
-#define TC0_SDS_BOOTLOADER_VALID_POS 0
-#define TC0_SDS_BOOTLOADER_OFFSET_POS 0
-#define TC0_SDS_BOOTLOADER_SIZE_POS 0
+#define TC0_SDS_BOOTLOADER_VALID_POS 0
+#define TC0_SDS_BOOTLOADER_OFFSET_POS 0
+#define TC0_SDS_BOOTLOADER_SIZE_POS 0
#endif /* TC0_SDS_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 04:40:50 +0000